CN114665375A - Method for manufacturing semiconductor chip - Google Patents
Method for manufacturing semiconductor chip Download PDFInfo
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- CN114665375A CN114665375A CN202210565777.7A CN202210565777A CN114665375A CN 114665375 A CN114665375 A CN 114665375A CN 202210565777 A CN202210565777 A CN 202210565777A CN 114665375 A CN114665375 A CN 114665375A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
Abstract
The invention provides a semiconductor chip manufacturing method, and relates to the technical field of semiconductors. The manufacturing method of the semiconductor chip comprises dividing odd-numbered rows and even-numbered rows which are alternately distributed on the side surface of a wafer far away from a substrate and extend along the cavity surface direction of the semiconductor chip; forming first grooves with the bottoms extending to the wafer substrate in the odd rows, and plating a first film layer on the inner sides of the first grooves; second grooves which extend from the bottoms of the even rows to the wafer substrate and are arranged at intervals with the first grooves are formed in the even rows; plating a second film layer on the inner side of the second groove; the wafer is cleaved at the first grooves and the second grooves along the facet direction of the semiconductor chip to obtain a plurality of bars. According to the manufacturing method of the semiconductor chip, the busbar is firstly coated and then cleaved, so that water ripple-shaped cracks generated on the busbar can be prevented, the cavity surface of the semiconductor chip can be prevented from being exposed for a long time, and the busbar does not need to be turned over by using a clamp.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor chip manufacturing method.
Background
The wafer generally includes a substrate, an epitaxial layer, a passivation layer and an electrode, and semiconductor chips can be obtained by performing processes such as cleaving and plating on the wafer. In a conventional semiconductor chip manufacturing process, after an epitaxial layer, a protective layer and electrodes are sequentially grown on a wafer substrate, as shown in fig. 1 and 2, a wafer 1 is cleaved into bars 2 along a direction perpendicular to a cavity surface of the semiconductor chip (also along a direction parallel to a resonant cavity), and as shown in fig. 2 and 3, the bars 2 are cleaved into bars 3, each bar 3 may include one or more semiconductor chips. Then, as shown in fig. 4, cavity surface coating is performed on the bars 3 (coating the epitaxial layer side surface in the direction of the resonant cavity, coating the front cavity surface with an antireflection film, and coating the rear cavity surface with a reflection film to form the resonant cavity that allows the excited radiation photons to proliferate), and after the coating is completed, the bars are trimmed to obtain bars having a size meeting the requirements, as shown in fig. 5, so that the manufacturing process of the semiconductor chip can be completed.
However, in the manufacturing process of the semiconductor chip, the external force applied when the wafer is cleaved into the bar is perpendicular to the cavity surface of the semiconductor chip, which easily causes the water ripple-shaped cracks on the surface of the bar; the cavity surface of the semiconductor chip is exposed in the air for a long time during film coating, and the bar needs to be turned over by using a clamp during film coating, so that the bar is easily damaged and the operation efficiency is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor chip manufacturing method, which aims to relieve the problem that in the manufacturing process of semiconductor chips in the prior art, the external force applied when a wafer is cleaved into bars is vertical to the cavity surface of the semiconductor chip, so that the water ripple-shaped cracks are easily generated on the surface of the bars; the cavity surface of the semiconductor chip is exposed in the air for a long time during film coating, and the bar needs to be turned over by using a clamp during film coating, so that the technical problems that the bar is damaged easily and the operation efficiency is reduced are solved.
In a first aspect, the present invention provides a method for manufacturing a semiconductor chip, comprising:
dividing odd columns and even columns which are alternately distributed on the side face of the wafer far away from the substrate, wherein the odd columns and the even columns extend along the cavity surface direction of the semiconductor chip;
forming first grooves in the odd rows, and extending the bottoms of the first grooves to the substrate of the wafer;
plating a first film layer on the inner side of the first groove;
second grooves which are arranged at intervals with the first grooves are formed in the even rows, and the bottoms of the second grooves extend to the substrate of the wafer;
plating a second film layer on the inner side of the second groove, wherein the second film layer is one of an antireflection film and a reflecting film, and the first film layer is the other film layer;
and cleaving the wafer at the first groove and the second groove along the cavity surface direction of the semiconductor chip to obtain a plurality of bars.
In an alternative embodiment, the method further comprises the step of, after cleaving the wafer at the first and second grooves along the facet direction of the semiconductor chip:
the bar is cleaved into a plurality of bars in a direction perpendicular to the facets of the semiconductor chip.
In an alternative embodiment, the method further comprises the step of, after cleaving the wafer at the first and second grooves along the facet direction of the semiconductor chip:
plating a first electrode on one side of the bar row away from the wafer substrate;
and plating a second electrode on one side of the bar row provided with the wafer substrate.
In an alternative embodiment, the step of plating the second electrode on the side of the bar where the wafer substrate is located comprises:
dividing a cleavage area for cleaving the bar at one side of the bar row provided with the wafer substrate, and arranging a shielding bar at the cleavage area;
and plating a second electrode in the area of the side of the busbar provided with the wafer substrate and positioned at two sides of the shielding strip.
In an alternative embodiment, the method further comprises the step of plating a second film layer on the inner side of the second groove:
and a mask plate is arranged at the first groove to cover the space in the groove of the first groove.
In an alternative embodiment, the step of cleaving the wafer at the first groove and the second groove in the facet direction of the semiconductor chip includes:
a third groove is formed between the first film layer at the groove bottom of the first groove and the substrate of the wafer;
a fourth groove is formed between the second film layer at the groove bottom of the second groove and the substrate of the wafer;
cleaving the wafer in the third groove and in the fourth groove to obtain a plurality of bars.
In an alternative embodiment, the step of cleaving the wafer at the first groove and the second groove in the facet direction of the semiconductor chip includes:
forming a plurality of cleavage grooves in the side surface of the substrate of the wafer, wherein the cleavage grooves are back to the first groove and the second groove one by one;
placing the side surface of the wafer, provided with the cleavage grooves, on a plurality of groove-shaped supports, and enabling the notches of the cleavage grooves to be located in the notch ranges of the supports in a one-to-one correspondence manner;
and applying pressure towards the support to the wafer in the first groove and the second groove so as to cleave the wafer.
In an alternative embodiment, the first groove has a first distance from the second groove on one side thereof and a second distance from the second groove on the other side thereof, and the first distance and the second distance are not equal.
In an alternative embodiment, the distance between the groove bottom of the first groove and the side face of the wafer provided with the substrate is less than half of the thickness of the substrate;
and the distance between the groove bottom of the second groove and the side face, provided with the substrate, of the wafer is smaller than half of the thickness of the substrate.
In an alternative embodiment, the depth of the first groove is equal to the depth of the second groove.
The semiconductor chip manufacturing method provided by the invention comprises the following steps: dividing the side surface of the wafer far away from the substrate into odd columns and even columns which are alternately distributed, wherein the odd columns and the even columns extend along the cavity surface direction of the semiconductor chip; forming first grooves in the odd rows, and extending the bottoms of the first grooves to the substrate of the wafer; plating a first film layer on the inner side of the first groove; second grooves which are arranged at intervals with the first grooves are formed in the even rows, and the bottoms of the second grooves extend to the substrate of the wafer; plating a second film layer on the inner side of the second groove, wherein the second film layer is one of an antireflection film and a reflecting film, and the first film layer is the other film layer; the wafer is cleaved at the first groove and the second groove along a facet direction of the semiconductor chip to obtain a plurality of bars. The method for manufacturing the semiconductor chip comprises the steps of dividing the side face, away from a substrate, of a wafer into odd columns and even columns extending along the cavity surface direction of the semiconductor chip, then forming first grooves in the odd columns, forming second grooves in the even columns, and extending the first grooves and the second grooves along the cavity surface direction of the semiconductor chip. After the first groove is formed, a first film layer needs to be plated on the inner side of the first groove, and after the second groove is formed, a second film layer needs to be plated on the inner side of the second groove. After the film coating is finished, the wafer is cleaved at the first groove and the second groove along the cavity surface direction of the semiconductor chip, and the busbar with one side coated with the antireflection film and the other side coated with the reflection film can be obtained after the wafer is cleaved. Before the wafer is cleaved into the busbar, the cavity surface is coated with an antireflection film or a reflecting film, so that the cavity surface of the semiconductor chip can be prevented from being damaged, and the surface of the busbar can be prevented from generating water ripple cracks. In addition, the method is to carry out film coating before the wafer is cleaved into the bar rows, so that the bar rows with one side coated with the antireflection film and the other side coated with the reflection film can be obtained after the wafer is cleaved. In addition, the film coating process of the method is carried out in the first groove and the second groove of the wafer, and the bar does not need to be turned over by using a clamp during film coating, so that the bar is not easy to damage, and the operation efficiency can be improved.
Compared with the prior art, the manufacturing method of the semiconductor chip provided by the invention has the advantages that the busbar is cleaved after the film is coated, the water ripple-shaped cracks generated on the busbar can be prevented, the cavity surface of the semiconductor chip can be prevented from being exposed in the air for a long time, and a clamp is not required to turn over the busbar during film coating.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a partial schematic view of a conventional wafer;
FIG. 2 is a schematic diagram of a prior art rowbar configuration;
FIG. 3 is a schematic structural view of a conventional bar;
FIG. 4 is a schematic structural diagram of a conventional coated bar;
FIG. 5 is a schematic diagram of a conventional trimmed bar;
FIG. 6 is a flow chart of a method for manufacturing a semiconductor chip according to an embodiment of the present invention;
FIG. 7 is a top view of a wafer according to an embodiment of the present invention;
FIG. 8 is a partial top view of a wafer according to an embodiment of the present invention;
FIG. 9 is a top view of a rowbar provided by an embodiment of the present invention;
fig. 10 is a partial cross-sectional view of a wafer with a first groove provided therein according to an embodiment of the present invention;
fig. 11 is a partial cross-sectional view of a wafer with a first layer provided thereon according to an embodiment of the invention;
fig. 12 is a partial cross-sectional view of a wafer with a first groove and a second groove provided in accordance with an embodiment of the present invention;
FIG. 13 is a partial cross-sectional view of a wafer with a first layer and a second layer provided in accordance with an embodiment of the present invention;
FIG. 14 is a partial cross-sectional view of a rowbar provided in accordance with an embodiment of the present invention;
FIG. 15 is a top view of a batten provided in accordance with an embodiment of the present invention;
FIG. 16 is another flow chart of a method for fabricating a semiconductor chip according to an embodiment of the present invention;
FIG. 17 is a flowchart of a method for fabricating a semiconductor chip according to an embodiment of the present invention;
FIG. 18 is a partial cross-sectional view of a wafer with a first electrode provided thereon according to an embodiment of the present invention;
FIG. 19 is another partial cross-sectional view of a wafer with a first electrode provided thereon according to an embodiment of the invention;
FIG. 20 is a further flowchart of a method for fabricating a semiconductor chip according to an embodiment of the present invention;
fig. 21 is a partial cross-sectional view of a wafer and pedestal having a first electrode according to an embodiment of the present invention.
Icon: 1-a wafer; 10-a substrate; 11-an epitaxial layer; 12-a protective layer; 2-bara; 3-batten; 4-a first groove; 40-a first film layer; 41-third groove; 5-a second groove; 50-a second film layer; 51-a fourth groove; 6-a first electrode; 7-a second electrode; 8-cleavage groove; 9-support.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with each other without conflict.
Example (b):
as shown in fig. 6, the method for manufacturing a semiconductor chip according to the present embodiment includes:
step S1: dividing the side surface of the wafer 1 far away from the substrate 10 into odd columns and even columns which are alternately distributed, wherein the odd columns and the even columns extend along the cavity surface direction of the semiconductor chip;
step S2: opening first grooves 4 in odd rows, and extending the bottoms of the first grooves 4 to the substrate 10 of the wafer 1;
step S3: plating a first film layer 40 on the inner side of the first groove 4;
step S4: second grooves 5 which are arranged at intervals with the first grooves 4 are arranged in even rows, and the bottoms of the second grooves 5 extend to the substrate 10 of the wafer 1;
step S5: plating a second film layer 50 on the inner side of the second groove 5, wherein the second film layer 50 is one of an antireflection film and a reflecting film, and the first film layer 40 is the other;
step S6: the wafer 1 is cleaved at the first grooves 4 and the second grooves 5 in the facet direction of the semiconductor chips to obtain a plurality of bars 2.
In the method for manufacturing the semiconductor chip provided in this embodiment, the side surface of the wafer 1 away from the substrate 10 is first divided into odd columns and even columns extending along the cavity surface direction of the semiconductor chip, and then as shown in fig. 7, 10 and 12, the first grooves 4 are opened in the odd columns, and the second grooves 5 are opened in the even columns, at this time, the first grooves 4 and the second grooves 5 also extend along the cavity surface direction of the semiconductor chip. When the first groove 4 and the second groove 5 are formed, grooving can be performed in a laser premelting manner. As shown in fig. 11 and 13, after the first groove 4 is formed, the first film layer 40 needs to be plated on the inner side of the first groove 4, and after the second groove 5 is formed, the second film layer 50 needs to be plated on the inner side of the second groove 5.
The arrow directions shown in fig. 7, 8, and 9 are directions extending along the cavity surface direction of the semiconductor chip, after the film plating is finished, as shown in fig. 7, 8, and 9, the wafer 1 is cleaved at the first groove 4 and the second groove 5 along the cavity surface direction of the semiconductor chip, and after the wafer 1 is cleaved, the bar 2 with one side plated with the antireflection film and the other side plated with the reflection film shown in fig. 9 and 14 is obtained. Since the direction of the external force applied to the wafer 1 when the wafer 1 is cleaved into the bar 2 extends along the cavity surface direction of the semiconductor chip, in the process of cleaving the wafer 1 into the bar 2, after the wafer 1 is initially cracked, the subsequent cavity surface thereof can be naturally cracked under the external force, so that the cleavage efficiency is improved.
In addition, the method is to carry out film coating before the wafer 1 is cleaved into the bar row 2, so that the bar row 2 with one side coated with the antireflection film and the other side coated with the reflection film can be obtained after the wafer 1 is cleaved, and compared with the mode that the wafer 1 is cleaved into the bar row 2, the bar row 2 is cleaved into the bars 3, and then the bars 3 are coated, the method can prevent the cavity surface from being damaged to generate water ripples when the wafer 1 is cleaved into the bar row 2 in the prior art. In addition, the film coating process of the method is carried out in the first groove 4 and the second groove 5 of the wafer 1, and the bar 3 does not need to be turned over by using a clamp during film coating, so that the bar 3 is not easy to damage, and the operation efficiency can be improved.
Compared with the prior art, the manufacturing method of the semiconductor chip provided by the embodiment can prevent the rowbar 2 from generating the water ripple-shaped cracks by firstly plating the film and then cleaving the rowbar 2, can prevent the cavity surface of the semiconductor chip from being exposed in the air for a long time, and does not need to use a clamp to turn over the bars 3 during film plating.
In the present embodiment, each of the wafer 1 for forming the bar 2 and the bar 2 obtained after cleaving the wafer 1 may include the substrate 10, the epitaxial layer 11 and the protective layer 12, as shown in fig. 14, and in this case, each of the bar 2 and the wafer 1 may include a side away from the substrate 10 and a side provided with the substrate 10. Wherein, the side far away from the substrate 10 and the side provided with the substrate 10 can be plated with electrode layers.
As shown in fig. 6, the method for manufacturing a semiconductor chip provided in the present embodiment further includes a step of, after cleaving the wafer 1 at the first groove 4 and the second groove 5 in the facet direction of the semiconductor chip:
step S7: the bar row 2 is cleaved into a plurality of bars 3 in a direction perpendicular to the cavity surface of the semiconductor chip.
After step S7, the batten 3 shown in fig. 15 is obtained.
It should be noted that, in step S7, the worker can cleave the bar 2 according to the required size of the semiconductor chip product to obtain the bar 3 meeting the requirement. In this process, the operator does not need to trim the bar 3 to obtain the bar 3 meeting the size requirement, so that the step of trimming the bar 3 can be omitted, and compared with the prior art, the semiconductor chip manufacturing method provided by the embodiment can effectively save the operation time and improve the operation efficiency.
Compared with the prior art, the method for manufacturing the semiconductor chip provided by the embodiment can obtain the bar 2 with both sides coated with the film when the bar 2 is obtained through cleavage, and the bar 3 can be coated without obtaining the bar 3 through cleavage of the bar 2, so that the bar 3 does not need to be sequentially coated, and the operation efficiency of the coating process can be effectively improved.
As shown in fig. 6, the method for manufacturing a semiconductor chip provided by the present embodiment further includes, after step S6:
step S07: plating a first electrode 6 on one side of the bar row 2 far away from the substrate 10 of the wafer 1;
step S007: a second electrode 7 is plated on the side of the bar 2 where the substrate 10 of the wafer 1 is located.
After steps S07 and S007, the steak 2 shown in fig. 14 is obtained.
The first electrode 6 is a positive electrode or a negative electrode, and correspondingly, the second electrode 7 is a negative electrode or a positive electrode.
In this embodiment, the first electrode 6 and the second electrode 7 may be disposed on both sides of the bar 2 by evaporation.
It should be noted that step S07 and step S007 in the present embodiment are not limited to be performed before step S7, and step S07 and step S007 may be performed after step S7.
As shown in fig. 16, step S007 includes:
step S0070: dividing a cleavage area for cleaving the bars 3 on one side of the substrate 10 of the bar row 2, where the wafer 1 is arranged, and arranging a shielding bar in the cleavage area;
step S0071: the second electrode 7 is plated in the area of the side of the bar 2 where the substrate 10 is located on both sides of the shielding strip.
The cleavage area in step S0070 is the cleavage position for cleaving the rowbar 2 into the rowbars 3, which can be planned in advance on the rowbar 2, said cleavage position being generally perpendicular to the extension direction of the rowbar 2. Further, in order to facilitate the arrangement of the shielding strip, the cleavage area may be marked on the rowbar 2 by a marking.
Wherein the extending direction of the shielding strips may be perpendicular to the extending direction of the busbar 2. After step S0070, the cleavage area of the rowbar 2 is covered by the shielding strip. The shielding strip can be made of a material which is the same as that of the mask plate, and the shielding strip protrudes out of the surface of the busbar 2 at the moment.
Then, step S0071 can be performed, when step S0071 is performed, the shielding strips can be prevented from being covered by the second electrodes 7 by controlling the thickness of the second electrodes 7, at this time, the second electrodes 7 on the surface of the busbar 2 are in an off state when the shielding strips are removed, and when step S7 is performed after the shielding strips are removed, the convenience of the cleavage process can be greatly improved, the situation that the second electrodes 7 are pulled and fall off due to the fact that the second electrodes 7 cannot be effectively broken can be effectively prevented during cleavage, and therefore the product yield can be effectively improved and the cleavage efficiency can be effectively improved.
As shown in fig. 6, the method for manufacturing a semiconductor chip provided by the present embodiment further includes, before step S5:
step S05: a mask is provided at the first groove 4 to cover the space in the groove of the first groove 4.
After the step S05, the step S5 is performed to effectively prevent the first film layer 40 formed in the first groove 4 from being covered by the second film layer 50, so that the wafer 1 with odd-numbered rows of grooves plated with the first film layer 40 and even-numbered rows of grooves plated with the second film layer 50 can be obtained.
It should be noted that, in step S3, in order to improve the operation efficiency, the first film layer 40 may be covered in the first groove 4 by covering the first film layer 40 on the side of the wafer 1 away from the substrate 10, and step S4 is performed after step S3. In step S4, the even-numbered rows are opened with the first film layer 40 as the starting point, and the inner walls of the second grooves 5 are not covered by the first film layer 40.
In this embodiment, as shown in fig. 12, 13 and 14, the side surface of the wafer 1 away from the substrate 10 needs to ensure that the inner wall of the second groove 5 is not covered by the first film layer 40, and the first film layer 40 on the surface of the protection layer 12 does not need to be removed, so that the first groove 4 is covered by the first film layer 40 by fully covering the first film layer 40 when performing step S3.
As shown in fig. 17, step S6 includes:
step S60: a third groove 41 is formed between the first film layer 40 at the groove bottom of the first groove 4 and the substrate 10 of the wafer 1;
step S61: a fourth groove 51 is formed between the second film layer 50 at the groove bottom of the second groove 5 and the substrate 10 of the wafer 1;
step S62: the wafer 1 is cleaved in the third recess 41 and in the fourth recess 51 to obtain a plurality of bars 2.
After the steps S60 and S61, the wafer 1 shown in fig. 18 is obtained.
The third groove 41 in the step S60 and the fourth groove 51 in the step S61 can both improve the yield of the cleavage of the wafer 1, so as to obtain the bar 2 meeting the requirement.
In practical applications, the third groove 41 in step S60 may have the same length as the first groove 4, and the third groove 41 may be located in the middle of the bottom of the first groove 4. Correspondingly, the fourth groove 51 in step S61 may be as long as the second groove 5, and the fourth groove 51 may be disposed in the middle of the bottom of the second groove 5.
Wherein, the third groove 41 and the fourth groove 51 can be obtained by laser pre-melting.
When the wafer 1 is cleaved in step S62, the wafer may be cleaved by dry etching, laser cleaving, or a cleaving blade.
When the wafer 1 is etched and cleaved by the dry method, etching gas may be introduced into the third groove 41 and the fourth grooveEtching gas is introduced into the groove 51, and the etching gas can adopt SF6。
Furthermore, in order to prevent excessive etching and improve the etching efficiency, passivation gas such as C can be introduced into the etching chamber simultaneously when the etching gas is introduced into the etching chamber4F8。
Wherein, the flow of the etching gas and the passivation gas can be both 13cm3/min。
In order to further prevent over etching, a periodic filling mode can be adopted when filling etching gas and passivation gas. Furthermore, the period of time for introducing the etching gas in one cycle may be 4s, and the period of time for introducing the passivation gas may be 3 s.
It should be noted that, by adopting the dry etching process with the above process parameters, the verticality of the side wall of the busbar 2 obtained after cleavage can be well controlled to 90 ° ± 1 °.
When the wafer 1 is cleaved by laser spalling, as shown in fig. 19, aluminum nanoparticles may be coated in the third groove 41 and the fourth groove 51, and then laser irradiation may be performed on the aluminum nanoparticles to achieve spalling by heat release of thermite reaction.
As shown in fig. 20, step S6 includes:
step S63: a plurality of cleavage grooves 8 are formed in the side surface of a substrate 10 of the wafer 1, and the cleavage grooves 8 are back to the first grooves 4 and the second grooves 5 one by one;
step S64: placing the side surface of the wafer 1 provided with the cleavage grooves 8 on a plurality of groove-shaped supports, and enabling the notches of the cleavage grooves 8 to be located in the notch ranges of the supports 9 in a one-to-one correspondence manner;
step S65: pressure is applied to the wafer 1 in the first recess 4 and in the second recess 5 towards the support 9 to cleave the wafer 1.
The cleavage grooves 8 in step S63 may be obtained by scribing, and further, the section of the cleavage groove 8 may be provided in a V shape.
The groove-shaped support in step S64 is shown in fig. 21, and the groove-shaped support and the cleavage groove 8 can be matched with each other in step S65, so as to improve the easiness of the cleavage process of the wafer 1 and effectively improve the effect of the wafer 1 after cleavage, so that the wafer 1 can be effectively cracked along the cleavage groove 8 and a smooth cleavage surface can be generated.
In step S65, when the wafer 1 is pressed toward the support 9, the diamond knife or the cleaving knife may be used to perform the auxiliary fitting cleaving, and the force application position of the diamond knife or the cleaving knife may be located at any position of the bottom of the third groove 41 and the bottom of the fourth groove 51, so that even if the force application position of the diamond knife or the cleaving knife is located at the bottom corner of the third groove 41 and the bottom corner of the fourth groove 51, the cleaving position of the wafer 1 may be maintained between the third groove 41 and the cleaving groove 8 and between the fourth groove 51 and the cleaving groove 8 without being shifted due to the auxiliary fitting of the cleaving groove 8 and the support 9. It can be seen that the third groove 41 and the fourth groove 51 can not only give way for plating, but also improve the ease of the wafer 1 cleavage process.
In this embodiment, the first groove 4 has a first distance from the second groove 5 on one side thereof, and has a second distance from the second groove 5 on the other side thereof, and the first distance and the second distance are not equal to each other.
When the first spacing and the second spacing are not equal, the bars 2 with different sizes can be obtained, so that the bars 3 with different sizes can be obtained, and different product requirements can be met.
Wherein, the distance between the groove bottom of the first groove 4 and the side surface of the wafer 1 provided with the substrate 10 is less than one half of the thickness of the substrate 10; the distance between the groove bottom of the second groove 5 and the side face of the wafer 1 provided with the substrate 10 is less than half of the thickness of the substrate 10.
The distance between the bottom of the first groove 4 and the side face of the wafer 1 is smaller than the thickness of the substrate 10, and the distance between the bottom of the second groove 5 and the side face of the wafer 1 is smaller than the thickness of the substrate 10, so that the easiness of the subsequent wafer 1 cleavage process can be improved, the wafer 1 is not prone to crack and deflect in the cracking process, and the yield of the bar row 2 after cracking is effectively improved.
Further, the distance between the bottom of the first recess 4 and the side of the wafer 1, and the distance between the bottom of the second recess 5 and the side of the wafer 1 may be equal to one third of the thickness of the substrate 10.
When the third groove 41 is provided in the first groove 4 and the fourth groove 51 is provided in the second groove 5, the groove depth of the third groove 41 and the groove depth of the fourth groove 51 may both be equal to one-fourth of the thickness of the substrate 10.
In the present embodiment, the depth of the first groove 4 is equal to the depth of the second groove 5.
When the depth of the first groove 4 is equal to that of the second groove 5, the process conditions for uniformly preparing the grooves are facilitated, and the subsequent splitting process is facilitated. Therefore, the present embodiment preferably has the depth of the first groove 4 equal to the depth of the second groove 5.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of manufacturing a semiconductor chip, comprising:
dividing the side surface of the wafer (1) far away from the substrate (10) into odd columns and even columns which are alternately distributed, wherein the odd columns and the even columns extend along the cavity surface direction of the semiconductor chip;
opening first grooves (4) in the odd rows, and enabling the bottoms of the first grooves (4) to extend to the substrate (10) of the wafer (1);
plating a first film layer (40) on the inner side of the first groove (4);
second grooves (5) which are arranged at intervals with the first grooves (4) are formed in the even rows, and the bottoms of the second grooves (5) extend to the substrate (10) of the wafer (1);
plating a second film layer (50) on the inner side of the second groove (5), wherein the second film layer (50) is one of an antireflection film and a reflecting film, and the first film layer (40) is the other;
cleaving the wafer (1) at the first recess (4) and at the second recess (5) in a facet direction of the semiconductor chip to obtain a plurality of bars (2).
2. The semiconductor chip manufacturing method according to claim 1, further comprising, after cleaving the wafer (1) at the first groove (4) and at the second groove (5) in the facet direction of the semiconductor chip:
the bar row (2) is cleaved into a plurality of bars (3) in a direction perpendicular to the cavity surface of the semiconductor chip.
3. A semiconductor chip manufacturing method according to claim 1, further comprising, after cleaving the wafer (1) at the first groove (4) and the second groove (5) in the facet direction of the semiconductor chip:
plating a first electrode (6) on one side of the bar row (2) far away from a substrate (10) of the wafer (1);
and plating a second electrode (7) on one side of the bar row (2) provided with the substrate (10) of the wafer (1).
4. A semiconductor chip manufacturing method according to claim 3, wherein the step of plating a second electrode (7) on the side of the bar (2) on which the substrate (10) of the wafer (1) is provided comprises:
dividing a cleavage area for cleaving the bars (3) on one side of the bar row (2) provided with the wafer (1) substrate (10), and arranging shielding bars at the cleavage area;
and plating a second electrode (7) in the area of one side of the busbar (2) provided with the substrate (10) of the wafer (1) and positioned at two sides of the shielding strip.
5. The method for manufacturing a semiconductor chip according to claim 1, further comprising a step of plating a second film layer (50) on the inner side of the second groove (5):
and a mask plate is arranged at the first groove (4) to cover the space in the groove of the first groove (4).
6. A semiconductor chip manufacturing method according to any one of claims 1 to 5, characterized in that the step of cleaving the wafer (1) at the first groove (4) and at the second groove (5) in the facet direction of the semiconductor chip comprises:
a third groove (41) is formed between the first film layer (40) at the groove bottom of the first groove (4) and the substrate (10) of the wafer (1);
a fourth groove (51) is formed between the second film layer (50) at the groove bottom of the second groove (5) and the substrate (10) of the wafer (1);
cleaving the wafer (1) in the third recess (41) and in the fourth recess (51) to obtain a plurality of bars (2).
7. A semiconductor chip manufacturing method according to any one of claims 1 to 5, characterized in that the step of cleaving the wafer (1) at the first groove (4) and at the second groove (5) in the facet direction of the semiconductor chip comprises:
forming a plurality of cleavage grooves (8) in the side surface of a substrate (10) of a wafer (1), wherein the cleavage grooves (8) are back to the first groove (4) and the second groove (5) one by one;
placing the side surface, provided with the cleavage grooves (8), of the wafer (1) on a plurality of groove-shaped supports, and enabling the notches of the cleavage grooves (8) to be located in the notch ranges of the supports (9) in a one-to-one correspondence manner;
applying a pressure on the wafer (1) in the first recess (4) and in the second recess (5) towards a support (9) for cleaving the wafer (1).
8. A semiconductor chip manufacturing method according to any one of claims 1 to 5, wherein the first recess (4) is spaced from the second recess (5) on one side thereof by a first pitch, and the second recess (5) on the other side thereof is spaced from the first recess by a second pitch, and the first pitch and the second pitch are not equal.
9. A semiconductor chip manufacturing method according to any one of claims 1 to 5, characterized in that the distance between the bottom of the first recess (4) and the side of the wafer (1) on which the substrate (10) is provided is less than half the thickness of the substrate (10);
the distance between the bottom of the second groove (5) and the side face, provided with the substrate (10), of the wafer (1) is smaller than half of the thickness of the substrate (10).
10. A semiconductor chip manufacturing method according to any one of claims 1 to 5, characterized in that the depth of the first recess (4) is equal to the depth of the second recess (5).
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| WO2024040513A1 (en) * | 2022-08-25 | 2024-02-29 | Innoscience (Zhuhai) Technology Co., Ltd. | Semiconductor device and method for manufacturing the same |
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