WO2024040513A1

WO2024040513A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: WO2024040513A1
Application number: PCT/CN2022/114804
Authority: WO
Inventors: Ronghui Hao; Lei Zhang; King Yuen Wong
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-08-25
Filing date: 2022-08-25
Publication date: 2024-02-29

Abstract

A semiconductor device includes a substrate, a plurality of epitaxy structures, a protection layer, and a dielectric layer. The substrate includes a plurality of first regions and a second region having at least one groove surrounding each of the first regions. Each of the first regions comprises a device region and an edge region surrounding the device region. The epitaxy structures are disposed over the device regions, respectively. The protection layer is disposed over and makes contact with top surfaces of the edge regions and the second region. Each of the epitaxy structures is confined by the first dielectric layer. The dielectric layer is stacked on the protection layer to form an interface therebetween. The interface is located directly on the edge region and the groove.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Ronghui HAO; Lei ZHANG; King Yuen WONG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a substrate with a groove/trench.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor device includes a substrate, a plurality of epitaxy structures, a protection layer, and a dielectric layer. The substrate includes a plurality of first regions and a second region having at least one groove surrounding each of the first regions. Each of the first regions comprises a device region and an edge region surrounding the device region. The epitaxy structures are disposed over the device regions, respectively. The protection layer is disposed over and makes contact with top surfaces of the edge regions and the second region. Each of the epitaxy structures is confined by the first dielectric layer. The dielectric layer is stacked on the protection layer to form an interface therebetween. The interface is located directly on the edge region and the groove.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A substrate is patterned to form at least one groove, in which a groove region of the substrate is defined by the at least one groove and a plurality of first regions are defined as regions enclosed by the groove region. A blanket protection layer is formed on the patterned substrate. Portions of the blanket protection layer are removed to expose a plurality of device regions of the first regions, thereby forming a protection layer, in which the protection layer covers edge regions of the first regions and the groove region and the edge region encloses the corresponding device region in the first region. A plurality of epitaxy structures are formed on the device regions, respectively. A first dielectric layer is formed to cover the protection layer, such that an interface is formed therebetween.

In accordance with one aspect of the present disclosure, a semiconductor device includes a substrate, an epitaxy structure, and a muti-layer dielectric structure. The substrate has a device region, an edge region enclosing the device region, and a recessed region enclosing the edge region. Top surfaces of the device region and the edge region are higher than that of the recess region. The epitaxy structure is disposed over the device region. The multi-layered dielectric structure includes an upper and lower dielectric layers. The lower dielectric layer at least makes contact with the recessed region, and the upper dielectric layer covers the epitaxy structure and extends downward to make contact with the lower dielectric layer, such that an interface therebetween is formed.

By the above configuration, in the present disclosure, prior to a step of forming epitaxy structures, a pre-cutting process is performed on a substrate to form at least one groove, thereby defining a recess region and a plurality of first regions. The location of the groove defines the recess region of the substrate, and each of the first region can be defined as a region of the substrate enclosed by the groove. Then, a protection layer is formed to cover the recess region and an edge region of the first region. A device region of the first region is defined by a region free from coverage of the protection layer. Then, the epitaxy structures can be formed in the device regions, respectively. After that, a singulation process/dicing process can be performed along the recess region of the substrate, so as to separate the epitaxy structures. Since the protection layer and the substrate are cut during the singulation process instead of the epitaxial structure, cracks generated during the singulation process are difficult to extend into the epitaxy structures. Thus, the quality of the epitaxy structures can be ensured.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is a vertical cross-sectional view of the semiconductor device taken along a line A-A’ in the FIG. 1A

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, and FIG. 2G show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

After electronic element layers are formed on a semiconductor wafer, there is a need to perform a singulation process on the semiconductor wafer, so as to form separated/independent electronic devices. A cutting tool is usually applied in the singulation process. However, the cutting tool may generate cracks to the electronic element layers during the singulation process, resulting in device failure. Therefore, there is a need to improve reliability of the device.

In order to avoid the crack issue, one of approaches is etching the electronic element layers on the semiconductor wafer to form a deep trench, thereby exposing a surface of the semiconductor wafer. Then, a singulation process can be performed along the trench on the semiconductor wafer. Such a method can avoid cracks generated during the singulation process extending into the electronic element layers. To form the aforesaid deep trench, in some cases, the etching depth of the etching process is large, so a thicker photoresist is required. In some cases, even two photolithography processes may be required to form the deep trench, resulting in a significant increase in manufacturing cost. On the other hand, due to manufacturing factors, the deep trench generally has an inverted trapezoid profile. A horizontal distance between a top and a bottom of the inverted trapezoid profile can even reach several tens of microns, resulting in reducing the wafer utilizable area and increasing the manufacturing cost.

At least to solve the aforesaid issue, the present disclosure provides a novel structure.

FIG. 1A is a top view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. FIG. 1B is a vertical cross-sectional view of the semiconductor device 1A taken along a line A-A’ in the FIG. 1A. The semiconductor device 1A includes a substrate 10, a plurality of epitaxy structures ES, a protection layer 20, a doped nitride-based semiconductor layer 40, a gate electrode 42, a dielectric layer 50, conductive vias CV1, CV2, and conductive layers M1, M2.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof. In some embodiments, the substrate 10 can be doped with dopants. For example, the substrate 10 can be a p-type doped silicon substrate, in which p-type dopants can include a group III element, such as boron (B) and gallium (Ga) .

In the present disclosure, prior a step of forming the epitaxy structures ES, a patterning process is performed on an intermediate substrate, so as to form the substrate 10 with at least one groove GV. The groove GV of the substrate 10 can be a shallow groove, in which a depth of the groove GV falls in a range of 1μm to 100 μm.

Specifically, the substrate 10 has a plurality of regions R1 and a region R2 having the groove GV. Each of the regions R1 is surrounded by the region R2. Since the region R2 has the groove GV, the region R2 can serve as a recess region/scribe region. In addition, the region R2 is prepared to be diced in the following steps; and therefore, the region R2 can be referred to as a dicing region. The profile of the groove GV can be determined by shape of cutting tool applied in the following dicing step, so as to adapt the cutting tool. In the embodiments, the groove GV can be a rectangular groove.

Then, a protection layer 20 is formed to cover an edge region ER of the region R1, and a region of the region R1 free from coverage of the protection layer 20 is defined as a device region DR, in which the device region R1 is a region where the epitaxy structure ES prepared to be formed. The protection layer 20 is formed to be disposed on/over/above top surfaces of the edge regions ER and the region R2. The protection layer 20 is formed to make contact with top surfaces of the edge regions ER and the second region R2. The protection layer 20 is conformally disposed with the edge region ER and the groove GV of the region R2. Referring to FIG. 1B, two adjacent regions R1 are depicted in the FIG. 1B. A portion of the protection layer 20 extends from a top surface of left one of two adjacent the regions to a top surface of the right one of two adjacent the regions R1 through the groove GV therebetween. Accordingly, the protection layer 20 can protect the edge regions ER and the region R2, and well define the device regions DR.

Top surfaces of the device region DR and the edge region ER are at the substantially same height levels. Thicknesses of the device region DR and the edge region ER are substantially the same. Top surfaces of the device region DR and the edge region ER are higher than a bottom surface of the groove GV. A thickness of the region R2 is thinner than that of the device region DR and the edge region ER. The edge region ER and the groove GV can collectively form at least one step structure. The substrate 10 has a connecting surface CS connecting the top surface of the edge region ER to the top surface of the groove GV, in which the connecting surface CS can be a vertical surface.

Then, a plurality of the epitaxy structures ES are formed to the device regions DR, respectively. It should be noted that the epitaxy structures ES are hard to grow/deposit on the protection layer 20 due to their material difference during the formation of the epitaxy structures ES. Therefore, these epitaxial structures ES can be naturally separated from each other instead of applying etching process to separate these epitaxial structures ES. The epitaxial structures ES can avoid possible destructions due to etching process. The quality of the epitaxial structures ES can be ensured.

Each of the epitaxy structures ES is confined by the protection layer 20. An edge of the epitaxy structure ES is separated from an edge of the edge region ER due to the protection layer 20. Two opposite sidewalls of the epitaxy structure ES are substantially perpendicular to a top surface the device region DR of the substrate 10. To be more specific, each of the epitaxy structures ES includes nitride-based semiconductor layers 32 and 34. The nitride-based semiconductor layer 32 is disposed on/over/above the device region DR. The nitride-based semiconductor layer 32 makes contact with a top surface of the device region DR. The nitride-based semiconductor layer 34 is disposed on/over/above the nitride-based semiconductor layer 32 and has a band gap greater than that of the nitride-based semiconductor layer 32. The nitride-based semiconductor layer 34 makes contact with a top surface of the nitride-based semiconductor layer 32. Each of the nitride-based semiconductor layers 32, 34 abuts against inner sidewalls of the protection layer 20. The side surfaces of the nitride-based semiconductor layers 32, 34 make contact with the inner sidewalls of the protection layer 20.

The material of the protection layer 20 can include, for example but are not limited to, dielectric materials. For example, the protection layer 20 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the protection layer 20 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

The exemplary materials of the nitride-based semiconductor layer 32 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 34 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

In some embodiments, the epitaxy structure ES can further include a buffer layer (not shown) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 32. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 32, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the epitaxy structure ES may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The exemplary materials of the nitride-based semiconductor layers 32 and 34 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 32, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 32 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 32 and 34 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The electrodes E1 and E2 can be disposed on/over/above the nitride-based semiconductor layer 34. The electrodes E1 and E2 make contact with a top surface of the nitride-based semiconductor layer 34. In some embodiments, the electrode E1 can serve as a source electrode. In some embodiments, the electrode E1 can serve as a drain electrode. In some embodiments, the electrode E2 can serve as a source electrode. In some embodiments, the electrode E2 can serve as a drain electrode. The role of the electrodes E1 and E2 depends on the device design.

In some embodiments, the electrodes E1 and E2 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the electrodes E1 and E2 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the electrodes E1 and E2 may be a single layer, or plural layers of the same or different composition. The electrodes E1 and E2 form ohmic contacts with the nitride-based semiconductor layer 34. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the electrodes E1 and E2. In some embodiments, each of the electrodes E1 and E2 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 40 is disposed on/over/above the nitride-based semiconductor layer 34. The doped nitride-based semiconductor layer 40 makes contact with the nitride-based semiconductor layer 34. The gate electrode 42 is disposed on/over/above the doped nitride-based semiconductor layer 40. The gate electrode 42 makes contact with the doped nitride-based semiconductor layer 40. The gate electrode 42 can be located between the electrodes E1, E2.

A width of the doped nitride-based semiconductor layer 40 is greater than that of the gate electrode 42. In some embodiments, a width of the doped nitride-based semiconductor layer 40 is substantially the same as a width of the gate electrode 42. The profiles of the doped nitride-based semiconductor layer 40 and the gate electrode 42 are the same, for example, both of them are rectangular profiles. In other embodiments, the profiles of the doped nitride-based semiconductor layer 40 and the gate electrode 42 can be different from each other, for example, the profile of the doped nitride-based semiconductor layer 40 can be a trapezoid profile, while the profile of the gate electrode 42 can be a rectangular profile.

In the exemplary illustration of FIG. 1B, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 42 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 40 may create at least one p-n junction with the nitride-based semiconductor layer 106 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 42 has different characteristics (e.g., different electron concentrations) than the remaining portion of the 2DEG region and thus is blocked.

Due to such mechanism, the semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 42 or a voltage applied to the gate electrode 42 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 42) , the zone of the 2DEG region below the gate electrode 42 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 40 can be omitted, such that the semiconductor device 1A is a depletion-mode device, which means the semiconductor device 1A in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 40 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 40 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 32 includes undoped GaN and the nitride-based semiconductor layer 34 includes AlGaN, and the doped nitride-based semiconductor layer 40 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.

The exemplary materials of the gate electrode 42 may include metals or metal compounds. The gate electrode 42 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The conductive vias CV1 are disposed on/over/above the electrodes E1, E2. The conductive vias CV1 make contact with the electrodes E1, E2, respectively.

The conductive layer M1 is disposed on/over/above the conductive vias CV1. The conductive layer M1 makes contact with the conductive vias CV1. The conductive vias CV1 extends vertically to make contact with the electrode E1/E2 and the conductive layer CV1.

The conductive vias CV2 are disposed on/over/above the conductive layer CV1. The conductive vias CV2 make contact with the conductive layer M1.

The conductive layer M2 is disposed on/over/above the conductive vias CV2. The conductive layer M2 makes contact with the conductive vias CV2. The conductive vias CV2 extends vertically to make contact with the conductive layer M1 and the conductive layer CV1.

The exemplary materials of the conductive vias CV1, CV2, the conductive layers M1, M2 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The dielectric layer 50 is disposed on/over/above the protection layer 20, the epitaxy structures ES, the doped nitride-based semiconductor layer 40, the gate electrode 42, the electrodes E1, E2, conductive vias CV1, CV2 and the conductive layers M1, M2. The dielectric layer 50 covers the aforesaid element layers. The dielectric layer 50 extends downward to make contact with the protection layer 20. The dielectric layer 50 is stacked on the protection layer 20 to form an interface IF therebetween, in which the interface IF is located directly on the edge region ER and the groove GV. The interface IF is formed within a thickness of the nitride-based semiconductor layer 32 of the epitaxy structure ES. The dielectric layer 50 can have a recess R corresponded to the groove GV.

The exemplary materials of the dielectric layer 50 can be similar or the same with the protection layer 20. The dielectric layer 50 at a higher position can be referred as to an upper dielectric layer, and the protection layer 20 at a lower position can be referred as to a lower dielectric layer. Thus, the dielectric layer 50 and the protection layer 20 can be referred as to a multi-layered dielectric structure.

Moreover, the dielectric layer 50 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the dielectric layer 50 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the dielectric layer 50 to remove the excess portions, thereby forming a level top surface.

Different stages of a method for manufacturing the semiconductor packaged device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, and FIG. 2G described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, an intermediate substrate is provided. The intermediate substrate is patterned to form at least one groove/trench GV. A groove region of the substrate 10 is defined by the at least one groove GV and a plurality of regions R1 are defined as regions enclosed by the groove region GV.

Referring to FIG. 2B, a blanket protection layer 60 is formed on the patterned substrate 10, such that an entirety of a top surface of the blanket protection layer 60 is covered.

Referring to FIG. 2C, portions of the blanket protection layer 60 are removed to expose a plurality of device regions DR of the regions R1, thereby forming a protection layer 20. The protection layer 20 covers edge regions ER of the regions R1 and the groove region GV. The protection layer 20 is conformal with the edge region ER and the groove region GV. The edge region ER encloses the corresponding device region DR in the region R1. Then, a plurality of epitaxy structures ES on the device regions DR, respectively. Specifically, a plurality of nitride-based semiconductor layers 32 are formed on/over/above the device regions DR, respectively. A plurality of nitride-based semiconductor layers 34 are formed on the nitride-based semiconductor layers 32, respectively. Electrodes E1, E2, a doped nitride-based semiconductor layer 40, and a gate electrode 42 are formed on each of the epitaxy structures ES in sequence. Then, the semiconductor device 1A in the FIG. 1A can be obtained.

Referring to FIG. 2E, another blanket protection layer 70 is formed to cover the resulted structure in the FIG. 2D. The resulted structure in the FIG. 2D is packaged by the blanket protection layer 70. The blanket protection layer 70 can include polyimide (PI) or other packaging materials.

Referring to FIG. 2F, an etching process is performed to remove portions of another blanket protection layer 70, portions of dielectric layer 50, and portions of the protection layer 20. Thus, top surfaces of the conductive layer M2 and the substrate 10 can be exposed.

Referring to FIG. 2G, a singulation/dividing process (or a wafer dicing process) is performed on the substrate 10 along the groove region GV. Specifically, the singulation/dividing process can be achieved by using a cutting tool to provide a stress to the patterned substrate 10, thereby separating the devices 1A'. The device 1A’ includes, for example, a single epitaxy structure ES. In some embodiments, the cutting tool can include a grinding wheel or a laser.

In some embodiments, a singulation/dividing process can include a dry or wet etching process. Compared to one etching process, two-stage etching processes can avoid possible crack risk in the epitaxy structures ES and the device 1A’, which is helpful for device reliability.

FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the groove GV in the FIG. 3 is an inverted trapezoid groove. A connecting surface CS connecting a top surface of the edge region and a top surface of the groove GV is an inclined surface.

FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that a connecting surface CS connecting a top surface of the edge region and a top surface of the groove GV is a curved surface.

In other embodiments, the connecting surface CS can be a combination of a vertical surface, a curved surface, and an inclined surface.

FIG. 5 is a vertical cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the groove GV in the FIG. 5 is an inverted triangle groove.

The structures of the embodiments as above can be selected to match different cutting tools.

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the top surface of the device region is higher than that of the edge region, and the top surface of the edge region ER is higher than that of the region R2. The device region DR, the edge region ER, and the region R2 can form two step structures.

FIG. 7 is a vertical cross-sectional view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that in these device regions DR, different portions of the corresponding epitaxy structure ES therein form a high-voltage electronic device HV and a low-voltage electronic device LV, respectively, in which the high-voltage electronic device HV is adapted to operate in a high working voltage and the low-voltage electronic device LV is adapted to operate in a low working voltage. The growth areas of the high-voltage electronic device HV and the low-voltage electronic device LV can be defined by the protection layer 20. In some embodiments, the high-voltage electronic device HV and the low-voltage electronic device LV which are separated from each other can be achieved without etching.

Based on the above descriptions, in the present disclosure, an intermediate substrate has been patterned to form a shallow trench/groove, in which the thickness of the shallow trench/groove falls in a range of 1μm to 100 μm. The shallow trench surrounds a plurality of first regions, and thus the first regions are defined. The multi-layered dielectric structure is formed in two stages. A lower dielectric layer of the multi-layered dielectric structure is formed prior the formation of the epitaxy structures to cover the shallow trench and an edge region of the first region, and a device region of the first region is exposed by the lower dielectric layer. Then, the epitaxy structures are formed in the device regions, respectively. Since the materials of the epitaxy structures and the lower dielectric layer are different, the epitaxy structures are less likely to form on the lower dielectric layer (or the edge region and shallow trench) . Due to existence of at least a portion the lower dielectric layer between any two adjacent the epitaxy structures, the formed epitaxy structures can be naturally separated from each other. There is no need to apply another etching process to separate/divide them, and thus possible damage caused by etching process can be avoided. Accordingly, the quality of the epitaxy structures can be improved. Thereafter, to protect other element layers of the device, an upper dielectric layer of the multi-layered dielectric structure is formed after the formation of the epitaxy structures, such that an interface is formed between the upper and the lower dielectric layers.

Furthermore, in some cases, the trench is a rectangular trench. The vertical surface of the rectangular trench is advantageous to improve wafer utilizable area. In some cases, the shape of the trench can be an inverted triangle or an inverted trapezoid, so as to adapt different shapes of cutting tools.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor device, comprising:

a substrate comprising a plurality of first regions and a second region having at least one groove surrounding each of the first regions, wherein each of the first regions comprises a device region and an edge region surrounding the device region;

a plurality of epitaxy structures disposed over the device regions, respectively;

a protection layer disposed over and making contact with top surfaces of the edge regions and the second region, wherein each of the epitaxy structures is confined by the first dielectric layer; and

a dielectric layer stacked on the protection layer to form an interface therebetween, wherein the interface is located directly on the edge region and the groove.
The semiconductor device of claim 1, wherein a portion of the protection layer extends from a top surface of one of two adjacent the first regions to a top surface of the other one of two adjacent the first regions through the groove therebetween.
The semiconductor device of claim 1, wherein the edge region and the groove collectively form at least one step structure.
The semiconductor device of claim 1, wherein the substrate has a connecting surface connecting the top surface of the edge region to the top surface of the groove.
The semiconductor device of claim 4, wherein the substrate has a connecting surface is a vertical surface, a curved surface, an inclined surface, or a combination thereof.
The semiconductor device of claim 1, wherein the groove is a rectangular groove, an inverted trapezoid groove, or an inverted triangle groove.
The semiconductor device of claim 1, wherein each of the epitaxy structures further comprises:

a first nitride-based semiconductor layer disposed over the device region; and

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a band gap greater than that of the first nitride-based semiconductor layer.
The semiconductor device of claim 7, wherein each of the first and second nitride-based semiconductor layers abuts against inner sidewalls of the protection layer.
The semiconductor device of claim 7, wherein an edge of the epitaxy structure is separated from an edge of the edge region.
The semiconductor device of claim 7, wherein in at least one of the device regions, different portions of the corresponding epitaxy structure therein form a high-voltage electronic device and a low-voltage electronic device, respectively.
The semiconductor device of claim 1, wherein at least a portion of the protection layer is conformally disposed with the edge region and the groove of the second region.
The semiconductor device of claim 1, wherein the substrate comprises a p-type doped silicon substrate.
The semiconductor device of claim 1, wherein a thickness of the first region is greater than that of the second region.
The semiconductor device of claim 1, wherein a depth of the groove falls in a range of 1μm to 100 μm.
The semiconductor device of claim 1, wherein the dielectric layer has a recess corresponded to the groove.
A manufacturing method of a semiconductor device, comprising:

patterning a substrate to form at least one groove, wherein a groove region of the substrate is defined by the at least one groove and a plurality of first regions are defined as regions enclosed by the groove region;

forming a blanket protection layer on the patterned substrate;

removing portions of the blanket protection layer to expose a plurality of device regions of the first regions, thereby forming a protection layer, wherein the protection layer covers edge regions of the first regions and the groove region and the edge region encloses the corresponding device region in the first region;

forming a plurality of epitaxy structures on the device regions, respectively; and

forming a first dielectric layer to cover the protection layer, such that an interface is formed therebetween.
The method of claim 16, wherein the protection layer is conformal with the edge region and the groove.
The method of claim 16, further comprising:

dividing the substrate along the groove region by applying stress to the substrate.
The method of claim 16, wherein a depth of the groove falls in a range of 1μm to 100 μm.
The method of claim 16, wherein forming the epitaxial structures further comprises:

forming a plurality of first nitride-based semiconductor layers on the device regions, respectively; and

forming a plurality of second nitride-based semiconductor layers on the first nitride-based semiconductor layers, respectively, wherein each of the second nitride-based semiconductor layer has a bandgap different from that of the first nitride-based semiconductor layer.
A semiconductor device, comprising:

a substrate having a device region, an edge region enclosing the device region, and a recessed region enclosing the edge region, wherein top surfaces of the device region and the edge region are higher than that of the recess region;

an epitaxy structure disposed over the device region; and

a multi-layered dielectric structure comprising an upper and lower dielectric layers, wherein the lower dielectric layer at least makes contact with the recessed region, and the upper dielectric layer covers the epitaxy structure and extends downward to make contact with the lower dielectric layer, such that an interface therebetween is formed.
The semiconductor device of claim 21, wherein a sidewall of the epitaxy structure is substantially perpendicular to a top surface the device region of the substrate.
The semiconductor device of claim 21, wherein the interface is formed within a thickness of the epitaxy structure.
The semiconductor device of claim 21, wherein the recessed region comprises at least one groove, such that a thickness of the recessed region is thinner than that of the device and the edge regions.
The semiconductor device of claim 21, wherein the top surface of the device region is higher than that of the edge region, and the top surface of the edge region is higher than that of the recess region.