CN115099182B

CN115099182B - Integral design method for segmented CDAC (capacitor-to-capacitor converter) bridge capacitor and analog-to-digital converter

Info

Publication number: CN115099182B
Application number: CN202210880356.3A
Authority: CN
Inventors: 邓欢; 朱朝峰; 罗杨贵; 唐金波; 龙睿; 戴超雄; 鄢光强; 李光耀
Original assignee: Hunan Guliang Microelectronics Co ltd
Current assignee: Hunan Guliang Microelectronics Co ltd
Priority date: 2022-07-25
Filing date: 2022-07-25
Publication date: 2022-11-22
Anticipated expiration: 2042-07-25
Also published as: CN115099182A

Abstract

The application relates to a segmented CDAC bridging capacitance integer design method and an analog-to-digital converter, wherein the method comprises the following steps: designing and determining a required segmented DAC capacitor array according to the bit requirement of a target SARADC required to be designed; keeping the capacitance value of each section of capacitor array in the DAC capacitor array unchanged, and respectively connecting the reference voltage ends of each section of capacitor array to the section reference voltage of each section in a one-to-one correspondence manner; respectively calculating DAC output variable quantities before and after integer change of the bridge capacitors according to the conservation of charge stored by the capacitor arrays when the voltage of the lower electrode plate of each capacitor array section changes, and calculating to obtain reference voltage of each capacitor array section according to the DAC output variable quantities; determining a target reference voltage of the DAC capacitor array, and generating segment reference voltages of the rest segments through resistance voltage division according to the target reference voltage to complete integral design of the segmented CDAC bridging capacitor; the target reference voltage is one of all the segment reference voltages. The capacitor array area is effectively reduced and the generation of CDAC gain errors is avoided.

Description

Integral design method for segmented CDAC (capacitor-to-capacitor converter) bridge capacitor and analog-to-digital converter

Technical Field

The invention belongs to the technical field of electronic circuits, and relates to a segmented CDAC bridging capacitor integer design method and an analog-to-digital converter.

Background

With the change of process technologies, sar adc (successive approximation analog to digital converter) is used in various scenarios because of its features of simple structure, strong process compatibility, low power consumption, etc. In many circuits requiring analog-to-digital converters, sar adc has become a common choice. The SAR adc is mainly composed of a DAC (digital-to-analog converter), a comparator, SAR logic and other modules. The DAC, as a core component module of the sar adc, may be classified into a resistance voltage division type DAC, a current superposition type DAC, a charge redistribution type DAC (CDAC), a hybrid DAC, and the like. Most of the currently mainstream sar adc is designed based on a charge redistribution DAC (CDAC) structure.

The common CDAC is composed of capacitors with binary weights, the capacitors have good matching, the capacitor array conforms to the binary relation, the total capacitance is exponentially increased along with the increase of the resolution of the SARADC, the design area is exponentially increased, and more layout resources are consumed. In order to solve the problem, the conventional design method is to process the full binary capacitor in sections, and divide the capacitor into two sections or even more sections by dividing the bridge capacitor by multiple times, so as to reduce the number of capacitors required by the DAC, thereby effectively reducing the area of the capacitor array. However, in the process of implementing the present invention, the inventor finds that the conventional design method has the problems that the fraction times of the bridge capacitance is difficult to implement on the layout and the matching accuracy is poor.

Disclosure of Invention

Aiming at the problems in the traditional method, the invention provides a segmented CDAC bridging capacitor integer design method and an analog-to-digital converter, which can solve the problems that a fractional bridging capacitor is difficult to realize on a layout and the matching precision is poor, and can realize the bridge capacitor integer on the layout easily, have high matching precision and avoid generating gain errors.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, a method for designing an integer of a segmented CDAC bridging capacitor is provided, which includes the steps of:

designing and determining a DAC capacitor array of a required segment according to the bit requirement of a target SARADC required to be designed;

keeping the capacitance value of each section of capacitor array in the DAC capacitor array unchanged, and respectively connecting the reference voltage ends of each section of capacitor array to each section of reference voltage in a one-to-one correspondence manner; each section of reference voltage is used for carrying out integer transformation on the bridge capacitor of the DAC capacitor array;

respectively calculating DAC output variable quantities before and after integral change of the bridge capacitors according to conservation of stored charges of the capacitor arrays when the voltage of the lower electrode plate of each capacitor array section changes, and calculating by using the DAC output variable quantities to obtain reference voltages of each capacitor section;

determining a target reference voltage of the DAC capacitor array, and generating the rest reference voltage through resistance voltage division according to the target reference voltage to complete the integer design of the segmented CDAC bridging capacitor; the target reference voltage is one of all the segment reference voltages.

In one embodiment, a process for designing a DAC capacitance array for determining a desired segment includes:

and determining the structure of each capacitor array section in the DAC capacitor array and the fraction value of the bridge capacitor.

In one embodiment, the DAC capacitor array comprises a low-section capacitor array, a high Duan Dianrong array and a bridge capacitor.

In one embodiment, each segment of reference voltage comprises a first reference voltage and a second reference voltage, the high Duan Dianrong array is correspondingly connected with the first reference voltage, and the low segment of capacitor array is correspondingly connected with the second reference voltage;

according to the conservation of the stored charges of the capacitor array when the voltage of the lower electrode plate of each capacitor array changes, respectively calculating the DAC output variable quantity before and after the integral change of the bridge capacitor, and calculating by utilizing the DAC output variable quantity to obtain the reference voltage of each section, the method comprises the following steps:

when all capacitor lower plates in the DAC capacitor array before the reference voltage is separated are grounded, determining the first DAC output variation caused by the fact that the voltage of the lower plate of any bit capacitor in the high Duan Dianrong array is changed from the ground to the basic reference voltage;

when the lower plates of the high-order capacitor and the low-order capacitor in the DAC capacitor array after the reference voltage division are grounded, determining the second DAC output variable quantity caused by the fact that the voltage of the lower plate of any one-order capacitor in the high Duan Dianrong array is changed from the ground to the first reference voltage; wherein, the lower polar plates of the low-level capacitors are all grounded;

and setting the output variation of the first DAC to be equal to the output variation of the second DAC, and calculating to obtain the value of the first reference voltage.

In one embodiment, the step of calculating DAC output variation before and after the integer change of the bridge capacitor according to conservation of charge stored in the capacitor array when the voltage of the lower plate of each capacitor array changes, and obtaining the reference voltage of each capacitor array by using the DAC output variation further includes:

when all capacitor lower plates in the DAC capacitor array before the reference voltage is divided are grounded, determining the third DAC output variation caused by the fact that the voltage of the lower plate of any bit capacitor in the low-section capacitor array is changed from the ground to the basic reference voltage;

when all capacitor lower plates in the DAC capacitor array after the reference voltage division are grounded, determining the output variation quantity of a fourth DAC caused by the fact that the voltage of the lower plate of any capacitor in the low-section capacitor array is changed from the ground to a second reference voltage; wherein, the lower polar plates of the high-order capacitors are all grounded;

and setting the output variation of the third DAC to be equal to the output variation of the fourth DAC, and calculating to obtain the value of the second reference voltage.

In one embodiment, the target reference voltage is input by an external voltage source or provided by a bandgap reference circuit.

In one embodiment, the process of generating the remaining segment reference voltage by resistive voltage division according to the target reference voltage includes:

and according to the proportional relation between the target reference voltage and the reference voltages of the rest sections, obtaining the reference voltages of the rest sections by adopting series resistance voltage division and operational amplifier buffering.

On the other hand, the analog-to-digital converter comprises a segmented DAC capacitor array, wherein the reference voltage ends of all the segments of the DAC capacitor array are respectively connected to all the segments of reference voltage in a one-to-one correspondence mode, and all the segments of reference voltage are used for enabling the bridge capacitors of the DAC capacitor array to be integer; the bridge capacitor integer of the DAC capacitor array is designed according to the design method.

In one embodiment, the DAC capacitor array comprises a three-segment segmented DAC capacitor array or a four-segment segmented DAC capacitor array.

In one embodiment, the analog-to-digital converter includes an 8-bit SAR ADC, a 12-bit SAR ADC, a 14-bit SAR ADC, or a 16-bit SAR ADC.

One of the above technical solutions has the following advantages and beneficial effects:

according to the integral design method, device and receiver of the segmented CDAC bridging capacitor, firstly, the DAC capacitor array required to be segmented is designed and determined according to the bit requirement of the target SARADC required to be designed, then the capacitance value of each capacitor array in the DAC capacitor array is kept unchanged, the reference voltage of each capacitor array is separately set, the value of each reference voltage is calculated by utilizing charge conservation, finally, one reference voltage is used as the new reference voltage of the DAC capacitor array, and the rest reference voltages are generated by utilizing resistance voltage division, so that the integral design of the segmented CDAC bridging capacitor can be realized.

Compared with the traditional design method, the scheme has the advantages that for the segmented CDAC with the existing digit, on the basis of not increasing the total quantity of the capacitors, integer digitalization of the bridging capacitor is realized by scaling the reference voltage, the fact that the same type of capacitors are adopted by the whole CDAC is guaranteed, influence of the fractional capacitors on the accuracy of the segmented CDAC is avoided, layout realization is easy, and matching accuracy is high. In addition, by changing the value of the reference voltage, all the capacitance weights are ensured to accord with the binary relation, the good linearity of the capacitor array is ensured, and CDAC gain errors cannot be generated; compared with the conventional segmented CDAC with the same number of bits, the capacitor array using the segmented CDAC has a greatly reduced capacitor area.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional 8-bit fully differential CDAC capacitor array;

FIG. 2 is a flowchart illustrating a method for designing integer numbers of bridge capacitors of a segmented CDAC system according to an embodiment;

FIG. 3 is a schematic diagram of an 8-bit CDAC design in one embodiment;

FIG. 4 is a schematic diagram of an optimized CDAC equivalent structure in one embodiment;

FIG. 5 is a schematic diagram of a design before optimization of a CDAC fractional bridge capacitor in one embodiment;

FIG. 6 is a schematic diagram of an embodiment of an optimized CDAC fractional bridge capacitor design;

FIG. 7 is a diagram illustrating the INL/DNL obtained from the CDAC simulation result in one embodiment; wherein (a) is a DNL result, and (b) is an INL result.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It should be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

One skilled in the art will appreciate that the embodiments described herein can be combined with other embodiments. The term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As shown in fig. 1, a schematic diagram of a conventional 8-bit capacitor array is composed of a set of binary-weighted capacitors, and the capacitors have good matching. The capacitor array conforms to a binary relation and has a capacitance value of C _i =2 ⁱ _* C (i =0,1,2 …) (C is unit capacitance), total capacitance C _tot =2 ⁸ _* C. As the resolution of the ADC increases, the total capacitance increases exponentially, and the area also increases exponentially, consuming more resources. The VIP, VREFLO, VREFHI and VIN are potentials required to be switched on of the capacitor plate respectively, COMP is an analog comparator, and VCM is common-mode voltage.

With the development of design technology, it has been proposed to reduce the number of capacitors required by the DAC by segmenting the full binary capacitor into two or more segments through the bridge capacitor, thereby effectively reducing the area of the capacitor array. The capacitor array is processed in segments, and it is common practice to use fractional values for the bridging capacitors. In the actual layout design and production, the integral multiple capacitors can be matched very well in a copying mode, the capacitance value of the fractional capacitor needs to be designed specially, and the fractional capacitor cannot be copied due to the fact that the integral multiple capacitors are different from the other integral capacitors in the layout, so that the proportion between the integral multiple capacitors and the other integral capacitors cannot be accurate enough, and a large gain error can be introduced.

In order to avoid the influence of the fractional bridge capacitor on the linearity of the DAC, some designers add a compensation capacitor at a low stage and design the fractional bridge capacitor into a unit capacitor of 2C or other integral multiples, but the method usually needs a larger compensation capacitor, so that the total capacitance number of the DAC is increased, the area of the whole ADC is increased, and the advantage of a segmented structure is greatly weakened; in addition, this approach introduces additional gain error, requires calibration, and increases the complexity of the ADC design.

In actual work, there is an existing solution that: in the segmented capacitor array, in order to avoid the influence of the fractional bridge capacitor on the DAC, the fractional bridge capacitor is changed into 2C by adding the compensation capacitor in the low segment, so that the influence of the fractional capacitor is avoided.

The following disadvantages were found by the analysis: the purpose of using the segmented DAC is to reduce the area of the DAC, but the method of adding the compensation capacitor usually needs a large compensation capacitor, and the compensation capacitor cannot be used in the actual ADC conversion process, thereby causing resource waste. In addition, this approach introduces additional gain error, requires calibration, and increases the complexity of the ADC design.

Yet another existing solution is: when the fractional capacitance is directly subjected to unit capacitance, the DAC does not completely conform to the binary system, the linearity is poor, so that a capacitance trimming array is added, and the lowest bit weight of the DAC Duan Dianrong is made to be approximately twice as large as the 2.0625 weight of the highest bit of the low-section capacitance through trimming.

The following disadvantages were found by the analysis: the trimming capacitor array needs to be additionally added, and because the error in the actual production process is uncertain and the capacitance value of the trimming capacitor array is uncertain, the capacitor needs to be added to increase the trimming range, so that the area is increased. The result after trimming only approximately conforms to the binary system, and certain error exists, so that the effect is poor.

Based on the above-mentioned disadvantage that the prior art can not avoid the generation of gain error when reducing the area of the capacitor array, the present invention provides an integer design method for segmented DAC bridging capacitors, which can realize the integer of the bridging capacitors without generating additional gain error by scaling the reference voltage without increasing the total number of capacitors.

The following detailed description of the embodiments of the invention will be made with reference to the accompanying drawings.

Referring to fig. 2, in an embodiment, the present application provides a segmented CDAC bridge capacitor integer design method, including steps S12 to S18:

and S12, designing and determining the DAC capacitor array of the required segment according to the bit requirement of the target SARADC required to be designed.

It is understood that the target sar adc of the desired design refers to the sar adc to be designed as specified for the specific application needs, and the bit requirement thereof can be predetermined, such as but not limited to 8 bits, 10 bits, 12 bits, 13 bits or 14 being equal bit requirement. According to the bit requirement of a given sar adc, a required segmented DAC capacitor array may be first designed, for example, how many segments of the DAC capacitor array need to be divided into, the number of capacitors included in each segment of the DAC capacitor array and the capacitance thereof, and the fraction of the bridge capacitor between each segment of the DAC capacitor array. For target SARADC with different bit number requirements, the specific number of segments of the segmented DAC capacitor array, the specific number of capacitors included in each segment of the DAC capacitor array and the capacitance value of each segment of the DAC capacitor array can be determined according to design experience, design standards or similar competitive products, and further the fraction value of the adopted bridge capacitors can be directly determined.

S14, keeping the capacitance value of each section of capacitor array in the DAC capacitor array unchanged, and respectively connecting the reference voltage ends of each section of capacitor array to each section of reference voltage in a one-to-one correspondence manner; each segment of reference voltage is used for integer-sizing the bridge capacitance of the DAC capacitor array.

It can be understood that after the DAC capacitor array to be segmented is designed, the capacitance values of the capacitor arrays of the respective segments in the DAC capacitor array are kept unchanged, and the reference voltages of the capacitor arrays of the respective segments are separated to be respectively and correspondingly connected to the reference voltages to be set (referred to as the segment reference voltages), for example, for the DAC capacitor array divided into two segments, the capacitor array of the two segments to the segment with relatively low bit number may be referred to as a low-segment capacitor array, and the capacitor array of the relatively high bit number may be referred to as a high-segment Duan Dianrong array; the reference voltage of the low-stage capacitor array and the reference voltage of the high Duan Dianrong array may be separated to be connected to new corresponding stage reference voltages, respectively, such as: the low-section capacitor array is connected to one section reference voltage, and the high-section capacitor array Duan Dianrong is connected to the other section reference voltage, so that the bridge capacitance between the sections is changed from a fraction value to an integer value by changing the section reference voltages in the following process. Typically, several reference voltages can be set separately by segmenting the DAC capacitor array.

And S16, respectively calculating DAC output variable quantities before and after integral change of the bridging capacitor according to charge conservation stored by the capacitor array when the voltage of the lower electrode plate of each capacitor array section changes, and calculating by using the DAC output variable quantities to obtain reference voltage of each capacitor section.

It can be understood that after the reference voltages of the capacitor arrays of the respective segments are separated (so as to make the bridge capacitor integer), a new DAC capacitor array structure is formed, and then the values of the reference voltages of the respective segments in the DAC capacitor array, that is, the reference voltage values for ensuring that the bridge capacitor is an integer capacitor, can be obtained through charge conservation derivation calculation.

Specifically, for any one section of the DAC capacitor array, when the lower plates of all capacitors in the DAC capacitor array are grounded, the charges stored in the DAC capacitor array are conserved with the charges stored in the DAC capacitor array when the voltage of the lower plate of any capacitor in the one section of the DAC capacitor array changes from ground to a reference voltage (which may correspond to different reference voltages set before and after the integral change of the bridge capacitor), so that the DAC output (voltage) variation caused by the voltage change of the lower plate of the one section of the DAC capacitor array before the integral change of the bridge capacitor and the DAC output (voltage) variation caused by the same voltage change of the lower plate of the one section of the DAC capacitor array after the integral change of the bridge capacitor can be calculated respectively, and the DAC output voltage variation before and after the integral change of the bridge capacitor can be used to equalize, that is the value of the reference voltage of the section of the one section of the DAC capacitor array to be connected after the integral change of the bridge capacitor can be calculated. Thus, the values of the reference voltages of other sections can be calculated respectively in the same way.

S18, determining a target reference voltage of the DAC capacitor array, and generating the rest reference voltage through resistance voltage division according to the target reference voltage to complete integral design of the segmented CDAC bridging capacitor; the target reference voltage is one of all the segment reference voltages.

It can be understood that after the design processing of the foregoing steps, any one of the calculated segment reference voltages can be used as a new reference voltage, and the remaining segment reference voltages can be accurately obtained by dividing voltages through resistors. The new reference voltage is a uniform reference voltage (which can be marked as a basic reference voltage V for the convenience of description and distinction) relative to that adopted in the traditional segmented DAC capacitor array of the same type _ref ) In other words.

At this point, the bridge capacitors in the segmented DAC capacitor array are integrated through the scaling design of the reference voltage, so that a new DAC capacitor array of the target sar adc is designed. By the above design method, in the same way, but not limited to, the integer design of the segmented CDAC bridge capacitors of various segmented structures such as the two-segment segmented DAC capacitor array, the three-segment segmented DAC capacitor array, and the four-segment segmented DAC capacitor array can be realized.

According to the integral design method of the segmented CDAC bridging capacitor, firstly, a DAC capacitor array required to be segmented is designed and determined according to the bit requirement of a target SARADC required to be designed, then the capacitance value of each capacitor array in the DAC capacitor array is kept unchanged, the reference voltage of each capacitor array is separately set, the value of each reference voltage is calculated by utilizing charge conservation, finally, one reference voltage is used as a new reference voltage of the DAC capacitor array, and the rest reference voltages are generated by utilizing resistance voltage division, so that the integral design of the segmented CDAC bridging capacitor can be realized.

Compared with the traditional design method, the scheme has the advantages that for the segmented CDAC with the existing digit, on the basis of not increasing the total quantity of the capacitors, integer digitalization of the bridging capacitor is realized by scaling the reference voltage, the fact that the same type of capacitors are adopted by the whole CDAC is guaranteed, influence of the fractional capacitors on the accuracy of the segmented CDAC is avoided, layout realization is easy, and matching accuracy is high. In addition, by changing the value of the reference voltage, all the capacitance weights are ensured to accord with the binary relation, the good linearity of the capacitor array is ensured, and CDAC gain errors cannot be generated; compared with the traditional same-digit segmented CDAC, the capacitor array using the segmented CDAC has the advantage that the capacitor area can be greatly reduced.

In one embodiment, the process of designing the DAC capacitance array that determines the desired segment may include the following: and determining the structure of each capacitor array section in the DAC capacitor array and the fraction value of the bridge capacitor.

Specifically, for target sar adc with different bit requirements, a uniform basic reference voltage V can be designed and determined according to the given bit requirement _ref The structure of each lower capacitor array (i.e. under the condition that the reference voltages of the array are not separated) is, for example, a two-segment structure including a lower capacitor array and a higher capacitor array Duan Dianrong, or other multi-segment structures, and the fractional value of the bridge capacitance between the capacitor arrays can also be directly determined according to the determined structure of each segment of the capacitor array. Therefore, the required DAC capacitor array structure form and the fractional bridge capacitor can be quickly determined.

It is understood that, in the present embodiment, the designed DAC capacitor array may be a two-segment DAC capacitor array, that is, the two-segment DAC capacitor array includes a low-segment capacitor array and a high-segment capacitor array Duan Dianrong, and a bridge capacitor between the two-segment capacitor arrays.

Specifically, the low-section capacitor array is connected to one section of reference voltage, the high-section capacitor array Duan Dianrong is connected to the other section of reference voltage, and the bridge capacitance between the two sections of capacitor arrays can be changed from a fractional value to an integer value by changing the two section of reference voltages subsequently, so that the design of the two sections of DAC capacitor arrays is completed efficiently.

In one embodiment, each segment reference voltage includes a first reference voltage and a second reference voltage. The array Duan Dianrong is correspondingly connected to a first reference voltage. The low-stage capacitor array is correspondingly connected with a second reference voltage.

With regard to step S16, the following process may be specifically included:

when all capacitor lower electrode plates in the DAC capacitor array before the reference voltage is divided are grounded, determining the first DAC output variable quantity caused by the fact that the voltage of the lower electrode plate of any bit capacitor in the high Duan Dianrong array is changed from the ground to the basic reference voltage;

when the lower electrode plates of the high-order capacitor and the low-order capacitor in the DAC capacitor array after the reference voltage is divided are grounded, determining the second DAC output variable quantity caused by the fact that the voltage of the lower electrode plate of any one-order capacitor in the high Duan Dianrong array is changed from the ground to the first reference voltage; wherein, the lower polar plates of the low-level capacitors are all grounded;

It is understood that, in this embodiment, for a design scenario of bridge capacitor integer of the DAC capacitor arrays of two segments, the above design calculation steps may be adopted to realize the value calculation determination of the first reference voltage.

Specifically, for convenience of illustration and intuitive understanding of the above method, in the present embodiment, for example, 8-bit sar adc is taken as an example for explanation, wherein the positive body and the italic body of each quantity are synonymous, and the design of the two-stage DAC capacitor array with other bits is similar to the same principle:

firstly, according to the bit requirement of the target sar adc, a required segmented DAC capacitor array is designed, as shown in 301 of fig. 3, where C is denoted as a unit capacitor, and the low-stage capacitor arrays 302 are respectively C,2c,4c and 8C. The high Duan Dianrong arrays 304 are C,2c,4c and 8C, respectively. Bridge capacitor 303 is a fractional value

。

Taking the conventional switching manner in which all capacitors participate in sampling as an example, the basic reference voltages are all V _ref The potential of the lower electrode plate of the capacitor to be connected is V _ref GND and Vin.

Low-order capacitor

High-order capacitor

The bridge capacitor 303 is

。

Keeping the capacitance values of the low-stage capacitor array and the high Duan Dianrong array unchanged, separating the reference voltage of the low-stage capacitor array from the reference voltage of the high Duan Dianrong array, which are respectively shown as 307 and 308 in fig. 3, and correspondingly, the second reference voltage can be marked as V _{LSB_REF} And the first reference voltage is denoted as V _{MSB_REF} . By changing the reference voltage of the high-stage capacitor array and the low-stage capacitor array, the bridge connection of the segmented capacitors is realized

Becomes C. I.e., the bridging capacitor 306 is

。

Deducing and calculating V required by new capacitor array structure according to charge conservation _{MSB_REF} And V _{LSB_REF} The value of (c). In particular, V _{MSB_REF} The specific calculation steps are as follows:

when all capacitor bottom plates in the DAC capacitor array 301 before the reference voltage is divided are connected with GND, one-bit capacitor C in the high Duan Dianrong array 304 is calculated _Mi The voltage of the lower polar plate is changed from GND to V _ref Causing a first DAC output change in the DAC output

：

（1）

When the lower electrode plates of the high-order capacitor and the low-order capacitor in the DAC capacitor array 305 after the reference voltage is separated are connected with GND, one-order capacitor C in the high Duan Dianrong array is calculated _Mi The voltage of the lower plate is changed from GND to a first reference voltage V _{MSB_REF} A second DAC output variation causing the DAC output

And at the moment, the lower polar plate of the low-level capacitor is also connected with GND, then:

（2）

according to the foregoing analysis, two capacitor arrays need to be completely equivalent, and the corresponding weights of the same high-order capacitor should be the same, so that the same high-order capacitor C _Mi The DAC output variation caused by the voltage variation of the lower plate needs to be kept consistent, so:

（3）

deriving the first reference voltage V from equation (3) above _{MSB_REF} Obtaining:

（4）

through the processing steps, the first reference voltage V can be accurately determined _{MSB_REF} And a base reference voltage V _ref So that the first reference voltage V can be easily and quickly determined _{MSB_REF} The value of (c).

In an embodiment, the step S16 may specifically include the following processing:

Specifically, for convenience of illustration and intuitive understanding of the above method, in the present embodiment, for example, 8-bit sar adc is still used as an example for explanation, wherein the positive body and the italic body of each quantity are synonymous, and the design of the two-stage DAC capacitor array with other bits is similar.

For the second reference voltage V _{LSB_REF} The value calculation of (2) determines the procedure as follows:

when the reference voltage is divided intoWhen all the capacitor bottom plates in the DAC capacitor array 301 before starting are connected with GND, one bit of capacitor C in the low-section capacitor array 302 _Li The voltage of the lower polar plate is changed from GND to V _ref When the equivalent structure diagram is shown in FIG. 4, the voltage change of the top electrode plate of the low-stage capacitor array is caused

And the resulting third DAC output change in the DAC output

. The relationship is derived as:

（5）

derive a bit capacitance C in the low-side capacitor array 302 _Li The voltage of the lower polar plate is changed from GND to V _ref When the temperature of the water is higher than the set temperature,

the variation amount of (c):

（6）

substituting formula (6) for formula (5) yields:

（7）

when all the capacitor bottom plates in the DAC capacitor array 305 after the reference voltage is divided are connected with GND, one-bit capacitor C in the low-bit capacitor _Li The voltage of the lower polar plate is changed from GND to a second reference voltage V _{LSB_REF} When the voltage is applied to the upper capacitor, the lower electrode plate of the high-order capacitor is connected with the GND, so that the variation of the output of the fourth DAC caused by the output of the DAC is

. The process from formula (5) to formula (7) can be deduced by the same principleAnd (3) discharging:

（8）

according to the foregoing analysis, two capacitor arrays need to be completely equivalent, and the corresponding weights of the same low-level capacitor should be the same, so that the same low-level capacitor C _Li The DAC output variation caused by the voltage variation of the lower plate needs to be kept consistent, so:

（9）

from equation (9) above, it can be derived:

（10）

through the processing steps, the second reference voltage V can be accurately determined _{LSB_REF} And a base reference voltage V _ref So that the second reference voltage V can be easily and quickly determined _{LSB_REF} The value of (c).

The first reference voltage V is obtained through the calculation and determination of the reference voltage _{MSB_REF} And a second reference voltage V _{LSB_REF} The two structures of DAC capacitor array 301 and DAC capacitor array 305 in fig. 3 are fully equivalent. The output voltage changes corresponding to the same input changes of the DAC are the same. Through the calculation and derivation in the foregoing, V can be known _{MSB_REF} And V _{LSB_REF} There is a certain proportional relationship, namely:

（11）

continuing to derive:

（12）

suppose handleTarget reference voltage (e.g., first reference voltage V is selected) _{MSB_REF} ) As a new reference voltage V _REF Can obtain

Can be accurately obtained by resistance voltage division

。

Specifically, first, V is _{MSB_REF} As a new reference voltage V _REF According to the proportional relation of the formula (11), it can be deduced

。

In one embodiment, the target reference voltage is input by an external voltage source or provided by a bandgap reference circuit. In particular, a new reference voltage V _REF Can be directly input from the outside or directly provided by a band-gap reference circuit so as to quickly provide the required new reference voltage V _REF 。

In an embodiment, the process of generating the remaining segment of reference voltage by dividing the target reference voltage through resistors in step S18 may specifically include the following steps:

It can be understood that after determining the proportional relationship between the target reference voltage and the reference voltages of the other segments, for example, but not limited to, the proportional relationship shown in the above equation (11), that is, the proportional relationship can be obtained by serially dividing a plurality of resistor strings with resistance value R and adding operational amplifier buffer, and the reference voltages of the other segments can be obtained, taking the proportional relationship shown in the above equation (11) as an example: providing a new reference voltage V _REF After that, the air conditioner is started to work,

can be obtained by connecting 17 resistor strings with the resistance value R in series to divide voltage and add operational amplifier buffer, and the voltage can be obtained

. In addition, a similar approach can also be adopted, and

as a new reference voltage V _REF Obtained by connecting 17 resistors with resistance value R in series to divide voltage and add operational amplifier bufferV _{MSB_REF} . The new reference voltage and the rest reference voltage of the capacitor array with multi-section are set similarly.

In one embodiment, another example of a CDAC bridge capacitance integer design application for SAR ADCs is provided for greater intuition and ease of understanding of the above approach. It should be noted that the examples of the present application are only illustrative, and are not intended to limit the application of the method of the present application, and those skilled in the art can implement the CDAC bridge capacitance integer design application of different SAR ADCs on the technical concept of the above method.

According to the content of the design method, taking the CDAC for designing a 12-bit SAR ADC as an example:

firstly, a segmented DAC capacitor array 401 meeting the 12-bit SARADC is designed, a two-segment structure is adopted, as shown in FIG. 5, a high Duan Dianrong array 404 is 64C,32C,16C,8C,4C,2C and C respectively, a low-segment capacitor array 402 is 1695C, 8C,4C,2C and C respectively, and in order to meet the all-binary relation, a bridging capacitor 403 is

. The SARADC adopts a traditional switching mode and adopts bottom plate sampling, the reference voltage is Vref, and the connection potentials of the capacitor bottom plate are Vref, GND and Vin respectively.

Total capacitance value of low-section capacitor array

Array Total capacitance value of Duan Dianrong high

The bridge capacitor is

。

The fractional bridge capacitance C is then achieved by changing the corresponding capacitance weights by changing the low and high reference voltages, as shown in fig. 6 _S1 Optimized as unit capacitance C _S2 . The segment reference voltage 505 of the corresponding low-side capacitor is V _{LSB_REF} The segment reference voltage 506 of the high-side capacitor is V _{MSB_REF} . Capacitance C of new bridge capacitor 503 _S2 =C。

V is then deduced from the conservation of charge _{LSB_REF} And V _{MSB_REF} 。

As shown in fig. 6, compared with the capacitor array 501 before optimization, the output charge variation caused by the voltage variation of the lower plate of the corresponding capacitor should be the same, that is, the linearity of the DAC after optimization is ensured to be as good as the linearity of the DAC before optimization. Deducing V by using charge equivalence principle _{LSB_REF} And V _{MSB_REF} ：

Firstly, it is calculated that the lower plate of one high-order capacitor in the fractional bridging capacitor array 401 changes from GND to V _ref The voltage at the output terminal changes. It is then calculated that the same high-order capacitance changes from GND to V in the optimized capacitor array 501 _{MSB_REF} The voltage at the output terminal changes. According to the principle of charge equivalence, the voltage variation should be the same, i.e. V can be derived _{MSB_REF} . The specific derivation calculation is as follows:

in the fractional bridge capacitor array 401, when all capacitor lower plates are connected to GND, it is assumed that the voltage at the output end of the DAC is at this time

Calculating the charge stored on the capacitor as:

one of the high-order capacitors C _Mi The voltage of the lower polar plate is changed from GND to V _ref Time of day DAC outputTerminal voltage is

Calculating the charge stored on the capacitor as

According to conservation of charge

And then:

assuming a variation in the DAC output

And then:

when all the capacitor bottom plates in the optimized integer bridging capacitor array 501 are connected to the GND, the voltage at the output end of the DAC is assumed to be

Calculating the charge stored on the capacitor as:

the same high-order capacitance C in the integer segmented capacitor array 501 _Mi The voltage of the lower polar plate is changed from GND to V _{MSB_REF} At the output terminal of DAC, the voltage is

And calculating the charge stored on the capacitor as:

according to conservation of charge

And then:

assuming variations in the DAC output

And then:

the two capacitor arrays need to be equivalent, and the corresponding weights of the same high-order capacitor are the same, so that the same high-order capacitor C _Mi The DAC output variation caused by the bottom plate voltage variation needs to be kept consistent, i.e.

。

V can be deduced _{MSB_REF} ：

Similarly, it is calculated that the lower plate of one low-level capacitor of the fractional bridge capacitor array 401 is changed from GND to V _ref The voltage at the output terminal changes. It is then calculated that the same low-level capacitance changes from GND to V in the optimized integer-bridged capacitor array 501 _{LSB_REF} The voltage at the output terminal changes. According to the principle of charge equivalence, the voltage variation should be the same, i.e. V can be derived _{LSB_REF} . The specific derivation calculation is as follows:

when the change of the low-order capacitance is calculated to cause the change of the DAC output end, firstly, the DAC capacitance array is simplified as shown in figure 4, and the DAC capacitance array can be obtained according to a capacitance series-parallel calculation formula:

therefore, a low-level capacitor C of a certain bit in the fractional capacitor array 401 can be obtained _Li From 0 to V _ref Time, resulting output variation:

in the optimized integer capacitor array 501, the same low-order capacitor C _Li From 0 to V _{LSB_REF} Output variation caused by time:

according to the above formula, only the derivation is needed

The voltage variation of the output end can be obtained and derived

The specific process is as follows:

in the fractional bridge capacitor array 401, when all the capacitor lower plates are connected to GND, the voltage of the DAC lower-stage capacitor array top plate is assumed to be

Calculating the charge stored on the capacitor as:

low-section capacitor arrayColumn, one bit capacitor C _Li The voltage of the lower plate is changed from GND to V _ref At the output terminal of DAC, the voltage is

And calculating the charge stored on the capacitor as:

according to conservation of charge

Then:

it can therefore be deduced that:

the same can be obtained:

thus far derived

Therefore, it can be obtained that the change of the DAC output caused by the low bit change is:

two capacitor array requirementsEquivalently, the corresponding weights of the same low-level capacitor should be the same, so that the same low-level capacitor C _Li The DAC output variation caused by the voltage variation of the lower plate needs to be kept consistent, so

So that V can be deduced _{LSB_REF} ：

V has been determined by pushing the previous derivation _{LSB_REF} And V _{MSB_REF} Then, the proportional relationship between them is determined, namely:

to facilitate later calculations of the SAR ADC and to simplify circuit design, the reference voltage may be redefined as

Then, we can get:

therefore, only two reference voltages are needed to be divided, the same capacitance weight as the original fractional capacitor array can be realized, the subsequent calculation complexity can be reduced, and the SARADC conversion result is not influenced. And only need can obtain through resistance string partial pressure:

so far, the design that the fractional bridge capacitor of the segmented DAC capacitor array is subjected to integer by scaling of the reference voltage has been realized. And finally, a simulation circuit is built in the Cadence to simulate the linearity of the simulation circuit, the linearity is good, the 12-bit SARADC requirement is met, and INL (integral nonlinearity)/DNL (differential nonlinearity) obtained from the CDAC simulation result is shown in FIG. 7.

Using the segmented DAC capacitor array, the area reduction compared to the conventional capacitor is 96.096%, which is calculated as follows:

in the 12-bit design example, the total capacitance:

conventional DAC Total capacitance

. Reduced capacitor area compared to conventional DAC

By using the design, on the basis of not changing the corresponding capacitance weight, the unit capacitance of the bridge capacitor of the segmented DAC capacitor array is realized by scaling the reference voltage, the whole DAC is ensured to adopt the same type of capacitor, all the capacitance weights are ensured to accord with the binary relation, the good linearity of the capacitor array is ensured, meanwhile, no gain error is generated, the influence of the fractional capacitor on the precision is avoided, the layout is easy to realize, and the matching precision is high.

It should be understood that although the various steps in the flowchart of fig. 2 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps of fig. 2 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternatingly with other steps or at least a portion of the sub-steps or stages of other steps.

In one embodiment, an analog-to-digital converter is provided, which includes a segmented DAC capacitor array, wherein reference voltage ends of each segment of the DAC capacitor array are respectively connected to each segment of reference voltage in a one-to-one correspondence manner, and each segment of reference voltage is used for integer-quantizing bridge capacitors of the DAC capacitor array. The bridge capacitor integer of the DAC capacitor array is designed according to the design method.

It can be understood that, for the explanation of the segmented DAC capacitor array in this embodiment, the same principle can be understood with reference to the corresponding explanation in each embodiment of the above design method, and details are not described here. It can be understood by those skilled in the art that the analog-to-digital converter in this embodiment may include other existing structure besides the segmented DAC capacitor array, which is not listed in detail in this specification, and may be specifically determined by referring to the specific type of structure composition of the sar adc in the art. The analog-to-digital converter may be of various types known in the art employing segmented DAC capacitor arrays.

Compared with the traditional design method, the analog-to-digital converter has the advantages that the integral number of the bridging capacitor is realized by scaling the reference voltage on the basis of not increasing the total number of capacitors for the segmented CDAC with the existing digit number by applying the segmented DAC capacitor array designed by the design method, the same type of capacitors are adopted for the whole CDAC, the influence of fractional capacitors on the precision of the segmented CDAC is avoided, the layout is easy to realize, and the matching precision is high. In addition, by changing the value of the reference voltage, all the capacitance weights are ensured to accord with the binary relation, the good linearity of the capacitor array is ensured, and CDAC gain errors cannot be generated; compared with the traditional same-digit segmented CDAC, the capacitor array using the segmented CDAC has the advantage that the capacitor area can be greatly reduced.

In one embodiment, the DAC capacitor array comprises a three-segment segmented DAC capacitor array or a four-segment segmented DAC capacitor array. It is to be understood that, in this embodiment, based on the same design principle, the DAC capacitor array in the analog-to-digital converter may also be a three-segment segmented DAC capacitor array, for example, the DAC capacitor array includes a first segment capacitor array, a first bridge capacitor, a second segment capacitor array, a second bridge capacitor, and a third segment capacitor array, the original unified basic reference voltage is correspondingly divided, and three segment reference voltages are respectively set for connecting the corresponding three segment capacitor arrays. The integral design of the first bridging capacitor and the second bridging capacitor can be realized by adopting the design method in the same way.

Based on the same design principle, the DAC capacitor array in the analog-to-digital converter may also be a four-segment segmented DAC capacitor array, for example, the DAC capacitor array includes a first segment capacitor array, a first bridge capacitor, a second segment capacitor array, a second bridge capacitor, a third segment capacitor array, a third bridge capacitor, and a fourth segment capacitor array, the original unified basic reference voltage is correspondingly divided, and four segment reference voltages are respectively set for connecting the corresponding four segment capacitor arrays. The integral design of the first bridging capacitor, the second bridging capacitor and the third bridging capacitor can be realized by adopting the design method in the same way.

In one embodiment, the analog-to-digital converter includes an 8-bit SAR ADC, a 12-bit SAR ADC, a 14-bit SAR ADC, or a 16-bit SAR ADC. It is to be understood that the above-described bridge capacitor integer design of the present application may be applied to, but is not limited to, SAR ADCs of similar structures such as 8-bit SAR ADC, 12-bit SAR ADC, 14-bit SAR ADC, and 16-bit SAR ADC.

For specific limitations of the analog-to-digital converter, reference may be made to the corresponding limitations of the above segmented CDAC bridging capacitance integer design method, and details are not repeated here.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several variations and modifications can be made without departing from the spirit of the present application. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims

1. A segmented CDAC bridge capacitor integer design method is characterized by comprising the following steps:

keeping the capacitance value of each section of capacitor array in the DAC capacitor array unchanged, and respectively connecting the reference voltage ends of each section of capacitor array to each section of reference voltage in a one-to-one correspondence manner; the reference voltages of all the sections are used for carrying out integer formation on the bridge capacitance of the DAC capacitor array;

respectively calculating DAC output variable quantities before and after the bridge capacitor is subjected to integral change according to the conservation of charge stored by the capacitor array when the voltage of the lower electrode plate of each capacitor array section is changed, and calculating to obtain the reference voltage of each capacitor section by utilizing the equal DAC output variable quantities before and after the integral change of the bridge capacitor;

determining a target reference voltage of the DAC capacitor array, and generating the rest reference voltages through resistance voltage division according to the target reference voltage to complete integral design of the segmented CDAC bridging capacitor; the target reference voltage is one of all the segment reference voltages.

2. The method of claim 1, wherein the array of DAC capacitors comprises an array of low stage capacitors, an array of high stage capacitors Duan Dianrong, and a bridge capacitor.

3. The method of claim 2, wherein the segment reference voltages comprise a first reference voltage and a second reference voltage, the high Duan Dianrong array is correspondingly connected to the first reference voltage, and the low segment capacitor array is correspondingly connected to the second reference voltage;

according to the conservation of the stored charges of the capacitor array when the voltage of the lower electrode plate of each capacitor array section changes, respectively calculating the DAC output variable quantity before and after the integral change of the bridging capacitor, and calculating by using the DAC output variable quantity to obtain the reference voltage of each section, the method comprises the following steps:

when all capacitor lower plates in the DAC capacitor array before the reference voltage is divided are grounded, determining the first DAC output variation caused by the fact that the voltage of the lower plate of any bit capacitor in the high Duan Dianrong array is changed from the ground to the basic reference voltage;

when the lower plates of a high-order capacitor and a low-order capacitor in the DAC capacitor array after the reference voltage is divided are grounded, determining the second DAC output variation caused by the fact that the voltage of the lower plate of any one-order capacitor in the high Duan Dianrong array is changed from the ground to the first reference voltage; the lower polar plates of the low-level capacitors are all grounded;

4. The method according to claim 3, wherein the step of calculating DAC output variation before and after the bridge capacitor integer according to conservation of charge stored in the capacitor array when the voltage of the lower plate of each capacitor array changes, and obtaining the reference voltage of each capacitor array by using the DAC output variation further comprises:

when all capacitor lower plates in the DAC capacitor array before the reference voltage is divided are grounded, determining the variation of the output of a third DAC caused by the fact that the voltage of the lower plate of any bit capacitor in the low-section capacitor array is changed from the ground to the basic reference voltage;

when all capacitor lower plates in the DAC capacitor array after the reference voltage is divided are grounded, determining the change of the fourth DAC output caused by the change of the voltage of the lower plate of any bit capacitor in the low-section capacitor array from the ground to the second reference voltage; the lower polar plates of the high-order capacitors are all grounded;

5. The method for designing integer capacitance of segmented CDAC bridge circuit according to any one of claims 1 to 4, wherein the target reference voltage is inputted by an external voltage source or provided by a bandgap reference circuit.

6. The method of claim 5, wherein the step of generating the remaining segment reference voltages by resistive division according to the target reference voltage comprises:

and according to the proportional relation between the target reference voltage and the rest of the segment reference voltages, obtaining the rest of the segment reference voltages by adopting series resistor voltage division and operational amplifier buffering.

7. The analog-to-digital converter is characterized by comprising a segmented DAC capacitor array, wherein reference voltage ends of all segments of the DAC capacitor array are respectively connected to all segments of reference voltages in a one-to-one correspondence manner, and the all segments of reference voltages are used for integrating bridge capacitors of the DAC capacitor array; wherein the bridge capacitance of the DAC capacitor array is designed according to the design method of any one of claims 1 to 6.

8. The analog-to-digital converter of claim 7, wherein the array of DAC capacitors comprises an array of low-section capacitors, an array of high Duan Dianrong, and a bridge capacitor.

9. The analog-to-digital converter of claim 7, wherein the DAC capacitor array comprises a three-segment segmented DAC capacitor array or a four-segment segmented DAC capacitor array.

10. The analog-to-digital converter according to claim 8 or 9, characterized in that the analog-to-digital converter comprises an 8-bit SAR ADC, a 12-bit SAR ADC, a 14-bit SAR ADC or a 16-bit SAR ADC.