CN114489239B - Method and device for dynamically calibrating real-time clock - Google Patents
Method and device for dynamically calibrating real-time clock Download PDFInfo
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Abstract
The invention discloses a method and a device for dynamically calibrating a real-time clock. A method for dynamically calibrating a real-time clock, comprising: step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period; step 2, counting the local clocks in each calibration period, and obtaining a dynamic calibration target set; and 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period. The invention can accurately calibrate the local clock, and avoid the delay and CPU burden of software calibration.
Description
Technical Field
The present invention relates to the field of real-time clock calibration technologies, and in particular, to a method and an apparatus for iterative dynamic calibration of a real-time clock.
Background
The reference clock for the Real Time Clock (RTC) operation typically sources an internal crystal Oscillator (OSC). The difference between crystal oscillator precision is a ubiquitous objective phenomenon, and the OSC also changes in frequency in different working temperature environments and different working humidity environments, namely the phenomenon that the industry mentions frequency deviation.
Under the condition that the crystal oscillator precision is affected, the timing state or result inside the RTC can lead to accumulation errors due to frequency deviation, if the accumulation errors are not timely counteracted, the timing result of the local RTC and an actual external time reference are caused to deviate, and negative influence is brought to the field of time synchronization required by multi-system interaction.
The error of the RTC crystal exists objectively, so many related design fields include implementation of calibrating the internal crystal oscillator of the RTC. The implementation is also a variety, including software calibration (with low requirements on calibration accuracy), hardware calibration (with high requirements on calibration accuracy). Common software calibration is to perform periodic compensation correction on time data based on real-time timing of the RTC through operation of periodic software instructions so as to achieve the expectation of calibration. Software calibration is a periodic and timed behavior requiring the application of timing queries to initiate the tasks of the CPU, which can result in bus bandwidth occupation and CPU running overhead.
Disclosure of Invention
In order to solve the technical problems of overhead and hysteresis caused by software calibration in the prior art, the invention provides a method and a device for dynamically calibrating a real-time clock.
The method for dynamically calibrating the real-time clock provided by the invention comprises the following steps:
Step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period;
step 2, counting the local clocks in each calibration period, and obtaining a dynamic calibration target set;
and 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
Further, the start time of the calibration period is the detection time of the falling edge of the local clock by the reference clock.
Further, the dynamic calibration target set includes: and error analysis results, and one of an up-conversion compensation calibration operation, a down-conversion compensation calibration operation, and a compensation-unnecessary calibration operation.
Further, calibrating the local clock based on the up-conversion compensation calibration operation specifically includes:
Generating an in-phase derived clock having a duty cycle other than 50%, and the in-phase derived clock and the local clock being the same frequency and the same phase;
Generating an inverted derivative clock having a duty cycle other than 50%, and the inverted derivative clock and the local clock being the same frequency and 180 ° out of phase;
Defining a compensation time slot counter, wherein the maximum counting value of the compensation time slot counter is the error analysis result;
and extracting the clock of the designated compensation time slot in the reverse derivative clock at the jump time of each compensation time slot counter, and generating a fast compensation clock as a calibrated real-time clock after being fused with the homodromous derivative clock.
Further, calibrating the local clock based on the down-conversion compensation calibration operation specifically includes:
Generating an in-phase derived clock having a duty cycle other than 50%, and the in-phase derived clock and the local clock being the same frequency and the same phase;
defining a shielding time slot counter, wherein the maximum counting value of the shielding time slot counter is the error analysis result;
And shielding clock pulses corresponding to the in-phase derived clock at the jump time of each shielding time slot counter, and generating a slow compensation clock as a calibrated real-time clock.
Further, the duty cycle of the in-phase derived clock is 20%.
Further, the duty cycle of the inverted derived clock is 20%.
And further, taking the calibrated real-time clock as a local clock to be calibrated to execute the steps 1 to 3 until the obtained calibrated real-time clock reaches a preset calibration expectation.
Further, the error analysis result is an average value corresponding to the calibration analysis of the plurality of calibration periods, or a real-time value corresponding to the calibration analysis of each calibration period.
In step 3, when the error analysis result meets the effective calibration interval, the local clock is calibrated.
The device for dynamically calibrating the real-time clock comprises a reference clock and a local clock to be calibrated, wherein the method for dynamically calibrating the local clock comprises the following steps:
The calibration period generation module monitors the phases of the reference clock and the local clock and obtains a calibration period;
the frequency deviation error analysis and extraction module counts the local clock in each calibration period and obtains a frequency deviation error and a dynamic calibration target set;
and the calibration output module is used for calibrating the local clock according to the dynamic calibration target set of the last calibration period.
Further, the calibration period generation module includes: the device comprises a reference clock and local clock initial phase alignment monitoring unit, a calibration period initial event generating unit and a calibration period end event generating unit.
Further, the frequency offset error analysis and extraction module includes: the error analysis corresponds to a counter CNT (analysis), a local clock frequency offset error analysis extraction unit.
Further, the calibration output module includes: the device comprises a local clock in-phase deriving unit, a local clock anti-phase deriving unit and a derived clock fusion output unit.
The invention can automatically construct a high-precision calibration period based on phase alignment, and meanwhile, the initial phase alignment of the reference clock and the local clock is beneficial to improving the precision of local clock error analysis, the derivative clock of the local clock can realize dynamic real-time calibration of the local clock, and the derivative clock obtained after the local clock calibration is subjected to secondary or iterative calibration so as to achieve the purpose of precision confirmation or improving the calibration precision. Such as a calibration period expansion coefficient, for expanding the actual calibration period. Through adjustment of the calibration period expansion coefficient, calibration targets with different error magnitudes can be met or considered. The reference clock and the local clock start phase alignment monitoring unit are used for monitoring and ensuring that at the moment of phase alignment, the generation of a calibration period is started, the calibration count analysis is started, the starting point of the corresponding count of the error analysis is determined in the calibration period, and the determined error is fed back to the calibration parameter.
According to the invention, the frequency deviation is acquired in real time, so that the storage resources of the frequency deviation mapping table are reduced, and the delay of storing or acquiring the frequency deviation coefficient is reduced. The counting module of the frequency offset error is a cycle counter, and is combined with a calibration period expansion coefficient to count corresponding times of cycles; after the calibration period ends, the cycle counter locks the history count value, so that the corresponding relation between the cycle count value and the error analysis result can be conveniently and rapidly established. The error analysis result can provide subsequent calibration operation in real time, so that the operations of memory writing and loading reading back are reduced, and the delay of calibration is avoided.
When the error analysis exceeds the expected calibration range, the effective calibration interval of the invention reports a serious error state. So that the application can reconfigure the calibration target range or forgo the calibration operation as desired. The effective calibration interval is a configuration parameter and controls the starting of the calibration operation; when the error analysis result is in the range of the effective calibration interval, automatically starting the calibration operation; otherwise, the calibration operation is abandoned, and the state related to errors can be selectively reported. The idea of an effective calibration interval avoids the negative problems of unnecessary calibration power consumption or other design overhead.
The derivative clock can effectively avoid the operation of calibrating the count value of the clock counter. And the phenomenon of uneven time jump in the process of acquiring sub-second timing information is avoided. In different time intervals, according to different error analysis results in current real time, the up-conversion compensation calibration operation, the down-conversion compensation calibration operation and the compensation calibration operation are possibly dynamically selected so as to realize dynamic calibration. And the local clock derived clock fusion output module is used for carrying out fusion processing on the local clock same-phase derived clock and the designated time slot in the local clock opposite-phase derived clock according to the dynamic calibration target set defined by the invention to generate a local clock calibrated fast compensation calibration clock. Or the dynamic calibration target set defined by the invention carries out shielding processing on the appointed time slot in the local clock same-phase derivative clock to generate the slow compensation calibration clock for local clock calibration. The fusion process is to uniformly up-convert or planarize up-convert in the calibration period, so that the clocks are fused uniformly and grouped in one complete calibration period. The masking process is a uniform down-conversion or a flattened down-conversion over the calibration period, so that the clock masks are grouped uniformly over a complete calibration period. According to the invention, a local clock frequency offset error analysis and extraction module and a local clock calibration output module can be additionally added, and the derivative clock calibrated by the local clock is recalibrated. The calibration derivative clock feedforward accuracy confirmation is realized by starting an iterative calibration mode, and the finally output calibration real-time clock can approach to actual calibration expectation after multiple dynamic calibration.
Drawings
The invention is described in detail below with reference to examples and figures, wherein:
FIG. 1 is a block diagram of a calibration period generation module of the present invention.
Fig. 2 is a block diagram of a frequency offset error analysis extraction module according to the present invention.
FIG. 3 is a block diagram of a calibration output module according to the present invention.
Fig. 4 is a schematic diagram of a data flow according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a non-iterative calibration mode of the present invention.
FIG. 6 is a schematic diagram of a one-time iterative calibration mode of the present invention.
FIG. 7 is a schematic diagram of a second iteration calibration mode of the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.
Before describing embodiments of the present invention, two clock and calibration periods of the present invention are declared: CLK (accurate) is a high-precision clock, i.e., a reference clock, provided externally or integrated internally in the present embodiment. CLK (local) is the local clock to be calibrated in this embodiment, and the calibration target clock common to RTC is: osc32.768k internal clock (ocs 32.768k internal clock can be understood as a typical example of CLK (local)), the time span of the basic calibration period T (cali) is 32 seconds, corresponding to example OSC32.768K herein, in other embodiments, the time span of the basic calibration period can be adjusted as needed.
The calibration period is determined according to the basic calibration period and the calibration period expansion coefficient, and after the calibration period expansion coefficient is determined, the time span of the calibration period corresponds to a constant time interval, and the calibration period T (cali_ext) =t (cali) x N (coe). The calibration period expansion coefficient N (coe) adjusts the calibration period to correspond to different calibration precision levels, and meanwhile solves the possible irregularity of instantaneous frequency deviation of the local clock CLK (local) to be calibrated, so that the error statistical average value can be better obtained in the proper calibration period.
The invention relates to a method for dynamically calibrating a real-time clock, which comprises the following basic steps: the method comprises the steps of monitoring and aligning phases of a reference clock and a local clock to be calibrated, obtaining calibration periods according to a period expansion coefficient and a basic calibration period, counting the local clock in each calibration period, obtaining a dynamic calibration target set, and calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
Correspondingly, the device for dynamically calibrating the real-time clock of the invention comprises: the device comprises a calibration period generation module, a frequency deviation error analysis extraction module and a calibration output module. The calibration period generation module monitors phases of the reference clock and the local clock and obtains a calibration period. The frequency deviation error analysis and extraction module counts the local clock in each calibration period and obtains a frequency deviation error and a dynamic calibration target set. And the calibration output module calibrates the local clock according to the dynamic calibration target set of the last calibration period.
As shown in fig. 1 and fig. 4, the calibration period generating module mainly includes three parts, namely a reference clock and local clock start phase alignment monitoring unit, a calibration period start event generating unit and a calibration period end event generating unit.
The reference clock and local clock start phase alignment monitor unit generates a precise check period by using the reference clock CLK (accurate), and starts the local clock CLK (local) to generate the count of the error analysis counter CNT (analysis) after the reference clock CLK (accurate) starts the count. If there is no processing of the reference clock and the local clock start phase alignment monitoring unit, the start time of the counting of the error analysis counter CNT (analysis) is uncertain, the earliest count start time may be at least one CLK (clock) delay after the calibration period is generated, the latest count start time may be at least one CLK (local) delay after the calibration period is generated, CLK (clock) is an M-stage clock, CLK (local) is a K-stage clock, and both clocks have a clock frequency of the order of 1000 times, it is obvious that an uncertain error value is introduced before the calibration operation is entered. The reference clock and local clock start phase alignment monitoring unit is an asynchronous clock phase monitoring module, and takes into consideration that in an actual circuit, the phase relation of a high-precision reference clock CLK (accurate) and a local clock CLK (local) is random, and the reference clock and local clock start phase alignment monitoring unit is used for avoiding uncertainty errors caused by uncertainty of clock phases of the reference clock and the local clock start phase alignment monitoring unit. The reference clock and the local clock initial phase alignment monitoring unit can be clock phase monitoring circuits or asynchronous signal sampling mechanisms in digital circuit design, and the reference clock and the local clock initial phase alignment monitoring unit are based on a specific implementation form of the phase alignment thought in the invention, and can avoid the introduction of uncertain error analysis results through the pre-processing of the reference clock and the local clock initial phase alignment monitoring unit.
The calibration period start event generating unit is a reference clock and local clock start phase alignment monitoring unit that determines a start count time of a reference clock CLK (accurate) generation check period, and also determines a start count time of a local clock CLK (local) within a calibration period. In a preferred embodiment, the calibration period start event generation time is the time when the reference clock CLK (accurate) detects the falling edge of the local clock CLK (local), so that it can be ensured that after the reference clock CLK (accurate) generates the calibration period window, the counting operation corresponding to the error analysis of the rising edge of the CLK (local) is started immediately after 0.5 CLK (local) clock cycles. The 0.5 CLK (local) clock period is a deterministic count delay that can be accounted for by the 0.5 CLK (local) period count delay to the error analysis result. The calibration period window referred to herein is illustrated as "32 seconds where the base calibration period is constant". If the reference clock CLK (accurate) is 50M, the basic calibration period of 32 seconds corresponds to the upper count limit of 50x1000x1000x32, counting based on the 50M clock corresponds to the "basic calibration period window" from 0 to 50x1000x1000x32, and the calibration period window also needs to incorporate the calibration period expansion coefficient.
The calibration period end event generating unit is configured to set the reference clock CLK (accurate) as the count start point at the calibration period start event, and to set the total number of periods of the reference clock CLK (accurate) corresponding to the calibration period T (cali_ext) as the cali_cycle_max based on the total number of periods, and to define the calibration period end event when the calibration period counter CNT (ref) reaches the cali_cycle_max count time.
The calibration period identification indication signal generation unit shown in the figure is not an actual hardware unit, but classifies two signals, and generates indication signals of corresponding calibration period span intervals based on a calibration period start event generation and a calibration period end event generation.
As shown in fig. 2 and fig. 4, the frequency offset error analysis and extraction module includes an error analysis counter CNT (analysis) and a local clock frequency offset error analysis and extraction unit.
The calibration period is between the calibration period starting event and the calibration period ending event, the error analysis of the local clock CLK (local) takes the calibration period starting event and the calibration period ending event as interval references, and when the error analysis corresponding counter CNT (analysis) appears after the calibration starting event, the count is cleared to 0; the count continues with a step size of 1 before the calibration period end event occurs. In a preferred embodiment, when the expansion coefficient N (coe) is defined as an integer value greater than 1, the error analysis counter CNT (analysis) presents a CYCLE count for several times, the number of CYCLEs is consistent with the defined value or configuration of the calibration CYCLE expansion coefficient N (coe), the upper limit value of the CYCLE count is the number of CYCLEs of the basic calibration CYCLE T (cali) corresponding to the local clock CLK (local), the number of CYCLEs is defined as cnt_cycle_max, and the counting result of the error analysis counter CNT (analysis) can quickly establish a corresponding relationship with the error analysis result by adopting a CYCLE counting manner. After the calibration period end event occurs, the error analysis corresponding counter CNT (analysis) holds the count history value until the count of the error analysis corresponding counter CNT (analysis) is cleared to 0 after the next calibration start event occurs.
The local clock frequency offset error analysis extraction unit extracts an error analysis result CALI_PARA, and each updated value of the parameter of the error analysis result CALI_PARA occurs at the moment when a calibration period is ended. The error analysis result cali_para may be an average value corresponding to the multiple periodic calibration analysis, or may be a real-time value corresponding to each periodic calibration analysis. In a preferred embodiment, after the calibration period end event occurs, the error analysis counter CNT (analysis) keeps counting the historical value as the error analysis result cali_para.
After the local clock frequency offset error analysis extraction unit extracts the error analysis result CALI_PARA, the condition of entering an automatic calibration flow is that an effective calibration interval defined by the invention must be satisfied, for some OSCs with large frequency offset errors, the subsequent calibration of possible inherent defects is not engineering practice significance, and the invention gives the idea of screening OSCs with crystal oscillator errors exceeding the effective calibration interval. When the error analysis result cali_para exceeds the definition range of the effective calibration interval, the action of the automatic calibration clock will not be generated, but the state information of the OSC serious error is fed back, and the information can be output in real time in the modes of state, interrupt, trigger event and the like.
The dynamic calibration target set of the invention comprises: and error analysis results, and one of an up-conversion compensation calibration operation, a down-conversion compensation calibration operation, and a compensation-unnecessary calibration operation. A parameter CFG (expect_ppm_max) defining the effective calibration interval. In a preferred embodiment, when the error analysis result CALI_PARA_E [ CNT_CYCLE_MAX-CFG (expect_ppm_max), CNT_CYCLE_MAX ] correspondingly performs an up-conversion compensation calibration operation; and when the CALI_PARA is equal to the CNT_CYCLE_MAX, the compensation calibration operation is not needed correspondingly.
The dynamic calibration target set is dynamic data obtained based on the error analysis result of each calibration period or several calibration periods. The three compensation operations of the dynamic calibration target set are mutually exclusive within the same time interval (the same time interval corresponds to the minimum unit: such as a calibration period). In special application scenarios, such as a situation of large temperature drift of the OSC in an actual working environment (calibration requirement of OSC in a plurality of environment temperatures of normal temperature, low temperature and high temperature for staggered operation), the frequency-up compensation calibration operation, the frequency-down compensation calibration operation and the calibration operation without compensation can be implemented in different time intervals. For a better understanding of the three compensation operations in the dynamic calibration target set described in the present invention, it is illustrated below that T1 (temperature 1), T2 (temperature 2), T3 (temperature 3) represent the time span of three consecutive calibration periods, including three different ambient temperatures. After the end of the calibration period of T1, T2, T3, different compensation operations can occur in the limit, possible case 1: { up-conversion compensation calibration operation, down-conversion compensation calibration operation, no compensation calibration operation required }; possible case 2{ no compensation calibration operation, up-conversion compensation calibration operation, down-conversion compensation calibration operation }: possible case 3: { Down Compensation calibration operation, up Compensation calibration operation, compensation free calibration operation }. Under the condition that the calibration period is taken as granularity, the dynamic calibration target set defined by the invention can meet the specific implementation requirement of dynamic calibration.
As shown in fig. 3 and fig. 4, the calibration output module includes a local clock in-phase deriving unit, a local clock anti-phase deriving unit, and a derived clock fusion output unit.
The local clock in-phase derivative unit is used to generate an in-phase derivative clock clk_p (derivative) signal with a duty cycle other than 50% (20% duty cycle is a preferred embodiment). The clock of the in-phase derived clock clk_p (derivative) and the local clock CLK (local) are in phase with the same frequency.
The local clock inverse phase deriving unit is used for generating an inverse derived clock CLK_N (derive) signal with a duty cycle of not 50% (20% duty cycle is a preferred embodiment); the inverted derivative clock clk_n (derivative) and the local clock CLK (local) are 180 ° out of phase.
The derived clock fusion output unit is used for outputting the calibrated real-time clock according to the dynamic calibration target set.
Specifically, calibrating the local clock based on the up-conversion compensation calibration operation specifically includes: generating an in-phase derived clock having a duty cycle other than 50%, and the in-phase derived clock and the local clock being the same frequency and the same phase; generating an inverted derivative clock having a duty cycle other than 50%, and the inverted derivative clock and the local clock being the same frequency and 180 ° out of phase; defining a compensating time slot counter of an inverse derived clock CLK_N (derive), wherein the maximum counting value of the compensating time slot counter is an error analysis result; and extracting the clock of the designated compensation time slot of the reverse derivative clock at the jump time of each compensation time slot counter, and generating a fast compensation clock as a calibrated real-time clock after merging the clock of the designated compensation time slot with the homodromous derivative clock.
The counting range of the compensation time slot counter is monotonously increased, and the maximum value is the error analysis result CALI_PARA of the dynamic calibration target set, and the jump time of the compensation time slot counter is the fast compensation time slot defined by the invention. After the fast compensation time slot is determined, the in-phase derived clock clk_p (derivative) clock pulses with the total error analysis result cali_para can be extracted, and in the preferred embodiment mentioned above, the duty ratio of the in-phase derived clock clk_p (derivative) and the reverse derived clock clk_n (derivative) is 20%, which is favorable for avoiding the situation of burrs and clock overlapping in the generation process of the fast compensation clock CLK (merge_fast).
In the real-time clock of the sub-second level, the application of accessing the real-time clock of the continuous microsecond level is often concerned, and in a more preferred embodiment, the monotonically increasing counting behavior of the compensation time slot counter is uniformly distributed in the whole check period, and the microsecond time of accessing the real-time clock from the application angle is similar to an OSC timing system with very high access precision. In the generation process of the fast compensation clock CLK (merge_fast), the frequency is evenly increased or flattened in the calibration period, so that the jump problem of continuous access to sub-second time can be effectively avoided.
Calibrating the local clock based on the down-conversion compensation calibration operation specifically comprises: generating an in-phase derived clock with a duty cycle other than 50%, wherein the in-phase derived clock and the local clock have the same frequency and the same phase; defining a shielding time slot counter, wherein the maximum counting value of the shielding time slot counter is an error analysis result; and shielding clock pulses corresponding to the in-phase derived clock at the jump time of each shielding time slot counter, and generating a slow compensation clock as a calibrated real-time clock. In a preferred embodiment, the duty cycle of the in-phase derived clock clk_p (derive) is 20%, which is advantageous in avoiding glitch and clock overlap during the generation of the fast compensation clock CLK (merge_fast).
In the generation process of the slow compensation clock CLK (merge_slow), the clock is uniformly down-converted or flattened down-converted in a calibration period, so that the rebound problem of continuous access sub-second time can be avoided.
The clock switching action of the derived clock fusion output unit is based on a dynamic calibration target set (up-conversion compensation calibration operation mark, down-conversion compensation calibration operation mark, no compensation calibration operation mark), and the sources of the calibrated derived clock CLK (cali) (also called as the calibrated real-time clock) include the following three possibilities: when the up-conversion operation compensation is needed, outputting CLK (merge_fast); when the down-conversion operation compensation is needed, outputting CLK (merge_slow); when clock compensation is not needed (no error exists in the local OSC), CLK (local) or clk_p (derive) or clk_n (derive) can be directly output, and in the derivative clock scheme described in the present invention, these three clocks are at the same frequency, but the difference of phase differences.
The clock switching action of the derived clock fusion output unit is based on a dynamic calibration target set (an up-conversion compensation calibration operation mark, a down-conversion compensation calibration operation mark, a calibration operation mark without compensation), and the calibration target set corresponding to the current calibration period is registered and acts on the next calibration period to perform any operation of up-conversion, down-conversion and calibration without compensation. The error analysis and the calibration operation approximate to pipeline operation tasks, reach the expectation of dynamic calibration mentioned in the invention, ensure to select the 'up-conversion compensation calibration operation' or the 'down-conversion compensation calibration operation' or the 'no compensation calibration operation' in the range that the calibration period is granularity, and reach the effect of dynamically calibrating the real-time clock with the calibration period as granularity.
Based on the dynamic calibration of the real-time clock, in a preferred embodiment, a process of recalibrating and confirming the derived clock CLK (cali) is also designed, that is, the feedforward accuracy of the derived clock is confirmed, which corresponds to the iterative calibration mode in the specific embodiment, as shown in fig. 6 and 7. The mode corresponding to the iterative calibration mode is a non-iterative calibration mode, as shown in fig. 5.
The derived clock feedforward accuracy confirmation needs to be additionally provided with a reference clock calibration period generating unit, a local clock frequency deviation error analysis extracting unit and a local clock calibration output unit, and the derived clock CLK (cali) is obtained by utilizing the high-accuracy clock source of the reference clock CLK (accurate) and after the early calibration, and then the calibration confirmation is carried out. When the corresponding dynamic calibration target set, the error analysis result cali_para=cnt_cycle_max, indicates that the derived clock CLK (CALI) has been calibrated to the desired degree, meeting the accuracy calibration expectations. Otherwise, according to the dynamic calibration target set (the up-conversion compensation calibration operation mark and the down-conversion compensation calibration operation mark) in the additionally added local clock frequency offset error analysis and extraction module, the additionally added local clock calibration output module is utilized to perform corresponding up-conversion compensation calibration operation or down-conversion compensation calibration operation.
As shown in fig. 6 and fig. 7, the calibrated real-time clock may be further used as a local clock to be calibrated to perform basic steps, that is, monitor and align phases of the reference clock and the local clock to be calibrated, obtain calibration periods according to the period expansion coefficient and the basic calibration period, count the local clock in each calibration period, obtain a dynamic calibration target set, and calibrate the local clock according to the dynamic calibration target set of the previous calibration period. The basic steps may be repeated one or more times until the calibrated real time clock reaches a preset calibration expectation.
The calibration clock generated by the non-iterative calibration mode is CLK (cali), and the CLK (cali) is the local clock CLK (local) which is generated after passing through the local clock frequency offset error analysis and extraction module and the local clock calibration output module.
The calibration clock generated by the iterative calibration mode is CLK (cali-fix), the CLK (cali-fix) is defined as a real-time clock to be calibrated, and the CLK (cali-fix) is processed by an additional reference clock calibration period generating module, an additional local clock frequency offset error analyzing and extracting module and an additional local clock calibration output module to generate the iterative calibration clock.
The number of the iteration times of the calibration clock generated by the iteration calibration mode is not limited to 1, and can be expanded to a plurality of times, and the number of the reference clock calibration period generation module, the local clock frequency offset error analysis extraction module and the local clock calibration output module is correspondingly increased when the iteration is carried out for a plurality of times. In the method, the local clock CLK (local) to be calibrated is calibrated with the iterative calibration mode to confirm the calibration precision or calibrate the local clock twice, and CLK (cali-fix), CLK (cali-fix 2) and CLK (cali-fix 3) are derived, so that the precision calibration expectation of the local clock CLK (local) can be approximated.
Because the invention adopts hardware to realize dynamic iteration, the CLK (cali) of the N-th calibration period and the CLK (cali-fix) of the N-1-th calibration period can be processed in parallel, and N is larger than 1. The CLK (cali) of the N-th calibration period, the CLK (cali-fix) of the N-1 th calibration period and the CLK (cali-fix 2) of the N-2 nd calibration period can be processed in parallel, and N is larger than 2, so on.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (20)
1. A method for dynamically calibrating a real-time clock, comprising:
Step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period;
Step 2, counting the local clocks in each calibration period, and obtaining a dynamic calibration target set; the dynamic calibration target set includes: error analysis results and up-conversion compensation calibration operation;
Step 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period;
Calibrating the local clock based on the up-conversion compensation calibration operation specifically comprises:
Generating an in-phase derived clock having a duty cycle other than 50%, and the in-phase derived clock and the local clock being the same frequency and the same phase;
Generating an inverted derivative clock having a duty cycle other than 50%, and the inverted derivative clock and the local clock being the same frequency and 180 ° out of phase;
Defining a compensation time slot counter, wherein the maximum counting value of the compensation time slot counter is the error analysis result;
and extracting the clock of the designated compensation time slot in the reverse derivative clock at the jump time of each compensation time slot counter, and generating a fast compensation clock as a calibrated real-time clock after being fused with the homodromous derivative clock.
2. The method of dynamically calibrating a real time clock according to claim 1, wherein the start time of the calibration period is the time of detection of the falling edge of the local clock by the reference clock.
3. The method of dynamically calibrating a real time clock according to claim 1, wherein the duty cycle of the in-phase derived clock is 20%.
4. The method of dynamically calibrating a real time clock according to claim 1, wherein the duty cycle of the inverted derived clock is 20%.
5. The method according to claim 1, wherein the steps 1 to 3 are executed by taking the calibrated real-time clock as the local clock to be calibrated, until the calibrated real-time clock reaches a preset calibration requirement.
6. The method of dynamically calibrating a real-time clock according to claim 1, wherein the error analysis result is an average value corresponding to the calibration analysis for a plurality of calibration periods or a real-time value corresponding to the calibration analysis for each calibration period.
7. The method for dynamically calibrating a real-time clock according to claim 1, wherein in the step 3, the local clock is calibrated only when the error analysis result satisfies the valid calibration interval.
8. A method for dynamically calibrating a real-time clock, comprising:
Step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period;
Step 2, counting the local clocks in each calibration period, and obtaining a dynamic calibration target set; the dynamic calibration target set includes: error analysis results and frequency-reducing compensation calibration operation;
Step 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period;
calibrating the local clock based on the down-conversion compensation calibration operation specifically includes:
Generating an in-phase derived clock having a duty cycle other than 50%, and the in-phase derived clock and the local clock being the same frequency and the same phase;
defining a shielding time slot counter, wherein the maximum counting value of the shielding time slot counter is the error analysis result;
And shielding clock pulses corresponding to the in-phase derived clock at the jump time of each shielding time slot counter, and generating a slow compensation clock as a calibrated real-time clock.
9. The method of dynamically calibrating a real time clock according to claim 8, wherein the start time of the calibration period is the time of detection of a falling edge of the local clock by the reference clock.
10. The method according to claim 8, wherein the steps 1 to 3 are executed by taking the calibrated real-time clock as the local clock to be calibrated again until the calibrated real-time clock reaches the preset calibration requirement.
11. The method of dynamically calibrating a real-time clock according to claim 8, wherein the error analysis result is an average value corresponding to the calibration analysis for a plurality of calibration periods or a real-time value corresponding to the calibration analysis for each calibration period.
12. The method for dynamically calibrating a real-time clock according to claim 8, wherein in the step 3, the local clock is calibrated only when the error analysis result satisfies the valid calibration interval.
13. An apparatus for dynamically calibrating a real time clock, comprising a reference clock and a local clock to be calibrated, wherein the local clock is dynamically calibrated by a method according to any one of claims 1-7, further comprising:
The calibration period generation module monitors the phases of the reference clock and the local clock and obtains a calibration period;
the frequency deviation error analysis and extraction module counts the local clock in each calibration period and obtains a frequency deviation error and a dynamic calibration target set;
and the calibration output module is used for calibrating the local clock according to the dynamic calibration target set of the last calibration period.
14. The apparatus for dynamically calibrating a real-time clock according to claim 13, wherein the calibration period generation module comprises: the device comprises a reference clock and local clock initial phase alignment monitoring unit, a calibration period initial event generating unit and a calibration period end event generating unit.
15. The apparatus for dynamically calibrating a real-time clock according to claim 13, wherein the frequency offset error analysis extraction module comprises: the error analysis corresponds to the counter CNT and the local clock frequency offset error analysis and extraction unit.
16. The apparatus for dynamically calibrating a real-time clock according to claim 13, wherein the calibration output module comprises: the device comprises a local clock in-phase deriving unit, a local clock anti-phase deriving unit and a derived clock fusion output unit.
17. An apparatus for dynamically calibrating a real time clock, comprising a reference clock and a local clock to be calibrated, wherein the local clock is dynamically calibrated using the method of any of claims 8-12, further comprising:
The calibration period generation module monitors the phases of the reference clock and the local clock and obtains a calibration period;
the frequency deviation error analysis and extraction module counts the local clock in each calibration period and obtains a frequency deviation error and a dynamic calibration target set;
and the calibration output module is used for calibrating the local clock according to the dynamic calibration target set of the last calibration period.
18. The apparatus for dynamically calibrating a real-time clock according to claim 17, wherein the calibration period generation module comprises: the device comprises a reference clock and local clock initial phase alignment monitoring unit, a calibration period initial event generating unit and a calibration period end event generating unit.
19. The apparatus for dynamically calibrating a real-time clock according to claim 17, wherein the frequency offset error analysis extraction module comprises: the error analysis corresponds to the counter CNT and the local clock frequency offset error analysis and extraction unit.
20. The apparatus for dynamically calibrating a real-time clock according to claim 17, wherein the calibration output module comprises: the device comprises a local clock in-phase deriving unit, a local clock anti-phase deriving unit and a derived clock fusion output unit.
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| CN113346881A (en) * | 2021-05-27 | 2021-09-03 | 珠海东之尼电子科技有限公司 | Digital clock calibration method, wireless remote controller and storage medium |
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| CN101523726A (en) * | 2006-10-12 | 2009-09-02 | 艾利森电话股份有限公司 | Efficient clock calibration in electronic equipment |
| CN102165695A (en) * | 2008-09-30 | 2011-08-24 | 拉姆伯斯公司 | Signal calibration methods and apparatuses |
| CN106569544A (en) * | 2015-10-10 | 2017-04-19 | 上海东软载波微电子有限公司 | Real time clock chip, and clock calibration method and apparatus |
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