CN113328733A - Duty ratio calibration circuit and method - Google Patents

Duty ratio calibration circuit and method Download PDF

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Publication number
CN113328733A
CN113328733A CN202110649834.5A CN202110649834A CN113328733A CN 113328733 A CN113328733 A CN 113328733A CN 202110649834 A CN202110649834 A CN 202110649834A CN 113328733 A CN113328733 A CN 113328733A
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delay
pulse width
clock signal
calibrated
level pulse
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CN113328733B (en
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海亚
刘飞
霍宗亮
叶甜春
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters

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  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The embodiment of the application provides a duty ratio calibration circuit and a method, which comprises an automatic pulse width detection module and a self-adaptive control module, wherein the automatic pulse width detection module comprises a configurable delay path, the automatic pulse width detection module can detect the high-level pulse width and the low-level pulse width of an input clock signal to be calibrated and the working environment of the circuit, so that the self-adaptive control module can automatically select and configure the corresponding delay path in a delay unit according to the detection result, the clock signal to be calibrated is input to the delay path for time delay, then a falling edge modulation module of the configurable delay path modulates the clock signal to be calibrated according to the high-level pulse width and the low-level pulse width, and finally the clock signal after duty ratio calibration is obtained. The self-adaptive configurable delay unit provided by the embodiment of the application can reduce the occupied area of the circuit, optimize the performance of the circuit and reduce the cost under the condition of meeting the requirements of duty ratio calibration accuracy of pulse width signals with different frequencies and different working environments of the circuit.

Description

Duty ratio calibration circuit and method
Technical Field
The invention relates to the technical field of signal processing, in particular to a duty ratio calibration circuit and a duty ratio calibration method.
Background
As integrated circuit manufacturing processes advance, the upper frequency limit of integrated circuit operation increases, which requires a wider frequency range of circuitry operation. In a circuit system with a wide frequency range, in order to ensure the accuracy of signal transmission, the duty ratio of a clock signal at the time of sampling needs to be 50%. However, since the circuit system is easily affected by Process, Voltage, and Temperature (PVT), the duty ratio of the clock signal may be jittered during signal transmission, which causes the duty ratio of the clock signal to be greatly deviated from 50% during sampling, thereby causing signal transmission errors.
Currently, a Duty Cycle Correction (DCC) circuit is used to offset the offset of the clock signal due to PVT and other influences during transmission, so that the clock signal has a Duty cycle of 50% during sampling.
One of the duty ratio calibration circuits commonly used at present is a duty ratio calibration circuit with a digital open loop structure, which mainly includes a delay line (delay line), a Falling Edge Modulation (FEM) module and a Phase Interpolator (PI) module. The delay line is composed of a plurality of delay units (delay units) connected in series for delaying the phase of the input signal by a unit time. The falling edge modulation module is used for modulating the falling edge of the input signal. And the phase interpolation module processes the input signal subjected to the falling edge modulation to obtain a signal subjected to duty ratio calibration.
However, since the calibration accuracy of the duty ratio is related to the delay time of each delay unit, the high accuracy of the calibration requires the delay time of the delay unit to be short for high frequency signals; for low-frequency signals, if the delay time of the delay unit is short, a large number of delay units are required to achieve high accuracy of duty calibration, and the duty calibration circuit occupies a large area, which increases the cost.
Disclosure of Invention
In view of this, an object of the present invention is to provide a duty calibration circuit, which can adaptively adjust a delay path, and reduce an occupied area of the circuit and reduce cost under the condition of meeting the accuracy of duty calibration of signals with different frequencies.
In order to achieve the purpose, the technical scheme is as follows:
a duty cycle calibration circuit comprising: the system comprises a first delay line of a configurable delay path, an automatic pulse width detection module, an adaptive control module, a falling edge modulation module of the configurable delay path and a phase interpolation module;
the first delay line of the configurable delay path is connected with a plurality of delay units in series, each delay unit comprises one or more delay paths, each delay path comprises one or more sub-delay units which are connected in series and have the same or different delay times, the total delay time of the former delay path is less than that of the latter delay path, the delay paths of the delay units connected in series in the first delay line of the configurable delay path have configurable characteristics, the delay time range of the delay paths is determined according to the pulse width information of a signal to be calibrated and the working environment of a circuit, and the first delay line of the configurable delay path is used for carrying out time delay on the clock signal to be calibrated;
the automatic pulse width detection module is used for simultaneously detecting pulse width information of high pulse width and low pulse width of the clock signal to be calibrated and generating information reflecting whether the length of a delay path of a delay unit in a first delay line of a configurable delay path is enough or not according to the pulse width information and the working environment of a circuit;
the self-adaptive control module is used for automatically adjusting the delay path of the delay unit in the first delay line of the configurable delay path to the current condition and the proper length according to the high pulse width and the low pulse width of the clock signal to be calibrated and the working environment of the circuit according to the information generated by the automatic pulse width detection module and reflecting whether the delay path of the delay unit in the first delay line of the configurable delay path is enough;
the falling edge modulation module of the configurable delay path is used for generating a control signal for performing falling edge modulation on the clock signal to be calibrated according to the pulse width information and performing falling edge modulation on the clock signal to be calibrated according to the control signal;
and the phase interpolation module is used for obtaining a clock signal with a calibrated duty ratio according to the clock signal to be calibrated after the falling edge modulation is carried out.
Optionally, the adaptive control module automatically configures a delay time length of a first delay line of the configurable delay path according to the pulse width detection result;
the automatic pulse width detection module is specifically configured to determine whether the time delay length of the first delay path is sufficient to detect the high-level pulse width information and determine whether the time delay length of the first delay path is sufficient to detect the low-level pulse width information, and if both the time delay lengths are sufficient to detect the low-level pulse width information, the adaptive control module determines that the first delay path performs time delay on the clock signal to be calibrated;
if any one of the two delay paths is not enough to be detected, the adaptive control module determines the next adjacent delay path, the automatic pulse width detection module continuously judges whether the time delay length of the next adjacent delay path is enough to detect the high-level pulse width information and judges whether the time delay length of the next adjacent delay path is enough to detect the low-level pulse width information, and if both the time delay lengths are enough to detect the low-level pulse width information, the adaptive control module determines that the next adjacent delay path carries out time delay on the clock signal to be calibrated;
if any one of the delay paths is not enough to be detected, the self-adaptive control module continues to determine the next adjacent delay path, and the automatic pulse width detection module repeats the step of continuing judgment.
Optionally, the automatic pulse width detection module includes a first D flip-flop, a second D flip-flop, a high-level pulse width information processing module, and a low-level pulse width information processing module; the high-level pulse width information processing module comprises a plurality of high-level pulse width information processing circuits, and the low-level pulse width information processing module comprises a plurality of low-level pulse width information processing circuits;
the D end of the first D trigger is connected with the clock signal to be calibrated, the clock input end of the first D trigger is connected with the delay signal output by the corresponding delay unit, and the Q end of the first D trigger is connected with the first input end of the high-level pulse width information processing circuit;
the D end of the second D trigger is connected with the clock signal to be calibrated, the clock input end of the second D trigger is connected with the delay signal output by the corresponding delay unit, and the Q end of the second D trigger is connected with the first input end of the low-level pulse width information processing circuit;
the first output end of the high-level pulse width information processing circuit is connected with the first input end of the high-level pulse width information processing circuit in the next high-level pulse width information processing module; the first output end of the low-level pulse width information processing circuit is connected with the first input end of the low-level pulse width information processing circuit in the next low-level pulse width information processing module;
the rising edge of the clock signal to be calibrated triggers the first D trigger to acquire the high-level pulse width information, and the high-level pulse width information processing circuit is used for processing the high-level pulse width information; and the falling edge of the clock signal to be calibrated triggers the second D trigger to acquire the low-level pulse width information, and the low-level pulse width information processing circuit is used for processing the low-level pulse width information.
Optionally, the high-level pulse width information includes a high-level end position, and the low-level pulse width information includes a low-level end position; the adaptive control module comprises a counter;
the automatic pulse width detection module judges whether the time delay length of the first delay path is enough to detect the high-level pulse width information according to the high-level end position, and judges whether the time delay length of the first delay path is enough to detect the low-level pulse width information according to the low-level end position to obtain delay path selection information;
the self-adaptive control module judges whether the numerical value of the counter is increased by one according to the delay path configuration information, if the delay path configuration information is enough to be detected, the numerical value of the counter is unchanged, and the self-adaptive control module determines that the first delay path carries out time delay on the clock signal to be calibrated; if any one of the delay path selection information is not enough to be detected, the value of the counter is increased by one, the automatic pulse width detection module continues to judge whether the time delay length of the next adjacent delay path is enough to detect the high-level pulse width information according to the high-level end position, judges whether the time delay length of the next delay path is enough to detect the low-level pulse width information according to the low-level end position to obtain the delay path selection information, and the adaptive control module continues to judge whether the value of the counter is increased by one according to the delay path selection information.
Optionally, the falling edge modulation module of the configurable delay path comprises a control logic circuit;
the control logic circuit is specifically configured to compare the high-level pulse width information with the low-level pulse width information, obtain a comparison result and a difference value of the high-level pulse width information and the low-level pulse width information, and generate a control signal for performing falling edge modulation on the clock signal to be calibrated according to the comparison result and the difference value;
and the falling edge modulation module of the configurable delay path performs falling edge modulation on the clock signal to be calibrated according to the control signal.
Optionally, the falling edge modulation module of the configurable delay path includes the second delay line, the second delay line is connected in series with a plurality of delay units, each delay unit includes one or more delay paths, the total delay time of the former delay path is less than the total delay time of the latter delay path, the number of delay paths of the second delay line is the same as the number of delay paths of the first delay line of the configurable delay path, the delay time of the ith delay unit of the second delay line is half of the delay time of the ith delay unit of the first delay line of the configurable delay path, and i is a positive integer greater than or equal to 1.
Optionally, the number of the delay paths is 3, and the number of the delay units is 16.
Optionally, the method further comprises: a clock signal generating circuit;
the clock signal generating circuit generates a first clock signal to be calibrated and a second clock signal to be calibrated, wherein the first clock signal to be calibrated and the second clock signal to be calibrated are differential clock signals.
The falling edge modulation module of the configurable delay path performs falling edge modulation on the first clock signal to be calibrated and the second clock signal to be calibrated;
and the phase interpolation module is used for processing the first clock signal to be calibrated and the second clock signal to be calibrated after the falling edge modulation is carried out, so as to obtain the clock signal with the calibrated duty ratio.
Optionally, the phase interpolation module comprises an inverter;
and the phase inverter processes the first clock signal to be calibrated and the second clock signal to be calibrated after the falling edge modulation is carried out, so as to obtain a clock signal with a calibrated duty ratio.
The embodiment of the application provides a duty ratio calibration method, which is used for carrying out duty ratio calibration on a clock signal to be calibrated by utilizing the duty ratio calibration circuit of the embodiment.
The embodiment of the application provides a duty ratio calibration circuit, includes: the system comprises a first delay line of a configurable delay path, an automatic pulse width detection module, an adaptive control module, a falling edge modulation module of the configurable delay path and a phase interpolation module; the first delay line of the configurable delay path is connected with a plurality of delay units in series, each delay unit comprises one or more delay paths, each delay path comprises one or more sub-delay units which are connected in series and have the same or different delay times, the total delay time of the former delay path is less than that of the latter delay path, the delay time range of the first delay line of the configurable delay path is automatically determined by an adaptive control module according to the pulse width information of a signal to be calibrated and the working environment of a circuit, and the first delay line of the configurable delay path is used for carrying out time delay on the clock signal to be calibrated; the automatic pulse width detection module is used for detecting the pulse width information of the clock signal to be calibrated and generating information reflecting whether the length of the delay path of the delay unit in the first delay line of the configurable delay path is enough or not according to the pulse width information and the working environment of the circuit; the self-adaptive control module is used for automatically adjusting the delay path of the delay unit in the first delay line of the configurable delay path to the current condition and the proper length according to the high pulse width and the low pulse width of the clock signal to be calibrated and the working environment of the circuit according to the information generated by the automatic pulse width detection module and reflecting whether the delay path of the delay unit in the first delay line of the configurable delay path is enough; the falling edge modulation module of the configurable delay path is used for generating a control signal for performing falling edge modulation on the clock signal to be calibrated according to the pulse width information and performing falling edge modulation on the clock signal to be calibrated according to the control signal; and the phase interpolation module is used for obtaining a clock signal with a calibrated duty ratio according to the clock signal to be calibrated after the falling edge modulation is carried out.
Therefore, the duty ratio calibration circuit provided in the embodiment of the present application includes an automatic pulse width detection module and a self-adaptive adjustment module, where the automatic pulse width detection module may detect a high-level pulse width and a low-level pulse width of an input clock signal to be calibrated, so that the self-adaptive control module automatically configures a corresponding delay path in a delay unit of a configurable delay path according to a result obtained by the detection, inputs the clock signal to be calibrated to the delay path for time delay, and then modulates the clock signal to be calibrated according to the high-level pulse width and the low-level pulse width by a falling edge modulation module of the configurable delay path, thereby finally obtaining the clock signal after duty ratio calibration. The multiple delay paths in the delay unit provided by the embodiment of the application can reduce the occupied area of the circuit, optimize the circuit performance and reduce the cost under the condition of meeting the duty ratio calibration precision under different working environments of different frequency signals and different circuits.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1(a) is a schematic diagram of a prior art duty cycle calibration circuit;
FIG. 1(b) is a timing diagram of a duty cycle calibration circuit in the prior art;
FIG. 1(c) is a schematic diagram of a prior art delay line;
fig. 2 is a schematic diagram of a duty ratio calibration circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a delay line of a configurable delay path according to an embodiment of the present application;
FIG. 4(a) is a schematic diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
FIG. 4(b) is a waveform diagram illustrating the operation principle of the clock signal generating circuit according to the embodiment of the present application;
fig. 5(a) is a circuit diagram of an automatic pulse width detection module provided in an embodiment of the present application;
fig. 5(b) is a waveform diagram illustrating an operation principle of an automatic pulse width detection module according to an embodiment of the present application;
fig. 6(a) is a circuit diagram and a truth table of a high-level pulse width information processing circuit UCR provided in an embodiment of the present application;
fig. 6(b) is a circuit diagram and a truth table of the low level pulse width information processing circuit DKN according to the embodiment of the present application;
fig. 6(c) is a circuit diagram of a Flag signal generating circuit provided in the embodiment of the present application;
fig. 7(a) is a circuit diagram of an adaptive control module according to an embodiment of the present application;
fig. 7(b) is a waveform diagram illustrating an operation principle of an adaptive control module according to an embodiment of the present application;
fig. 8(a) is a circuit diagram of a falling edge modulation module of a configurable delay path provided in an embodiment of the present application;
fig. 8(b) is a waveform diagram illustrating an operation principle of a falling edge modulation module of a configurable delay path according to an embodiment of the present application;
fig. 9 is a schematic diagram of a control logic circuit and a falling edge modulation module of a configurable delay path according to an embodiment of the present application;
fig. 10 is a circuit diagram of a phase interpolation module according to an embodiment of the present application;
fig. 11 is a waveform diagram of an operating principle of performing duty ratio calibration of a clock signal by using the duty ratio calibration circuit according to the embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Now, as mentioned in the background, referring to fig. 1(a), a schematic diagram of a duty cycle calibration circuit in the prior art is shown. In the prior art, a duty ratio calibration circuit mainly includes: a Phase Split (PS) module, a delay line (delay line), a Control Logic (Control Logic) module, a Falling Edge Modulation (FEM) module, and a Phase Interpolator (PI) module.
The basic working principle is as follows: the reset signal Rst is set high, the circuit enters the initial state and then is resetThe signal Rst is low, the circuit enters a normal operation state, the phase splitting module generates a differential clock signal according to the input clock signal Clk _ in, that is, generates two in-phase clock signals Clk _ p and Clk _ n with complementary duty ratios, as shown in fig. 1(b), which is a timing diagram of a prior art duty ratio calibration circuit, the differential clock signals Clk _ p, Clk _ n and Clk _ in have the same clock period TClk_inAnd the duty cycle is close to 50%, THIndicating a high level pulse width of clk _ p or a low level pulse width of clk _ n. Normally, the falling edge of the reset signal Rst needs to keep a certain phase relationship with Clk _ in, otherwise the circuit will not work normally. The clk _ p enters a delay line for time delay to obtain a set of clock signals clk [ i ] with different phases]Clock signal clk i]Input to the control logic module, which outputs a selection signal sel [ i ]]、on[i]And control signals control, sel [ i ]]And on [ i ]]The signal selects a signal Clk _ pb complementary to the duty ratio of Clk _ p in phase in the delay line, the control signal is used for controlling the FEM, two FEM modules respectively adjust the falling edges of Clk _ pb and Clk _ p according to the control signal, the adjusted signals output in-phase clock signals Clk _ pbf and Clk _ pf with complementary duty ratios and the duty ratios are close to 50%, the PI integrates the two signals and outputs a clock signal Clk _ out with the duty ratio of 50%, and referring to fig. 1(b), the output clock signal Clk _ out and the high-level pulse width of the input clock signal Clk _ in have the following relation:
TH,Clk_out＝0.5(TClk_in-TH)+0.5TH＝0.5TClk_in
i.e., high level pulse width T of the output clock signal Clk _ outH,Clk_outIs TClk_inHalf the high pulse width, representing a 50% duty cycle.
Referring to fig. 1(c), which is a schematic diagram of a delay line in the prior art, for a delay line with the same number of delay units, the total delay time of the delay line determines the frequency range of the input signal, and the delay time of each delay unit determines the duty ratio calibration accuracy. Therefore, the delay time of the delay unit in the delay line has different influences on the output duty ratio error under different frequencies: for high frequency signals, high precision of calibration requires short delay time of the delay unit; for low-frequency signals, high calibration accuracy requires a long delay time of the delay unit, that is, if a delay is set according to the low-frequency signals, an output error at high frequency is too large; if the delay is set at a high frequency, the total delay of the delay chain is small, which limits the low frequency range of circuit operation. When high accuracy and a wide frequency range of an input signal are compatible, it is necessary to employ delay units of short delay time and increase the number of delay units. Considering low frequency input signals results in excessive number of delay units and corresponding complex control circuits, which leads to a sharp increase in circuit area and power consumption cost.
Based on the above technical problem, an embodiment of the present application provides a duty ratio calibration circuit, including: the system comprises a first delay line of a configurable delay path, an automatic pulse width detection module, an adaptive control module, a falling edge modulation module of the configurable delay path and a phase interpolation module; the first delay line of the configurable delay path is connected with a plurality of delay units in series, each delay unit comprises one or more delay paths, each delay path comprises one or more sub-delay units which are connected in series and have the same or different delay times, the total delay time of the former delay path is less than that of the latter delay path, the delay paths of the delay units connected in series in the first delay line of the configurable delay path have configurable characteristics, the delay time range of the delay paths is determined according to the pulse width information of a signal to be calibrated and the working environment of a circuit, and the first delay line of the configurable delay path is used for carrying out time delay on the clock signal to be calibrated; the automatic pulse width detection module is used for detecting the pulse width information of the clock signal to be calibrated and generating information reflecting whether the length of the delay path of the delay unit in the first delay line of the configurable delay path is enough or not according to the pulse width information and the working environment of the circuit; the self-adaptive control module is used for automatically adjusting the delay path of the delay unit in the first delay line of the configurable delay path to the current condition and the proper length according to the high pulse width and the low pulse width of the clock signal to be calibrated and the working environment of the circuit according to the information generated by the automatic pulse width detection module and reflecting whether the delay path of the delay unit in the first delay line of the configurable delay path is enough; the falling edge modulation module of the configurable delay path is used for generating a control signal for performing falling edge modulation on the clock signal to be calibrated according to the pulse width information and performing falling edge modulation on the clock signal to be calibrated according to the control signal; and the phase interpolation module is used for obtaining a clock signal with a calibrated duty ratio according to the clock signal to be calibrated after the falling edge modulation is carried out.
Therefore, the duty ratio calibration circuit provided in the embodiment of the present application includes an automatic pulse width detection module and an adaptive control module, where the automatic pulse width detection module may detect a high-level pulse width and a low-level pulse width of an input clock signal to be calibrated, so that the adaptive control module automatically configures a corresponding delay path in a delay unit according to a result obtained by the detection, inputs the clock signal to be calibrated to the delay path for time delay, and then modulates the clock signal to be calibrated according to the high-level pulse width and the low-level pulse width by using a falling edge modulation module of the configurable delay path, thereby finally obtaining the clock signal after duty ratio calibration. The multiple delay paths in the delay unit provided by the embodiment of the application can reduce the occupied area of the circuit, optimize the circuit performance and reduce the cost under the condition of meeting the duty ratio calibration precision under different working environments of different frequency signals and different circuits.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a schematic diagram of a duty calibration circuit provided in an embodiment of the present application is shown, where the duty calibration circuit 100 includes: a Pulse Width Detector (PWD) module 110, a delay line (delay line)111 capable of configuring a delay path, a Falling Edge Modulation (FEM) module 120, and a Phase Interpolator (PI) module 130, and may further include a clock signal generation Circuit (Start Circuit, SC) 140. The automatic pulse width detection module 110 includes a first delay line 111 of a configurable delay path and an Adaptive Control (AC) module 112, and the falling edge modulation module 120 of the configurable delay path includes a Control Logic (Control Logic) circuit 121 and a second delay line 122.
Referring to fig. 3, a schematic diagram of a delay line according to an embodiment of the present application is shown. In the embodiment of the present application, each delay unit may include one or more delay paths, fig. 3 shows 3 delay paths a0, a1, and a2, the buffer is a sub-delay unit, the delay time of the sub-delay unit may be determined according to actual situations, and the delay time of the sub-delay unit may be the same or different. The total delay time of the previous delay path is less than the total delay time of the next delay path, for example, delay path a1 has 2 sub-delay units compared to delay path a0, so the total delay time of delay path a1 is greater than the total delay time of delay path a0, and similarly the total delay time of delay path a2 is greater than the total delay time of delay path a 1. A0 may be referred to as a Short delay path (Short delay line), a1 may be referred to as a Medium delay path (Medium delay line), and A3 may be referred to as a Long delay path (Long delay line). The 3 delay paths a0, a1, and a2 may be identified using two-bit 2-ary digits, e.g., S <1:0> -00, denoted as short delay path a 0; s <1:0> -01, denoted as medium delay path a 1; s <1:0> -10, denoted long delay path a 2. The number of delay paths is not limited in the embodiments of the present application, and therefore, the number of bits of binary digits is not limited, for example, each delay unit of the present application includes 8 delay paths, and at this time, a two-bit 2-ary digit cannot completely satisfy 8 delay paths, so that a three-bit 2-ary digit can be used to identify 8 delay paths. As shown in fig. 3, when delay cells including three different delay paths are connected in series, a first delay line of the configurable delay paths that can constitute three different delay times includes a first short delay line in which the delay cell employs the short delay path a0, a first middle delay line in which the delay cell employs the middle delay path a1, and a first long delay line in which the delay cell employs the long delay path a 2. That is, the more delay paths included in the delay unit, the more the delay line makes the selection of the time delay.
In an embodiment of the present application, the clock signal may be output from out by selecting one of the 3 delay paths from the delay cells in the incoming delay line 111. As the delay line extends, the number of delay cells on the delay line increases, and the delay time gradually increases. Each delay unit comprises a plurality of delay paths with different delay times, for high-frequency signals, the delay units in front can be used for selecting the shorter delay path in the delay units to delay the time of the clock signal, and the delay time is shorter at the moment, so that the accuracy of duty ratio calibration of the high-frequency signals can be ensured; for low-frequency signals, the method can be extended to a later delay unit, and a longer delay path in the delay unit is selected for time delay of the clock signal, so that the delay time is longer, the accuracy of duty ratio calibration of the low-frequency signals can be ensured, the number of the delay units is reduced, the occupied area of a duty ratio calibration circuit is reduced, and the cost is reduced.
The following briefly describes a main process of calibrating the duty ratio calibration circuit provided in the embodiment of the present application:
in the embodiment of the present application, when the reset signal Rst is ended, that is, the reset signal Rst is low, the Circuit enters a normal operation state, as shown in fig. 2, the clock signal generating Circuit (Start Circuit, SC)140 generates the first clock signal to be calibrated Clk _ p and the second clock signal to be calibrated Clk _ n according to the input clock signal Clk _ in, where the first clock signal to be calibrated Clk _ p and the second clock signal to be calibrated Clk _ n are differential clock signals. Then, the Pulse Width Detection (PWD) module 110 performs Pulse Width detection on the clock signal clk _ p to be calibrated through a first delay line of a configurable delay path having three delay units connected in series and having three different delay paths to form three configurable delay paths with different delay times, so as to obtain Pulse Width information of the clock signal clk _ p to be calibrated, and determines a delay path corresponding to the delay time according to the Pulse Width information, where S <1:0> -00 indicates that the short delay path a0 is selected, S <1:0> -01 indicates that the medium delay path a1 is selected, and S <1:0> -10 indicates that the long delay path a2 is selected. The PWD module 110 uses the Flag signal to indicate whether the time delay length of the delay line composed of the delay path is sufficient or not in the process of detecting the pulse width of the clock signal clk _ p to be calibrated, adjusts the delay path, i.e., adjusts the identification S <1:0> of the delay path according to the value of the Flag signal fed back to the Adaptive Control (AC) module 112, so that the PWD module 110 can automatically configure a proper delay path in the detection process, if the time delay length of the delay line composed of the delay path is sufficient to detect the pulse width of the clock signal clk _ p to be calibrated, the Flag signal is low, S <1:0> is not changed, if the time delay length of the delay line composed of the delay path is insufficient to detect the pulse width of clk _ p, the Flag signal is high, a counter in the Adaptive Control (AC) module 112 increments S <1:0> by one, selects a delay path with a longer delay time, then, the PWD module 110 uses a delay line composed of suitable delay paths to detect the high level pulse width information up <3:0> and the low level pulse width information down <3:0> of the clock signal to be calibrated clk _ p, and selects the in-phase clock signal clk _ pb having a complementary duty ratio with the clock signal to be calibrated clk _ n according to the pulse width information detection result, where the high level pulse width information up <3:0> and the low level pulse width information down <3:0> may be represented as four-bit 2-ary numbers, for example, up <3:0> -0111, and down <3:0> -0011. Then, the clock signal Clk _ pb to be calibrated is input to a Falling Edge Modulation (FEM) module 120, a Control Logic (Control Logic) circuit 121 included in the FEM module 120 obtains Control signals INC, TYP, DEC, Y <11:0> and YN <11:0> for falling Edge modulation of the clock signals Clk _ pb and Clk _ n to be calibrated according to high-level pulse width information up <3:0> and low-level pulse width information down <3:0>, and the FEM module 120 obtains in-Phase clock signals Clk _ pb and Clk _ n for falling Edge modulation according to the duty signal to obtain in-Phase clock signals pf and Clk _ nf with complementary duty ratios and duty ratios close to 50%, and finally obtains a clock signal Clk _ out with a duty ratio of 50% through integration of a Phase interpolation (Phase Interpolator, PI) module 130.
Therefore, after the duty ratio calibration circuit starts to work, the automatic pulse width detection module with the delay lines with different time delay lengths automatically configures a proper delay path and a required clock signal according to a pulse width detection result, and then the clock signal with the duty ratio of 50% is obtained through the falling edge modulation module and the phase interpolation module of the configurable delay path and is output, so that the open-loop duty ratio calibration circuit with a wide working frequency range is realized. And the delay unit in the automatic pulse width detection module comprises three delay paths with different time delay lengths, a simple self-adaptive control circuit is used for automatically configuring the proper delay path detection pulse width, the self-adaptive configurable mode not only can be automatically adjusted according to the pulse width length to be detected of the input clock signal, but also can be automatically adjusted by combining the current PVT condition of the circuit, a more proper delay path under the corresponding frequency pulse width and the PVT condition at the moment is selected, and the influence of PVT change on the circuit performance is reduced.
After the main process of calibrating the duty ratio calibration circuit provided in the embodiment of the present application is briefly described, a detailed description will be given below to a process of calibrating a clock signal to be calibrated by each module:
first, a clock signal generation Circuit (SC) 140 is provided. Fig. 4(a) is a schematic diagram of a clock signal generation circuit provided in an embodiment of the present application, where the clock signal generation circuit includes a D flip-flop, an or gate, a buffer, and a matched delay line MDL. Fig. 4(b) is a waveform diagram of an operating principle of the clock signal generating circuit according to the embodiment of the present application. Referring to fig. 4(a) and 4(b), when the reset signal Rst is high, the D flip-flop is in a reset state, the circuit does not operate, when the reset signal Rst is low, the circuit starts to operate, and the clock signal Clk _ in to be calibrated is input to the D flip-flop. From the operating schematic waveform diagram, it can be known that when Rst is high, Qn is high, Clk is also high after Clk passes through the or gate, after Rst is low, Qn is pulled low at the first rising edge of the clock signal to be calibrated Clk _ in, and will keep this value, after Rst passes through the or gate, Clk will follow the clock signal to be calibrated Clk _ in, and Clk generates the differential clock signals Clk _ p and Clk _ n through the buffer and the delay line MDL. Clk _ p is output through the buffer to provide drive to the circuitry of the following PWD module. In order to bring clk _ n and clk _ pb into phase, clk _ n is output through a matched delay line MDL, the delay generated by the MDL canceling the delay generated in the PWD module when clk _ pb is output.
Next is an automatic Pulse Width Detector (PWD) module 110. The Pulse Width Detector (PWD) module 110 used in the embodiment of the present application may be a multiplexing automatic Pulse Width detection module, that is, only the Pulse Width detection module that is already owned needs to be multiplexed into the duty ratio calibration circuit in the embodiment of the present application without separately resetting a Pulse Width detection module. This can further reduce the cost of the duty cycle calibration circuit in the embodiments of the present application.
Fig. 5(a) is a circuit diagram of an automatic pulse width detection module according to an embodiment of the present application, where the circuit of the automatic pulse width detection module includes a plurality of first D flip-flops 113, a plurality of second D flip-flops 114, a high-level pulse width information processing module 115, a low-level pulse width information processing module 116, a first delay line 111 with a configurable delay path, and a Flag signal generation circuit. Fig. 5(b) is a waveform diagram of an operating principle of the automatic pulse width detection module according to an embodiment of the present application.
In an embodiment of the present application, the automatic pulse width detection module 110 includes a first delay line 111 of a configurable delay path, the first delay line 111 of the configurable delay path includes a plurality of delay units, the plurality of delay units are connected in series to form the first delay line 111 of the configurable delay path, and each delay unit includes one or more delay paths. As can be seen from fig. 5(a), the first delay line 111 of the configurable delay path includes 16 delay cells, each of which includes 3 delay paths a0, a1, and a 2. The high-level pulse width information processing module 115 includes a plurality of high-level pulse width information processing circuits UCR, and the low-level pulse width information processing module 116 includes a plurality of low-level pulse width information processing circuits DKN. The number of the first D flip-flops 113, the number of the second D flip-flops 114, the number of the high-level pulse width information processing circuits UCR, and the number of the low-level pulse width information processing circuits DKN in the automatic pulse width detection module 110 are all the same, and are all the number of delay cells in the first delay line 111 of the configurable delay path.
In the automatic pulse width detection module 110, the D terminal of the first D flip-flop is connected to the clock signal clk _ p to be calibrated, and the D terminal of the first D flip-flop is connected to the clock signal clk _ p to be calibratedThe clock input end is connected with the delay signal psi output by the corresponding delay unitiAnd i represents the ith delay unit, and the Q end of the first D flip-flop is connected with the first input end of the high-level pulse width information processing circuit UCR. The D end of the second D trigger is connected with a clock signal clk _ p to be calibrated, and the clock input end of the second D trigger is connected with a delay signal psi output by the corresponding delay unitiThe Q terminal of the second D flip-flop is connected to the first input terminal of the low-level pulse width information processing circuit DKN. The first output end of the high-level pulse width information processing circuit UCR is connected with the first input end of the high-level pulse width information processing circuit UCR in the next high-level pulse width information processing module, the first output end of the low-level pulse width information processing circuit UCR is connected with the first input end of the low-level pulse width information processing circuit DKN in the next low-level pulse width information processing module, the rising edge of a clock signal clk _ p to be calibrated triggers the first D trigger to acquire clk _ p high-level pulse width information, then the high-level pulse width information processing circuit processes the high-level pulse width information, the falling edge of the clock signal clk _ p to be calibrated triggers the second D trigger to acquire clk _ p low-level pulse width information, and then the low-level pulse width information processing circuit processes the low-level pulse width information. The collected and processed high level pulse width information and low level pulse width information may then be used to determine an appropriate delay path.
Fig. 6(a) is a circuit diagram and a truth table of a high-level pulse width information processing circuit UCR according to an embodiment of the present application. Fig. 6(b) is a circuit diagram and a truth table of the low level pulse width information processing circuit DKN according to the embodiment of the present application. Fig. 6(c) is a circuit diagram of a Flag signal generating circuit according to an embodiment of the present application.
When the clock signal clk _ p to be calibrated is input to the automatic pulse width detection module 110, S is changed<1:0>To configure different delay paths, S<1:0>Defaults to the short delay path a0, i.e., S<1:0>At 00, the delay unit using the short delay path a0 outputs a set of clock signals psi with the same phase intervaliTriggering a first D flip-flop to sample clk _ p to acquire high-level pulse width information by the rising edge of a clock signal to be calibrated clk _ p, and outputting a U code U [ i ] by the first D flip-flop]Clock signal clk to be calibratedThe falling edge of p triggers a second D flip-flop to sample clk p to obtain low-level pulse width information, and the second D flip-flop outputs a D code D [ i ]]. U code U [ i ] output by first D flip-flop]And inputting the high-level pulse width information into a high-level pulse width information processing circuit UCR, and obtaining a C code and an R code after the UCR processing, wherein the C code is high-level pulse width information used by a subsequent circuit, and the R code represents the position of the end of sampling high level in the pulse width detection process. D code D [ i ] output by second D flip-flop]The pulse width information is input to a low-level pulse width information processing circuit DKN, and after DKN processing, a K code and an N code are obtained, wherein the K code is low-level pulse width information used by a subsequent circuit, and the N code represents a position where sampling low level ends in a pulse width detection process.
The automatic pulse width detection module 110 determines whether the time delay length of the first delay path a0 is sufficient to detect the high level pulse width information according to the high level end position R code, and determines whether the time delay length of the first delay path a0 is sufficient to detect the low level pulse width information according to the low level end position K code, so as to obtain the delay path selection information. Specifically, all values in the R code are or are taken together to obtain a value of flag _ up, if the value of flag _ up is 0, it indicates that the time delay length of the first delay path a0 is not enough to detect the high level pulse width of clk _ p, otherwise, it indicates that the time delay length of the first delay path a0 is enough to detect the high level pulse width of clk _ p, and all values in the N code are or are taken together to obtain a value of flag _ down, if the value of flag _ down is 0, it indicates that the time delay length of the first delay path a0 is not enough to detect the low level pulse width of clk _ p, otherwise, it indicates that the time delay length of the first delay path a0 is enough to detect the low level pulse width of clk _ p. Referring to the Flag signal generating circuit shown in fig. 6(c), Flag _ up and Flag _ down obtain a Flag signal through the nand gate, and as long as one of Flag _ up and Flag _ down is 0, the value of the Flag signal is 1, which indicates that the first delay path a0 is not enough to detect the pulse width of clk _ p, and S <1:0> needs to be adjusted to select an appropriate delay path.
In practical application, the reason why the UCR is used to process the acquired high-level pulse width information is that if the clock period of the clock signal clk _ p to be calibrated is less than the length of the time delay of the first delay line of the configurable delay path, multiple groups of continuous 1 may appear in the output U code, which may cause errors in subsequent circuit logic. The reason why DKN is adopted to process the collected low-level pulse width information is that if the clock period of the clock signal clk _ p to be calibrated is less than the length of the time delay of the first delay line of the configurable delay path, multiple groups of continuous 0 may appear in the output D code, and the D code is processed by DKN to obtain a K code and an N code.
Fig. 7(a) is a circuit diagram of an adaptive control module according to an embodiment of the present application, where the circuit of the adaptive control module includes a D flip-flop, a buffer, a nand gate, and a counter (2bit counter). Fig. 7(b) is a waveform diagram of an operating principle of an adaptive control module according to an embodiment of the present application.
In the embodiments of the present application, the delay path configuration information includes the following two types: the first is that a value of 1 for the Flag signal indicates that the length of the first delay line time delay of the configurable delay path is not sufficient to detect the pulse width of clk _ p, and the second is that a value of 0 for the Flag signal indicates that the length of the first delay line time delay of the configurable delay path is sufficient to detect the pulse width of clk _ p. Therefore, when the value of the Flag signal is 0, the adaptive control module determines that the current delay path is the delay path for calibrating the clock signal to be calibrated clk _ p, the value of the counter is unchanged, and the value of S <1:0> is unchanged; when the value of the Flag signal is 1, the adaptive control module determines that the current delay path is insufficient to calibrate the clock signal clk _ p to be calibrated, the value of the counter is increased by one, the value of S <1:0> is also increased by one, the adaptive control module determines the next delay path of the current delay path, the first D flip-flop and the second D flip-flop of the automatic pulse width detection module continue to acquire high-level pulse width information and low-level pulse width information, the value of the Flag signal is obtained after the high-level pulse width information and the low-level pulse width information are processed, and whether the time delay length of the next delay path can detect the pulse width of the clk _ p is judged according to the value of the Flag signal. Specifically, referring to fig. 7(b), using the divided-by clock signal clk _ div2 of clk _ p as the operation cycle of the delay selection, the value of the Flag signal is sampled at the rising edge of clk _ div2, if the value of Flag is 1, Qf is pulled high, and clk _ div2 passes through an and gate, then a rising edge occurs at clks, at which a counter (2-bit counter) is triggered to change the value of S <1:0 >. S <1:0> is defaulted to 00, a short delay path A0 is selected, if the short delay path A0 does not detect the pulse width enough, a Flag signal is 1, clks has a rising edge, a counter is added with 1 to change S <1:0> to 01, a middle delay path A1 is selected, if the middle delay path A1 detects the pulse width enough at the moment, the Flag signal is pulled low, if the middle delay path A1 detects the pulse width not enough, the Flag signal is 1, clks has a rising edge, the counter is added with 1 to change S <1:0> to 10, a long delay path A1 is selected, and if the long delay path A2 detects the pulse width enough at the moment, the Flag signal is pulled low. If the Flag value is 0, Qf is low, clks is kept low, and clk _ div2 is coupled to the nand gate through the buffer in order to cancel the propagation delay of the Flag signal to Qf.
In the embodiment of the present application, only 3 delay paths are listed, and therefore the counter performs incrementing twice at most, but in practical applications, the number of delay paths may not be limited, and therefore the counter may perform incrementing twice to change the delay path.
In the embodiment of the application, the adaptive control module automatically configures a proper delay path according to the result of pulse width detection of the delay path in the automatic pulse width detection module, and the adaptive delay path configuration mode can automatically adapt to PVT (voltage-to-volume ratio) change of a circuit and improve the robustness of the circuit. And a new module is not required to be added in the circuit, and when the self-adaptive configuration of the delay path is realized, the self-adaptive configuration can be realized only by simply and logically combining the information related to the pulse width of the clock signal to be calibrated, which is output by the automatic pulse width detection module and input by the automatic pulse width detection module. In addition, compared with the method of only detecting the falling edge of the clock signal to be calibrated, the pulse width detector is used for detecting the high-level pulse width information and the low-level pulse width information of the input clock signal to be calibrated, and the difference value of the high-level pulse width and the low-level pulse width is obtained; and then the duty ratio of the signal is adjusted to 50% by using the pulse width difference, so that the range of the input duty ratio adjusted by the circuit can be increased, and the duty ratio calibration effect is enhanced.
Referring to fig. 5(b), which is a waveform diagram of the operating principle of the automatic pulse width detection module 110, it can be seen that the rising edge of the clock signal to be calibrated clk _ p triggers the first D flip-flop to sample clk _ p to obtain the U code, U [0 ]]-U[6]Is 1, U [7 ]]The high-level pulse width of the clk _ p is 0, the high-level pulse width of the clk _ p comprises 7 tau, the tau is the delay time of each delay unit, in order to avoid the influence of a plurality of groups of continuous 1 in the U code on the circuit logic, the U code is processed into a C code and an R code by using the UCR, and the number of the 1 in the C code represents the high-level pulse width information up of the clk _ p<3:0>. A1 in the R code indicates the position of the first D flip-flop at which the high-level pulse width sampling of clk _ p ends, and the output of the delay unit is selected as clk _ pb, R7]1, selecting psi7Clk _ pb. The second D flip-flop triggered by the falling edge of the clock signal to be calibrated clk _ p samples clk _ p to obtain the D code D [0 ]]-D[2]Is 0, D3]1, the low-level pulse width of clk _ p is shown to contain 3 τ, in order to avoid that a plurality of groups of continuous 0 in the D code have influence on the circuit, DKN is used for processing the D code into K code and N code, and the number of 1 in the K code represents the low-level pulse width information down of clk _ p<3:0>And 1 in the N code represents the position where the second D flip-flop ends sampling the low level pulse width of clk _ p.
Again a Falling Edge Modulation (FEM) module 120 of the configurable delay path. Fig. 8(a) is a circuit diagram of a falling edge modulation module of a configurable delay path provided in an embodiment of the present application, and fig. 8(b) is a waveform diagram of an operation principle of the falling edge modulation module of the configurable delay path provided in the embodiment of the present application. The falling edge modulation module 120 of the configurable delay path includes a Control Logic (Control Logic) circuit 121 and a second delay line 122. The second delay line 122 is connected in series with a plurality of delay units, each delay unit includes one or more delay paths, the total delay time of the former delay path is less than that of the latter delay path, the number of the delay paths of the second delay line 122 is the same as that of the delay paths of the first delay line 111 of the configurable delay path, the delay time of the ith delay unit of the second delay line 122 is one half of that of the ith delay unit of the first delay line 111 of the configurable delay path, and i is a positive integer greater than or equal to 1. That is, the delay unit FEM _ delay unit in the FEM module has the same structure as the delay unit in the PWD module, and the delay time of FEM _ delay unit is about half of the delay time of the delay unit in the PWD for the determined delay path S <1:0 >.
The falling edge modulation module 120 of the configurable delay path is configured to generate a control signal for performing falling edge modulation on the clock signal to be calibrated according to the high-level pulse width information and the low-level pulse width information, and perform falling edge modulation on the clock signal to be calibrated according to the control signal.
In an embodiment of the present application, the falling edge modulation module 120 of the configurable delay path includes a Control Logic (Control Logic) circuit 121. Fig. 9 is a schematic diagram of a Control Logic (Control Logic) circuit 121 and a falling edge modulation module 120 of a configurable delay path according to an embodiment of the present disclosure.
In the embodiment of the application, the control logic circuit is specifically configured to compare high-level pulse width information and low-level pulse width information, obtain a comparison result of the high-level pulse width information and the low-level pulse width information and a difference value E <3:0>, generate control signals INC, TYP, DEC, Y <11:0> and YN <11:0> for performing falling edge modulation on a clock signal to be calibrated according to the comparison result and the difference value, and then perform falling edge modulation on the clock signal to be calibrated according to the control signals by a falling edge modulation module of the configurable delay path.
Specifically, Comp & Sub in the control logic circuit 121 represents comparison and subtraction, and compares the magnitudes of the high-level pulse width information up <3:0> and the low-level pulse width information down <3:0>, if the two are the same, TYP is 1, and the rest is 0; if up <3:0> is greater than down <3:0>, INC is 1, and the rest is 0; if up <3:0> is less than down <3:0>, DEC is 1, and the rest is 0. Finally, calculating the difference value of the two, if TYP is 1, E <3:0> is 0000; if INC is 1, E <3:0> is the result of up <3:0> minus down <3:0 >; if DEC is 1, E <3:0> is the result of down <3:0> minus up <3:0 >. A decoder (Decode) in the control logic circuit 121 decodes E <3:0> into Y <11:0> of 12 bytes (bits), and YN <11:0> is obtained after inverting each bit of Y <11:0 >.
Referring to fig. 8(b), the output of the middle delay cell of the second delay line is nclk, and the output of the middle delay cell of the second delay line is TYP0 with no change in pulse width through the buffer, the outputs fclkn and nclk of the left delay cell of the second delay line are and gate, and are aligned with the rising edge of nclk, DECn with narrowed pulse width of 0.5n τ, and the outputs bclkn and nclk of the right delay cell of the second delay line are or gate, and are aligned with the rising edge of nclk, and INCn with widened pulse width of 0.5n τ. The switch circuit is a transmission gate formed by complementary NMOS and PMOS transistors, when the gate control voltage Y < i > of the NMOS is 1 and the gate control voltage YN < i > of the PMOS is 0, the switch is turned on, a signal on the transmission gate is transmitted to the lower side, otherwise, the switch is turned off, and the transmission gate outputs a high-resistance state. In order to avoid that the circuit performance is influenced by the excessive load of the switch circuits caused by the connection of a large number of switch circuits, the switch circuits for selecting TYP0 and INCn are connected together, the switch circuits for selecting DECn are connected together, and the s signal is used for controlling the two-way multiplexer to select the required clock signal output. For example, referring to fig. 8(a), taking the FEM module for adjusting the clock signal to be calibrated clk _ pb as an example, clk _ pf selects in1 with a narrowed pulse width if s is 1, and clk _ pf selects in0 with a constant or widened pulse width if s is 0.
Referring to fig. 8(a), Y <11:0> and YN <11:0> are used to control the opening and closing of the switching circuit formed by the transfer gates in the FEM module. INC and TYP control the s signal in the FEM module that adjusts clk _ pb, if TYP is 1, Y <0> in Y <11:0> is 1, the transmitted to in0 is nclk with unadjusted pulse width, s is 0, clk _ pf selects in0, if INC is 1, s is 1, clk _ pf selects DECn with narrowed pulse width, if INC and TYP are both 0, s is 0, clk _ pf selects in0 with widened pulse width, similarly DEC and TYP control the s signal in the FEM module that adjusts clk _ n, after adjustment, the duty cycle of clk _ pf and _ nf is close to 50%.
Finally, a Phase Interpolator (PI) block 130. Fig. 10 is a circuit diagram of a phase interpolation module according to an embodiment of the present application, where the phase interpolation module includes an inverter. In the embodiment of the application, the phase interpolator is composed of three inverters, and the inverters process the first clock signal to be calibrated Clk _ pf and the second clock signal to be calibrated Clk _ nf to obtain the clock signal Clk _ out with the calibrated duty ratio.
The above detailed description is provided for the process of calibrating the clock signal to be calibrated specifically by each module in the duty ratio calibration circuit provided in the embodiment of the present application.
Fig. 11 is a waveform diagram illustrating an operation principle of performing duty ratio calibration of a clock signal by using the duty ratio calibration circuit according to the embodiment of the present application. As can be seen, the reset signal Rst is high, the circuit enters the initial state, the Flag signal is initially 1, S <1:0> is initially 00, the short delay path A0 is used, the high level pulse width information up <3:0> is initially 0000, and the low level pulse width information down <3:0> is initially 1111. After the reset signal Rst is pulled down, the circuit starts to work, the clock signal generating circuit outputs differential clock signals clk _ p and clk _ n, after rising edges of clk _ p occur, the PWD module starts to detect the pulse width of clk _ p, the time delay length of the short delay path A0 is not enough to detect the pulse width of clk _ p, the Flag signal is 1, S <1:0> is changed from 00 to 01, the middle delay path A1 is selected, the Flag signal is 0, the PWD module selects a clock signal clk _ pb which is complementary to the same-phase duty ratio of clk _ n, detects high-level pulse width information up <3:0> 0111and low-level pulse width information down <3:0> -0011, the control logic circuit compares up <3:0> and down <3:0>, INC ═ 1, TYPP and DEC are both 0, the difference between up <3:0> and down <3:0> is calculated to be 01011: YN <11: 11, YN > 3683, the control signals INC, TYP, DEC, Y <11:0> and YN <11:0> control the FEM modules, the falling edges of Clk _ pb and Clk _ n are adjusted, clock signals Clk _ pf and Clk _ nf which have complementary duty ratios in phase and the duty ratios are close to 50% are obtained, and finally the clock signals Clk _ out with the duty ratios of 50% are obtained through integration of PI modules.
The duty ratio calibration circuit provided in the embodiment of the application comprises an automatic pulse width detection module and an adaptive control module, wherein the automatic pulse width detection module can detect a high-level pulse width and a low-level pulse width of an input clock signal to be calibrated, so that the adaptive control module automatically configures a corresponding delay path in a delay unit according to a result obtained by detection, the clock signal to be calibrated is input to the delay path for time delay, a falling edge modulation module of the configurable delay path modulates the clock signal to be calibrated according to the high-level pulse width and the low-level pulse width, and finally the clock signal after duty ratio calibration is obtained. The delay path with the configurable characteristics in the delay unit provided by the embodiment of the application can enable the circuit to operate in a wide frequency range, for example, the circuit operates in a frequency range of 3.33GHz-360 MHz. The embodiment of the application can meet the duty ratio calibration accuracy of signals with different frequencies, for example, the error of the duty ratio is controlled within + -2% in a high-frequency range from 2GHz to 360 MHz; the circuit is in a low-frequency range of 3.33GHz to 2GHz, and the duty ratio error is controlled within + -3.1%. In addition, the duty ratio calibration circuit provided by the embodiment of the application has the advantages that the logic of the control circuit is simple, the occupied resources of the whole circuit are less, the occupied area of the circuit is reduced, and the cost is reduced.
Based on the duty ratio calibration circuit provided by the above embodiment, the embodiment of the present application further provides a duty ratio calibration method, and the duty ratio calibration circuit provided by the above embodiment is used to perform duty ratio calibration on a clock signal to be calibrated.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.

Claims (10)

1. A duty cycle calibration circuit, comprising: the system comprises a first delay line of a configurable delay path, an automatic pulse width detection module, an adaptive control module, a falling edge modulation module of the configurable delay path and a phase interpolation module;
the first delay line of the configurable delay path is connected with a plurality of delay units in series, each delay unit comprises one or more delay paths, each delay path comprises one or more sub-delay units which are connected in series and have the same or different delay times, the total delay time of the former delay path is less than that of the latter delay path, the delay paths of the delay units connected in series in the first delay line of the configurable delay path have configurable characteristics, the delay time range of the delay paths is determined according to the pulse width information of a signal to be calibrated and the working environment of a circuit, and the first delay line is used for carrying out time delay on the clock signal to be calibrated;
the automatic pulse width detection module is used for simultaneously detecting the pulse width information of the high-level pulse width and the low-level pulse width of the clock signal to be calibrated and automatically generating information for reflecting whether the delay path length of a delay unit in a first delay line of a configurable delay path is enough or not according to the pulse width information and the working environment of a circuit;
the self-adaptive control module is used for automatically adjusting the delay paths of the delay units in the first delay line of the configurable delay paths to the current condition and proper length according to the widths of the high-level pulse width and the low-level pulse width of the clock signal to be calibrated and the working environment of the circuit according to the information generated by the pulse width detection module and reflecting whether the delay paths of the delay units in the first delay line of the configurable delay paths are enough;
the falling edge modulation module of the configurable delay path is used for generating a control signal for performing falling edge modulation on the clock signal to be calibrated according to the pulse width information and performing falling edge modulation on the clock signal to be calibrated according to the control signal;
and the phase interpolation module is used for obtaining a clock signal with a calibrated duty ratio according to the clock signal to be calibrated after the falling edge modulation is carried out.
2. The duty cycle calibration circuit of claim 1, wherein the adaptive control module automatically configures a delay time length of the first delay line of the configurable delay path according to the pulse width detection result;
the automatic pulse width detection module is specifically configured to determine whether the time delay length of the first delay path is sufficient to detect the high-level pulse width information and determine whether the time delay length of the first delay path is sufficient to detect the low-level pulse width information, and if both the time delay lengths are sufficient to detect the low-level pulse width information, the adaptive control module determines that the first delay path performs time delay on the clock signal to be calibrated;
if any one of the two delay paths is not enough to be detected, the adaptive control module determines the next adjacent delay path, the automatic pulse width detection module continuously judges whether the time delay length of the next adjacent delay path is enough to detect the high-level pulse width information and judges whether the time delay length of the next adjacent delay path is enough to detect the low-level pulse width information, and if both the time delay lengths are enough to detect the low-level pulse width information, the adaptive control module determines that the next adjacent delay path carries out time delay on the clock signal to be calibrated;
if any one of the delay paths is not enough to be detected, the self-adaptive control module continues to determine the next adjacent delay path, and the automatic pulse width detection module repeats the step of continuing judgment.
3. The duty cycle calibration circuit of claim 2, wherein the automatic pulse width detection module comprises a first D flip-flop, a second D flip-flop, a high level pulse width information processing module, and a low level pulse width information processing module; the high-level pulse width information processing module comprises a plurality of high-level pulse width information processing circuits, and the low-level pulse width information processing module comprises a plurality of low-level pulse width information processing circuits;
the D end of the first D trigger is connected with the clock signal to be calibrated, the clock input end of the first D trigger is connected with the delay signal output by the corresponding delay unit, and the Q end of the first D trigger is connected with the first input end of the high-level pulse width information processing circuit;
the D end of the second D trigger is connected with the clock signal to be calibrated, the clock input end of the second D trigger is connected with the delay signal output by the corresponding delay unit, and the Q end of the second D trigger is connected with the first input end of the low-level pulse width information processing circuit;
the first output end of the high-level pulse width information processing circuit is connected with the first input end of the high-level pulse width information processing circuit in the next high-level pulse width information processing module; the first output end of the low-level pulse width information processing circuit is connected with the first input end of the low-level pulse width information processing circuit in the next low-level pulse width information processing module;
the rising edge of the clock signal to be calibrated triggers the first D trigger to acquire the high-level pulse width information, and the high-level pulse width information processing circuit is used for processing the high-level pulse width information; and the falling edge of the clock signal to be calibrated triggers the second D trigger to acquire the low-level pulse width information, and the low-level pulse width information processing circuit is used for processing the low-level pulse width information.
4. The duty cycle calibration circuit of claim 3, wherein the high level pulse width information comprises a high level end position and the low level pulse width information comprises a low level end position; the adaptive control module comprises a counter;
the automatic pulse width detection module judges whether the time delay length of the first delay path is enough to detect the high-level pulse width information according to the high-level end position, and judges whether the time delay length of the first delay path is enough to detect the low-level pulse width information according to the low-level end position to obtain delay path configuration information;
the self-adaptive control module judges whether the numerical value of the counter is increased by one according to the delay path configuration information, if the delay path configuration information is enough to be detected, the numerical value of the counter is unchanged, and the self-adaptive control module determines that the first delay path carries out time delay on the clock signal to be calibrated; if any one of the delay path configuration information is not enough to be detected, the value of the counter is increased by one, the automatic pulse width detection module continues to judge whether the time delay length of the next adjacent delay path is enough to detect the high level pulse width information according to the high level end position, and judges whether the time delay length of the next delay path is enough to detect the low level pulse width information according to the low level end position to obtain the delay path configuration information, and the adaptive control module continues to judge whether the value of the counter is increased by one according to the delay path configuration information.
5. The duty cycle calibration circuit of claim 2, wherein the falling edge modulation module of the configurable delay path comprises control logic circuitry;
the control logic circuit is specifically configured to compare the high-level pulse width information with the low-level pulse width information, obtain a comparison result and a difference value of the high-level pulse width information and the low-level pulse width information, and generate a control signal for performing falling edge modulation on the clock signal to be calibrated according to the comparison result and the difference value;
and the falling edge modulation module of the configurable delay path performs falling edge modulation on the clock signal to be calibrated according to the control signal.
6. The duty cycle calibration circuit of claim 5, wherein the falling edge modulation module of the configurable delay path comprises the second delay line, the second delay line is connected in series with a plurality of delay units, each delay unit comprises one or more delay paths, the total delay time of the former delay path is less than that of the latter delay path, the number of delay paths of the second delay line is the same as that of the first delay line of the configurable delay path, the delay time of the ith delay unit of the second delay line is half of that of the ith delay unit of the first delay line of the configurable delay path, and i is a positive integer greater than or equal to 1.
7. The duty cycle calibration circuit of claim 1, wherein the number of delay paths is 3 and the number of delay cells is 16.
8. The duty cycle calibration circuit of claim 1, further comprising: a clock signal generating circuit;
the clock signal generating circuit generates a first clock signal to be calibrated and a second clock signal to be calibrated, wherein the first clock signal to be calibrated and the second clock signal to be calibrated are differential clock signals.
The falling edge modulation module of the configurable delay path performs falling edge modulation on the first clock signal to be calibrated and the second clock signal to be calibrated;
and the phase interpolation module is used for processing the first clock signal to be calibrated and the second clock signal to be calibrated after the falling edge modulation is carried out, so as to obtain the clock signal with the calibrated duty ratio.
9. The duty cycle calibration circuit of claim 8, wherein the phase interpolation module comprises an inverter;
and the phase inverter processes the first clock signal to be calibrated and the second clock signal to be calibrated after the falling edge modulation is carried out, so as to obtain the clock signal with the calibrated duty ratio.
10. A duty cycle calibration method, characterized in that, the duty cycle calibration circuit of any one of claims 1-9 is used to perform the duty cycle calibration on the clock signal to be calibrated.
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CN114489239A (en) * 2022-01-21 2022-05-13 国微集团(深圳)有限公司 Method and device for dynamically calibrating real-time clock
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CN113778057A (en) * 2021-09-13 2021-12-10 深圳茂硕电子科技有限公司 Time sequence correction method and system for DALI (digital addressable lighting interface) control device
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