CN114070762B - Network monitoring probe assembly, synchronization method and data acquisition and analysis device - Google Patents

Network monitoring probe assembly, synchronization method and data acquisition and analysis device Download PDF

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Publication number
CN114070762B
CN114070762B CN202010743304.2A CN202010743304A CN114070762B CN 114070762 B CN114070762 B CN 114070762B CN 202010743304 A CN202010743304 A CN 202010743304A CN 114070762 B CN114070762 B CN 114070762B
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time
network monitoring
monitoring probe
probe assembly
time stamp
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CN114070762A (en
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张蕾
李金艳
李红祎
赵一荣
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China Telecom Corp Ltd
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China Telecom Corp Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/14—Arrangements for monitoring or testing data switching networks using software, i.e. software packages

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Electric Clocks (AREA)

Abstract

The invention relates to a network monitoring probe assembly, a synchronization method and a data acquisition and analysis device. The network monitoring probe assembly includes: the GPS time service module is used for acquiring GPS time information; the high-frequency clock module generates a high-frequency clock signal; the data acquisition module acquires data, generates a time stamp request when a time stamp is needed for the acquired data, and sends the time stamp request to the clock synchronization control module, and reads the time stamp from the clock synchronization control module in response to receiving a time stamp ready notification; and a clock synchronization control module that acquires GPS time information from the GPS time service module, acquires a high-frequency clock signal from the high-frequency clock module, generates a coarse time portion of the time stamp using the GPS time information, generates a fine time portion of the time stamp using the high-frequency clock signal and a correction factor that is a time delay correction amount for synchronizing the time stamp of the network monitoring probe assembly with the time stamp of the network monitoring probe assembly as a reference, and generates the time stamp based on the coarse time portion and the time portion.

Description

Network monitoring probe assembly, synchronization method and data acquisition and analysis device
Technical Field
The invention belongs to the technical field of 5G communication, and particularly relates to a network monitoring probe assembly, a synchronization method and a data acquisition and analysis device for safety monitoring of a 5G core network capability open interface.
Background
The core network of the fifth generation mobile communication network has been added with a special feature-network function opening (NEF, network Exposure Function) before. The network function open service is the result of the core network of the mobile communication network moving from the previous 2G/3G/4G closure to the opening, can meet more sexualization demands, follows the market opening demands, and adapts to new market systems.
In the 5G network architecture, open services provided by the network function open are: basic resources, value added services, data information and operation support. The 5G network function is opened to perform capacity adaptation, encapsulation, partial arrangement and finally provide network capacity for a third party through a unified interface on basic resources, value-added services, data information, operation support, user data value-added services, infrastructure and the like of the core network.
The network capability opening is a service oriented to a third party outside the network, the security of the network is extremely important, all-weather monitoring and prevention are required, and a capability opening caller is required to be fully authenticated and network information is required to be effectively protected. At present, in order to effectively isolate network resources from third party invokers, a NEF gateway is adopted to carry out information transfer processing, and the third party invokers must pass through the NEF gateway to obtain the network resources.
In order to ensure network security in the access process of a third party caller, necessary monitoring software can be deployed on the NEF gateway, and equipment such as a firewall is added on each of the north and south routes of the NEF gateway, but the load of the NEF gateway is greatly increased, the time delay and complexity of the call are increased, and effective analysis of access relevance from data depth based on time dimension is difficult to realize.
The probes for the monitoring system are distributed and deployed on different network element interfaces, the network elements often process different physical space positions, to effectively monitor the interfaces, the probes deployed in the system must form a whole, and it is particularly important to perform clock synchronization; the probe is used for detecting the accurate moment of information occurrence in the interface, the moment is an important judgment condition for judging the information flow direction and carrying out accurate tracking, and the accuracy is extremely important.
The probe can time stamp the received information (i.e. time stamp) in the process of detecting the information; one piece of information passes through a plurality of interfaces in sequence on a network and is detected by probes on the corresponding interfaces, and the time stamp of the probe for the information should correspond to the sequence of the information passing through each interface; if the time of each probe is not synchronous, serious consequences are caused, information is detected later, the time of the information is instead detected in front, and vice versa, so that the information is disordered in time, accurate tracking of information flow cannot be realized, reliable and basic support cannot be provided for later advanced statistical analysis, such as appearance time, the stay time length of a certain network element, the occurrence frequency among related information and the like.
Disclosure of Invention
The problem of time synchronization of probes is important in a distributed monitoring system, particularly in a 5G core network, and the flow rate of the probe are greatly improved compared with the prior method. Heretofore, each network element in the core network and monitoring software installed on the network element often adopts an NTP (Network Time Protocol ) mode to perform clock synchronization, and each network element obtains synchronization time from a specified time server through the NTP protocol, so that in order to keep synchronization errors within a certain range, synchronization operation is often required to be performed periodically. The mode of NTP synchronization is realized by a software system through an NTP protocol, a transmission network and the like, and the average precision of time synchronization is not high and sometimes the time stamp precision requirement of a probe cannot be met due to the processing process of the protocol, particularly the delay of transmission on different network paths.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a network monitoring probe assembly and a clock synchronization method of the network monitoring probe assembly that achieve higher precision time synchronization and better meet the time synchronization precision requirements of distributed probes.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. It should be understood, however, that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its purpose is to present some concepts related to the invention in a simplified form as a prelude to the more detailed description that is presented later.
According to one aspect of the present invention, there is provided a network monitoring probe assembly comprising: a GPS time service module for acquiring GPS time information, wherein the GPS time information comprises pulse per second signals (PPS) and real-time clock information (RTC); the high-frequency clock module generates a high-frequency clock signal; the data acquisition module acquires data, generates a time stamp request when time stamps are needed for the acquired data, and sends the time stamp request to the clock synchronization control module, and reads the time stamps from the clock synchronization control module in response to receiving a time stamp ready notification from the clock synchronization control module; and the clock synchronization control module acquires the GPS time information from the GPS time service module, acquires the high-frequency clock signal from the high-frequency clock module, generates a coarse time part of a time stamp by using the GPS time information, generates a fine time part of the time stamp by using the high-frequency clock signal and a correction factor, and generates the time stamp according to the coarse time part and the time part, wherein the correction factor is a time delay correction amount for synchronizing the time stamp of the network monitoring probe assembly with the time stamp of the network monitoring probe assembly serving as a reference.
According to another aspect of the present invention, there is provided a data acquisition and analysis apparatus comprising: more than one of the above network monitoring probe assemblies; a data storage storing the collected data; and a data analysis device for analyzing the acquired data.
According to an aspect of the present invention, there is provided a clock synchronization method of a network monitoring probe assembly, the network monitoring probe assembly being the above-mentioned network monitoring probe assembly, the clock synchronization method comprising: in the case that the corrected network monitoring probe assembly and the network monitoring probe assembly serving as a reference are started simultaneously, the nanosecond timer serving as the reference of the network monitoring probe assembly starts counting from the arrival time of the edge of the pulse signal per second, stops counting when the edge of the next pulse signal per second arrives, and notifies the corrected network monitoring probe assembly through a synchronous interface; responsive to receiving the notification, the corrected network monitoring probe component stops counting; taking the difference value between the count value of the nanosecond counter of the corrected network monitoring probe assembly and the count value of the nanosecond counter of the network monitoring probe assembly serving as a reference as a correction factor; and generating a timestamp using the high frequency clock signal and a correction factor.
According to one or more embodiments of the invention, a higher-precision time stamp can be provided, a powerful support is provided for the integrated monitoring of the distributed deployed probes, and a basic guarantee is provided for analysis of the occurrence time of data in a monitored network, the flow direction tracking and the like. .
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. The invention may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a block diagram illustrating a network monitoring probe assembly 1 according to one embodiment of the invention.
Fig. 2 is a block diagram illustrating a data acquisition analysis apparatus 100 according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating correction factors for a network monitor probe assembly.
Fig. 4 is a flow chart illustrating a method of clock synchronization of a network monitoring probe assembly according to one embodiment of the invention.
Fig. 5 shows a hardware configuration diagram of an application example according to the present invention.
Fig. 6 shows a flow chart for correcting the high frequency clock module.
Fig. 7 is a flow chart illustrating a flow of time stamping generated by the network monitoring probe component.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Fig. 1 is a block diagram illustrating a network monitoring probe assembly 1 according to one embodiment of the invention.
In fig. 1, the network monitoring probe assembly 1 comprises a GPS timing module 11, a high frequency clock module 12, a data acquisition module 13 and a clock synchronization control module 14.
The GPS timing module 11 is configured to acquire GPS Time information, where the GPS Time information includes a Pulse Per Second (PPS) and a Real Time Clock (RTC). The GPS time service module 11 receives GPS satellite signals through an antenna, and calculates PPS and RTC. The calculated PPS pulse signal gps_pps is a high-precision signal having a period of 1 second, and the leading edge of each pulse signal is input to the clock synchronization control module 14 for the internal processing trigger signal of the clock synchronization control module 14. The resolved RTC time gps_rtc is fed to the clock synchronization control module 14 as the "chrono-lunar chrono-minute-second" part of the combined timestamp, i.e. the coarse time part. In order to ensure the consistency of the solutions of each GPS module PPS, RTC, it is preferable to use the same manufacturer, the same batch of modules. The GPS timing module receives GPS satellite signals to calculate PPS and RTC, and since the probe is usually deployed inside the machine room, there is often no signal or the signal is too weak, and thus, in one embodiment, the outdoor GPS signal is introduced to the GPS timing module 11 through the mushroom antenna and the coaxial cable.
The high frequency clock module 12 is configured to generate a high frequency clock signal to provide a stable timing signal for the local clock. In one embodiment, the high frequency clock module 12 may employ a high frequency active crystal oscillator. In one embodiment, the active crystal oscillator may be of a temperature compensated type to improve the stability of the signal frequency. In one embodiment, the high frequency clock module 12 may employ a high precision crystal that is a 100MHz 0.1ppm temperature compensated active crystal.
The data acquisition module 13 is configured to acquire data, generate a time stamp request when a time stamp is required for the acquired data, and send the time stamp request to the clock synchronization control module 14. Further, the data acquisition module 13 reads the time stamp from the clock synchronization control module 14 in response to receiving a time stamp ready notification from the clock synchronization control module 14.
The clock synchronization control module 14 acquires GPS time information from the GPS time service module 11, acquires a high-frequency clock signal from the high-frequency clock module 12, generates a coarse time portion of a time stamp using the GPS time information, generates a fine time portion of the time stamp using the high-frequency clock signal and a correction factor, and generates a time stamp based on the coarse time portion and the time portion. The correction factor is a delay correction amount for synchronizing the time stamp of the network monitoring probe assembly 1 with the time stamp of the network monitoring probe assembly as a reference. In one embodiment, the clock synchronization control module 14 may be implemented by a field programmable gate array (FPGA, field Programmable Gate Array) or by an application specific integrated circuit (ASIC, application Specific Integrated Circuit).
In one embodiment, the clock synchronization control module 14 further includes a frequency multiplier that multiplies the acquired high frequency clock signal. In one embodiment, the frequency multiplier may be a phase-locked loop circuit.
In one embodiment, the clock synchronization control module 14 includes a nanosecond counter that counts on the order of nanoseconds with a high frequency clock signal. By using a counter on the order of nanoseconds, clocking with accuracy of microsecond or more can be achieved.
In one embodiment, the clock synchronization control module 14 further includes a synchronization interface via which the trigger signal is received, and the clock synchronization control module 14 calculates the delay correction amount according to the trigger signal and the count value of the nanosecond counter.
In one embodiment, the clock synchronization control module 14 includes a coarse TIME register (rtc_time_reg), a fine TIME register (us_time_reg), a TIME STAMP register (time_stamp_reg), a nanosecond count register (ns_counter_reg), and a TIME delay correction register (ns_correct_reg), the coarse TIME register updating in response to arrival of an edge of the pulse signal per second and storing real-TIME clock information as a coarse TIME portion of a TIME STAMP, the fine TIME register storing a fine TIME portion of a TIME STAMP generated from a count value of the nanosecond COUNTER and a corrected value of the TIME delay correction, the TIME STAMP register storing the generated TIME STAMP, the nanosecond count register storing a count value of the nanosecond COUNTER, and the TIME delay correction register storing the TIME delay correction amount.
In one embodiment, the delay correction amount is an amount of time corresponding to a difference between a count value of a nanosecond counter of the network monitoring probe assembly 1 and a count value of a nanosecond counter of the network monitoring probe assembly as a reference, in a period from when an edge of the pulse signal PPS arrives every second to when an edge of the pulse signal PPS next arrives, in a case where the network monitoring probe assembly 1 and the network monitoring probe assembly as a reference are started simultaneously. In one embodiment, the delay correction amount is an average of a plurality of the time amounts.
Fig. 2 is a block diagram illustrating a data acquisition analysis apparatus 100 according to an embodiment of the present invention.
As shown in fig. 2, the data acquisition and analysis device 100 includes a data storage 2, a data analysis device 3, and a plurality of network monitoring probe assemblies 1. The memory 2, the data analysis device 3 and the plurality of network monitoring probe assemblies 1 are communicatively connected. Two network monitoring probe assemblies 1 are exemplarily shown in fig. 2, but the number of network monitoring probe assemblies 1 may be arbitrary, which matches the number of network elements to be monitored.
Each network monitoring probe assembly monitors data of each 5G network element port. For example, in one embodiment, the network monitoring probe assembly 1 monitors data of an access and mobility management function network element AMF (not shown), and the network monitoring probe assembly 1' monitors data of a session management function network element SMF (not shown). The network monitoring probe assemblies 1 and 1' respectively acquire the data of the AMF and SMF network elements and acquire the time stamp from the clock synchronization control module 14, the network element data and the time stamp are combined and transmitted and stored in the data memory 2, the data analysis device 3 directly acquires the combined information of the network element data and the time stamp from the data memory 2 or each network monitoring probe assembly and performs various analyses, and the analysis result is output.
Fig. 3 is a schematic diagram illustrating correction factors for a network monitor probe assembly.
One embodiment of determining the correction FACTOR ns_correct_factor is described below with reference to fig. 3. Before deploying the network monitor probe assemblies, selecting one network monitor probe assembly from the plurality of network monitor probe assemblies as a reference network monitor probe assembly, and performing time delay alignment of the other network monitor probe assemblies with the reference network monitor probe assembly.
As previously mentioned, each network monitoring probe assembly has a synchronous interface, with the interfaces being connected by cables. In one embodiment, the cable may be a coaxial cable. The network monitoring probe assembly with corrected time delay and the network monitoring probe assembly as reference time delay start to work simultaneously, and the nanosecond counter is started to count when the GPS_PPS edge is detected to arrive respectively, and when the nanosecond counter count value of the network monitoring probe assembly with reference time delay reaches a preset value (for example, 10 9 (corresponding to 1 second)) immediately informing the network monitoring probe assembly of the corrected delay through the synchronization interface to stop counting, and determining the relative delay difference by calculating the difference between the count values in the nanosecond count register ns_counter_reg of the two network monitoring probe assemblies. In one embodiment, the relative delay difference may be determined from a plurality of averages of the difference, thereby further improving accuracy. In one embodiment, the count number may be set to 30. Assume that the count value of each time the delay probe is corrected is identified as ns_counter_reg_cor n Then the value of ns_correct_reg can be found by the following equation (1):
it should be understood that the number of counts is not limited to 30 and may be arbitrarily set according to actual needs.
NS_CORRECT_REG>At 0, the early time delay T of the network monitoring probe assembly with corrected time delay delay Smaller;
when ns_correct_reg=0, the network monitoring probe assembly with corrected delay has a front-end delay T delay The time delay is the same as that of a reference time delay probe;
NS_CORRECT_REG<at 0, the early time delay T of the network monitoring probe assembly with corrected time delay delay Larger;
the calculated ns_correct_reg is the signed number, the value of which is written to a memory stored in non-volatile memory. When the network monitoring probe assembly is started, a value is loaded into the NS_CORRECT_REG from a nonvolatile memory.
As shown in figure 3, T delay_ref And T is delay_cor Under the condition that GPS_PPS simultaneously appears, T is caused by the time difference calculated by respective GPS time service modules and the signal time delay difference on a circuit delay_ref And T is delay_cor Is different in size. Correction factor reflects T delay_ref And T is delay_cor Is a difference in (c). The time stamps of the individual network monitoring probe assemblies are synchronized by the compensation of the correction factors.
Fig. 4 is a flow chart illustrating a method of clock synchronization of a network monitoring probe assembly according to one embodiment of the invention.
As shown in fig. 4, in step S401, when the corrected network monitoring probe assembly and the network monitoring probe assembly as a reference are started simultaneously, the nanosecond timer as the reference network monitoring probe assembly starts counting from the arrival of the edge of the pulse signal PPS per second.
Next, in step S402, counting is stopped and the corrected network monitoring probe assembly is notified via the synchronization interface when the edge of the next pulse signal per second arrives.
Next, in step S403, in response to receiving the notification, the corrected network monitoring probe component stops counting.
Next, in step S404, a difference between the count value of the nanosecond counter of the network monitoring probe assembly being corrected and the count value of the nanosecond counter of the network monitoring probe assembly serving as a reference is used as a correction factor.
Next, in step S405, a time stamp is generated using the high frequency clock signal and a correction factor.
< application example >
Specific hardware application examples will be described below. It should be noted that the parameters, model numbers, and the like of the hardware listed below are merely examples, and are not intended to limit the scope of the claims of the present invention, and can be replaced or changed as appropriate within the scope of the concept and spirit of the present invention.
For the 5G core network, particularly for the network capability opening part, network services are provided for external third party applications through a capability opening platform, and particularly, the network security aspect is outstanding, so that more effective monitoring can be performed through a distributed monitoring system. In a monitoring system, the acquisition of network data is realized by adopting network monitoring probe assemblies distributed on a plurality of network nodes, and the time synchronization precision among the network monitoring probe assemblies is important to realize the accurate tracking of the network data. The more accurate the clock synchronization between the network monitor probe components, the higher the degree of network monitor probe component integrity.
In the application example, in order to ensure the clock synchronization precision reaching microsecond level or more, the network monitoring probe assembly adopts a high-speed FPGA, a GPS time service module and a 0.1ppm100MHz temperature compensation crystal oscillator as a hardware base. In the application example, the FPGA realizes the functions of a data acquisition module and a clock synchronous control module. It should be understood that the data acquisition module and the clock synchronization control module may be implemented by separate devices, or may be implemented using dedicated chips.
Fig. 5 shows a hardware configuration diagram of an application example according to the present invention.
Referring to fig. 5, in the implementation architecture of the present invention, an FPGA serving as a core control is connected to a GPS timing module through a level signal and a serial interface, connected to a 0.1ppm100mhz temperature compensation crystal oscillator through a clock interface, connected to a data acquisition module through an internal interface, and connected to other network monitoring probe assemblies through a synchronization interface.
The GPS time service module provides a PPS second alignment function with extremely high precision on one hand, provides RTC time information including year, month, day, time, minute and second on the other hand, and the GPS time service precision can reach 10 -9 Second, belonging to the nanosecond scale, is represented by a high-precision PPS signal, i.e. the time precision between two PPS pulse edges adjacent one after the other reaches the nanosecond scale, but there is no finer evenly distributed clock signal between the two PPS pulse edges. The GPS time service module is connected with the FPGA and provides 2 paths of signals, one path is a PPS pulse signal, and the other path is a serial signal.
The high-precision crystal oscillator serving as the high-frequency clock module is a 0.1ppm temperature compensation type active crystal oscillator of 100MHz, and provides a stable timing signal for a local clock. The high-precision crystal oscillator is connected with the FPGA and provides a periodic oscillation signal of 100MHz for the FPGA. Of course, the high-precision crystal oscillator can select proper frequency and precision according to practical conditions, for example, the crystal oscillator with higher frequency and better precision is selected.
The FPGA acquires and processes 3 paths of clock signals from the GPS time service module and the high-precision crystal oscillator, and outputs high-precision time stamps with year, month, day, time, minute, second and microsecond to the data acquisition module; in addition, a synchronous interface for time delay correction between different network monitoring probe assemblies is arranged on the FPGA.
The GPS time service module receives GPS satellite signals and calculates PPS and RTC. Network monitoring probe assemblies are typically deployed inside a machine room, often without or with weak signals, thereby requiring the introduction of outdoor GPS signals onto a GPS timing module through a mushroom antenna and coaxial cable. The calculated PPS pulse signal GPS_PPS is a high-precision signal with the period of 1 second, and the front edge of each pulse is input into the FPGA as a trigger signal for internal processing of the FPGA. The resolved RTC time gps_rtc is fed to the FPGA through the serial port in a fixed clear protocol format as the coarse time part of the combined timestamp. In order to ensure the consistency of the PPS and RTC solutions of a plurality of GPS modules, the GPS modules of the same manufacturer and the same batch are preferably selected.
The high-precision active crystal oscillator singly provides 100MHz and 0.1ppm of signal OSC_100MHz for the FPGA, and a temperature compensation type is selected for improving the stability of signal frequency. This signal acts as a counting source in clock synchronization that generates a "fine time".
The high-speed FPGA is a processing part in clock synchronization, and is externally provided with 4 interfaces: an interface for connecting a GPS time service module, an interface for connecting a high-precision crystal oscillator, a component synchronization interface and a time stamp output interface (in an application example, the interface is connected with other modules in the FPGA). There are 5 registers designed inside the high-speed FPGA: coarse TIME register rtc_time_reg, fine TIME register us_time_reg, TIME STAMP register time_stamp_reg, nanosecond count register ns_counter_reg, delay correction register ns_correct_reg. In addition, a correction FACTOR ns_correct_factor stored in the nonvolatile memory is provided.
The FPGA synchronous clock processing process includes 2 stages: a base synchronization stage and a delay correction stage.
First, the basic synchronization phase is explained.
The FPGA firstly uses the phase-locked loop in the FPGA to carry out 10 times frequency processing on the input OSC_100MHz signal to obtain a signal PLL_1GHZ of 1GHZ, and the signal PLL_1GHZ is used for pushing nanosecond counting to count. When the FPGA detects that the GPS_PPS edge arrives, the FPGA starts to asynchronously clear the NS_COUNTER_REG and starts the nanosecond COUNTER to start counting, and when the FPGA detects that the data acquisition module requests the arrival of the time stamp signal, the FPGA synchronously stops counting of the nanosecond COUNTER, and the count value of the COUNTER is stored in the NS_COUNTER_REG. The nanosecond pulse is adopted for counting, and finally the nanosecond pulse is converted into microsecond with fine time, so that the accuracy of time can be improved.
Next, the delay correction stage is explained.
The FPGA carries out delay correction on the NS_COUNTER_REG according to the value in the NS_CORRECT_REG, intercepts microsecond parts from the corrected value and assigns the microsecond parts to the US_TIME_REG. The RTC TIME is also read and assigned to rtc_time_reg when the FPGA detects that a gps_pps edge arrives. The FPGA assembles the rtc_time_reg and us_time_reg into a completed timestamp that is stored in the time_stamp_reg and notifies the acquisition module to take the timestamp.
The following two clock correction processes can be performed before the FPGA clock synchronization is formally enabled to ensure the accuracy of the time stamp: the high-frequency clock module is used for correcting the stability of the PLL_1GHZ signal within 1 second; and correction FACTOR correction processing for determining a correction FACTOR ns_correct_factor.
(1) High frequency clock module correction process
The high frequency clock module corrects the pll_1ghz signal to be stable within a predetermined range. Fig. 6 shows a flow chart for correcting the high frequency clock module.
As shown in fig. 6, at the start of correction, when the FPGA detects the gps_pps edge arrival, the nanosecond COUNTER is started to count, when the FPGA detects the next gps_pps edge arrival, the FPGA stops counting, and then judges whether the value in ns_counter_reg is 100 (i.e., 10 9 ×(±10 -7 ) Fluctuation in the range, repeating the measurement 30 times. If yes, the OSC_100MHz crystal oscillator meets the requirement of 0.1ppm of stability, a green indicator lamp on the board card is lightened, otherwise, the green indicator lamp on the board card is lightened, the replacement of the OSC_100MHz crystal oscillator is prompted, and then the stability measurement of the PLL_1GHZ signal is continued until the green indicator lamp is lightened.
(2) Correction factor correction process
The correction FACTOR correction process is used to determine a correction FACTOR ns_correct_factor.
After the previously calibrated stability of pll_1ghz meets the requirement, before deploying the network monitor probe assemblies, selecting one network monitor probe assembly from the plurality of network monitor probe assemblies as a network monitor probe assembly with clock reference delay, and performing delay alignment on the other network monitor probe assemblies with the network monitor probe assembly as the reference delay. As mentioned before, each network monitoring probe assembly has a synchronous interface, the interfaces are connected by coaxial cables, the two network monitoring probe assemblies start working simultaneously, a nanosecond counter is started to count when the GPS_PPS edge is detected to arrive respectively, and the reference time delay network monitoring probe assembly count reaches 10 9 At once, another network monitoring probe assembly (i.e., delay corrected network monitoring probe assembly) is notified via the inter-board synchronization interface) The counting is stopped and the relative delay difference is determined by calculating the multiple average of the differences between ns_counter_regs of the two network monitoring probe assemblies, as an example the selected number of counts is 30. The count value of each time of the network monitoring probe assembly assumed to be corrected for delay is identified as ns_counter_reg_cor n . The value of ns_correct_reg is:
NS_CORRECT_REG>at 0, the early time delay T of the network monitoring probe assembly with corrected time delay delay Smaller;
when ns_correct_reg=0, the network monitoring probe assembly with corrected delay has a front-end delay T delay The time delay is the same as that of a reference time delay probe;
NS_CORRECT_REG<at 0, the early time delay T of the network monitoring probe assembly with corrected time delay delay Larger;
ns_correct_reg is a signed number whose value is written to a memory stored in non-volatile memory. The value is loaded into ns_correct_reg from nonvolatile memory at the start of the network monitoring probe assembly.
As shown in figure 3, T delay_ref And T is delay_cor Under the condition that GPS_PPS simultaneously appears, T is caused by the time difference calculated by respective GPS time service modules and the signal time delay difference on a circuit delay_ref And T is delay_cor Is different in size. NS_CORRECT_REG reflects T delay_ref And T is delay_cor Is a difference in (c).
After calibration is complete, the network monitoring probe assembly can be deployed to each monitored network interface to begin operation.
Fig. 7 is a flow chart illustrating a flow of time stamping generated by the network monitoring probe component. As shown in fig. 7, the time stamp generation includes the steps of:
when the FPGA detects that the gps_pps edge arrives in step S701, then in step S702, asynchronous zero clearing of the ns_counter_reg is started and the nanosecond COUNTER is started to start counting. Next, in step S703, the FPGA determines whether a signal requesting the time stamp from the data acquisition module is detected, and when the FPGA detects that the signal requesting the time stamp from the data acquisition module arrives (i.e., yes in step S703), the FPGA proceeds to step S704 to asynchronously stop counting by the nanosecond COUNTER, where the count value of the COUNTER is stored in the ns_counter_reg. Next, in step S705, the FPGA performs delay correction on the ns_counter_reg according to the value in the ns_correct_reg, and intercepts the microsecond part from the corrected value and assigns it to the us_time_reg, forming a microsecond part of a fine TIME (step S706). Next, in step S707, the FPGA reads the RTC TIME assignment to rtc_time_reg when detecting that the gps_pps edge arrives, forming a part of the coarse TIME. Next, in step S708, the FPGA stores the completed TIME STAMPs assembled from rtc_time_reg and us_time_reg in time_stamp_reg and notifies the acquisition module to take the TIME STAMPs. If the data acquisition module does not receive a request for a time stamp signal within a 1 second period, it recounts when the next GPS PPS edge arrives. Steps S701 to S707 are repeated thereafter.
Further, in one embodiment, the fine time portion in step S706 is not limited to microseconds, e.g., a fraction of one tenth of a microsecond, one hundredth of a microsecond may be reserved to further improve the accuracy of the timestamp.
According to the embodiment, the clock synchronization precision of the probe is improved by multiplying the frequency of 0.1ppm of 100MHz by a phase-locked loop in the FPGA, refining the counting granularity, and counting nanoseconds by using a GPS_PPS edge triggering nanosecond counter, and further, ensuring the stability of counting and time delay alignment among different network monitoring probe assemblies by two correction modes. Therefore, microsecond-level or even higher-precision time stamps can be provided, powerful support is provided for integrated monitoring of distributed deployed probes, and basic guarantee is provided for analysis of data occurrence time, flow direction tracking and the like in a monitored network.
It should be appreciated that reference throughout this specification to "an embodiment" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in an embodiment of the invention" or similar expressions in this specification are not necessarily referring to the same embodiment.
It will be appreciated by those skilled in the art that the present invention may be embodied as a system, apparatus, method, or computer readable medium (e.g., non-transitory storage medium) as a computer program product. Accordingly, the present invention may be embodied in various forms, such as entirely hardware embodiments, entirely software embodiments (including firmware, resident software, micro-program code, etc.), or software and hardware embodiments, which may all generally be referred to herein as a "circuit," module "or" system. Furthermore, the present invention may also be embodied in any tangible media form as a computer program product having computer usable program code stored thereon.
The relevant description of the present invention is described with reference to flowchart illustrations and/or block diagrams of systems, apparatuses, methods and computer program products according to specific embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and any combination of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be executed by a machine, such as a processor of a general purpose computer or special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the computer or other programmable data processing apparatus, create means for implementing the functions or acts specified in the flowchart and/or block diagram block or blocks.
In the drawings, flowcharts and block diagrams of architecture, functionality, and operation that can be implemented by systems, devices, methods, and computer program products according to various embodiments of the present invention are shown. Accordingly, each block in the flowchart or block diagrams may represent a module, segment, or portion of program code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some other embodiments, the functions described for the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order of the figures, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of market technology, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A network monitoring probe assembly, comprising:
a GPS time service module for acquiring GPS time information, wherein the GPS time information comprises pulse per second signals (PPS) and real-time clock information (RTC);
the high-frequency clock module generates a high-frequency clock signal;
the data acquisition module acquires data, generates a time stamp request when time stamps are needed for the acquired data, and sends the time stamp request to the clock synchronization control module, and reads the time stamps from the clock synchronization control module in response to receiving a time stamp ready notification from the clock synchronization control module; and
the clock synchronization control module acquires the GPS time information from the GPS time service module, acquires the high-frequency clock signal from the high-frequency clock module, generates a coarse time part of a time stamp by using the GPS time information, generates a fine time part of the time stamp by using the high-frequency clock signal and a correction factor, and generates the time stamp according to the coarse time part and the fine time part, wherein the correction factor is a time delay correction amount for synchronizing the time stamp of the network monitoring probe assembly with the time stamp of the network monitoring probe assembly serving as a reference.
2. The network monitoring probe assembly of claim 1, wherein,
the clock synchronization control module includes a frequency multiplier that multiplies the high frequency clock signal.
3. The network monitoring probe assembly of claim 1, wherein,
the clock synchronization control module includes a nanosecond counter that counts on the order of nanoseconds using the high frequency clock signal.
4. The network monitoring probe assembly of claim 1, wherein,
the clock synchronization control module comprises a synchronization interface, receives a trigger signal through the synchronization interface, and calculates the time delay correction amount according to the trigger signal and the count value of the nanosecond counter.
5. The network monitoring probe assembly of claim 1, wherein,
the clock synchronization control module comprises a coarse time register, a fine time register, a time stamp register, a nanosecond count register and a time delay correction register,
the coarse time register updates and stores the real-time clock information as a coarse time portion of a time stamp in response to arrival of the edge of the pulse signal per second, the fine time register stores a fine time portion of a time stamp generated from a count value of a nanosecond counter and the time delay correction amount corrected value, the time stamp register stores the generated time stamp, the nanosecond count register stores the count value of the nanosecond counter, and the time delay correction register stores the time delay correction amount.
6. The network monitoring probe assembly of claim 3, wherein,
the delay correction amount is an amount of time corresponding to a difference between a count value of a nanosecond counter of the network monitoring probe assembly and a count value of a nanosecond counter of the network monitoring probe assembly serving as a reference, in a period from when the edge of the pulse signal per second arrives to when the edge of the pulse signal per second arrives next, in a case where the network monitoring probe assembly and the network monitoring probe assembly serving as the reference are simultaneously started.
7. The network monitoring probe assembly of claim 6, wherein,
the delay correction amount is an average of a plurality of the time amounts.
8. The network monitoring probe assembly of claim 1, wherein,
the high-frequency clock module is a 100MHz 0.1ppm temperature compensation type active crystal oscillator.
9. A data acquisition analysis device comprising:
a network monitoring probe assembly according to any one of claims 1 to 8;
a data storage storing the collected data; and
and the data analysis device is used for analyzing the acquired data.
10. A method of clock synchronization of a network monitoring probe assembly according to any one of claims 1 to 8, the method comprising:
in the case that the corrected network monitoring probe assembly and the network monitoring probe assembly serving as a reference are started simultaneously, the nanosecond timer serving as the reference of the network monitoring probe assembly starts counting from the arrival time of the edge of the pulse signal per second, stops counting when the edge of the next pulse signal per second arrives, and notifies the corrected network monitoring probe assembly through a synchronous interface;
responsive to receiving the notification, the corrected network monitoring probe component stops counting;
taking the difference value between the count value of the nanosecond counter of the corrected network monitoring probe assembly and the count value of the nanosecond counter of the network monitoring probe assembly serving as a reference as a correction factor; and
a time stamp is generated using the high frequency clock signal and a correction factor.
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