CN114489239A - Method and device for dynamically calibrating real-time clock - Google Patents
Method and device for dynamically calibrating real-time clock Download PDFInfo
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Abstract
The invention discloses a method and a device for dynamically calibrating a real-time clock. The method for dynamically calibrating the real-time clock comprises the following steps: step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period; step 2, counting the local clock in each calibration period, and obtaining a dynamic calibration target set; and 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period. The invention can accurately calibrate the local clock, and avoids the time delay of software calibration and the CPU burden.
Description
Technical Field
The present invention relates to the technical field of real-time clock calibration, and in particular, to a method and an apparatus for iteratively and dynamically calibrating a real-time clock.
Background
The reference clock at which the Real Time Clock (RTC) operates is usually sourced from an internal crystal Oscillator (OSC). The difference between the crystal oscillator accuracies is a ubiquitous objective phenomenon, and the frequency of the OSC itself changes in different operating temperature environments and different operating humidity environments, i.e., the industry refers to the frequency deviation.
Under the condition that the crystal oscillator precision is influenced, accumulated errors can be introduced into the timing state or result in the RTC due to frequency deviation, if the accumulated errors are not timely offset, the timing result of the local RTC and the actual external time reference can be deviated, and negative influence is brought in the field of time synchronization required by multi-system interaction.
The error of the RTC crystal oscillator is objective, so that the realization of calibrating the RTC internal crystal oscillator is included in many related design fields. The implementation modes are also diversified, and include software calibration (which has low requirement on calibration accuracy) and hardware calibration (which has high requirement on calibration accuracy). Conventional software calibration is performed by periodically performing compensation correction on RTC-based real-time timing time data through operation of periodic software instructions to achieve the expected calibration. Software calibration is a periodic and timed behavior, and needs to apply a task of starting a CPU by timing query, which causes occupation of bus bandwidth and running overhead of the CPU.
Disclosure of Invention
The invention provides a method and a device for dynamically calibrating a real-time clock, which aim to solve the technical problems of overhead and lag caused by software calibration in the prior art.
The method for dynamically calibrating the real-time clock comprises the following steps:
step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period;
step 2, counting the local clock in each calibration period, and obtaining a dynamic calibration target set;
and 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
Further, the start time of the calibration period is the detection time of the reference clock to the falling edge of the local clock.
Further, the set of dynamic calibration targets includes: error analysis results, and one of an up-compensation calibration operation, a down-compensation calibration operation, and a compensation-less calibration operation.
Further, calibrating the local clock based on the up-conversion compensation calibration operation specifically includes:
generating an in-phase derived clock with a duty cycle different from 50%, wherein the in-phase derived clock and a local clock have the same frequency and the same phase;
generating an inversely derived clock with a duty cycle of not 50%, wherein the inversely derived clock and the local clock have the same frequency and are 180 degrees out of phase;
defining a compensation time slot counter, wherein the maximum counting value of the compensation time slot counter is the error analysis result;
and at the jump moment of each compensation time slot counter, extracting a clock of the appointed compensation time slot in the reverse derivative clock, and fusing the clock with the equidirectional derivative clock to generate a fast compensation clock serving as a calibrated real-time clock.
Further, calibrating the local clock based on the downconversion compensation calibration operation specifically includes:
generating an in-phase derived clock with a duty cycle different from 50%, wherein the in-phase derived clock and a local clock have the same frequency and the same phase;
defining a shielding time slot counter, wherein the maximum counting value of the shielding time slot counter is the error analysis result;
and shielding the clock pulse corresponding to the in-phase derived clock at the jumping time of each shielding time slot counter, and generating a slow compensation clock as a calibrated real-time clock.
Further, the duty cycle of the in-phase derived clock is 20%.
Further, the duty cycle of the inversely derived clock is 20%.
Further, the step 1 to the step 3 are executed by taking the calibrated real-time clock as the local clock to be calibrated again until the calibrated real-time clock reaches the preset calibration expectation.
Further, the error analysis result is an average value corresponding to a plurality of calibration period calibration analyses, or a real-time value corresponding to each calibration period calibration analysis.
Further, in step 3, when the error analysis result satisfies the effective calibration interval, the local clock is calibrated.
The device for dynamically calibrating the real-time clock comprises a reference clock and a local clock to be calibrated, and the method adopting the technical scheme is used for dynamically calibrating the local clock, and further comprises the following steps:
the calibration period generation module is used for monitoring the phases of the reference clock and the local clock and obtaining a calibration period;
the frequency offset error analysis and extraction module counts the local clock in each calibration period and obtains a frequency offset error and a dynamic calibration target set;
and the calibration output module is used for calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
Further, the calibration period generation module includes: the device comprises a reference clock and local clock starting phase alignment monitoring unit, a calibration period starting event generating unit and a calibration period ending event generating unit.
Further, the frequency offset error analyzing and extracting module comprises: the error analysis corresponds to the counter CNT (analysis), the local clock frequency deviation error analysis extraction unit.
Further, the calibration output module includes: the local clock fusion output unit comprises a local clock in-phase derivation unit, a local clock anti-phase derivation unit and a derivation clock fusion output unit.
The method can automatically construct a high-precision calibration period based on phase alignment, meanwhile, the initial phase alignment of the reference clock and the local clock is beneficial to improving the precision of local clock error analysis, the derived clock of the local clock can realize the dynamic real-time calibration of the local clock, and the derived clock obtained after the local clock is calibrated is subjected to secondary or iterative calibration so as to achieve the purpose of precision confirmation or improvement of calibration precision. Such as a calibration period expansion coefficient, for expanding the actual calibration period. Through the adjustment of the expansion coefficient of the calibration period, calibration targets with different error magnitudes can be met or considered. The reference clock and local clock start phase alignment monitoring unit is used for monitoring and ensuring that the generation of a calibration period and the calibration counting analysis are started at the time of phase alignment, determining a starting point of counting corresponding to error analysis in the calibration period, and feeding back the determined error to the calibration parameter.
The invention acquires the frequency deviation in real time, reduces the storage resource of the frequency deviation mapping table and reduces the delay of storing or acquiring the frequency deviation coefficient. The counting module of the frequency offset error is a cycle counter, and combines with the calibration period expansion coefficient to correspond to the cycle counting of corresponding times; and after the calibration period is finished, the loop counter locks the historical count value, so that the corresponding relation between the loop count value and the error analysis result is conveniently and quickly established. The error analysis result can provide subsequent calibration operation in real time, reduce the operations of storing, writing out, loading and reading back, and is favorable for avoiding the delay of calibration.
The effective calibration interval of the present invention reports a severe error condition when the error analysis exceeds the expected calibration range. So that the application can reconfigure the calibration target range or abandon the calibration operation as required. The effective calibration interval is a configuration parameter and controls the start of calibration operation; when the error analysis result is within the range of the effective calibration interval, automatically starting calibration operation; otherwise, the calibration operation is abandoned, and the state related to the error can be selectively reported. The idea of an effective calibration interval avoids the negative problems of unnecessary calibration power consumption or other design overhead.
The derived clock can effectively avoid the operation of calibrating the count value of the clock counter. The phenomena of unevenness and time jump in the process of acquiring the sub-second timing information are avoided. In different time intervals, according to different current real-time error analysis results, the up-conversion compensation calibration operation, the down-conversion compensation calibration operation and the compensation-free calibration operation may be dynamically selected to realize dynamic calibration. The local clock derived clock fusion output module performs fusion processing on the assigned time slots in the local clock in-phase derived clock and the local clock in the local clock anti-phase derived clock according to the dynamic calibration target set defined by the invention to generate the fast compensation calibration clock for local clock calibration. Or according to the dynamic calibration target set defined by the invention, the assigned time slot in the local clock in-phase derived clock is shielded to generate the slow compensation calibration clock for local clock calibration. The merging process is uniformly frequency-rising or flattening frequency-rising in the calibration period, so that the clock merges uniformly in the grouping in a complete calibration period. The masking process is a uniform downconversion or a flattening downconversion within a calibration period so that the clock masks the uniform packets for a complete calibration period. The invention can additionally add a local clock frequency offset error analysis and extraction module and a local clock calibration output module to recalibrate the derived clock calibrated by the local clock. The feedback precision confirmation before the calibration of the derived clock is that the final output calibration real-time clock can approach to the actual calibration expectation through starting an iterative calibration mode and carrying out multiple times of dynamic calibration.
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The invention is described in detail below with reference to examples and figures, in which:
FIG. 1 is a block diagram of a calibration period generation module according to the present invention.
Fig. 2 is a block diagram of a frequency offset error analyzing and extracting module according to the present invention.
FIG. 3 is a block diagram of a calibration output module according to the present invention.
Fig. 4 is a diagram illustrating a data flow according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a non-iterative calibration mode according to the present invention.
FIG. 6 is a diagram of an iterative calibration mode according to the present invention.
FIG. 7 is a diagram illustrating a second iteration calibration mode according to the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Thus, a feature indicated in this specification will serve to explain one of the features of one embodiment of the invention, and does not imply that every embodiment of the invention must have the stated feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.
Before describing embodiments of the present invention, two clock and calibration periods of the present invention are declared: clk (clock) is an externally provided or internally integrated high precision clock, i.e., reference clock, in this embodiment. Clk (local) is the local clock to be calibrated in this embodiment, and the common calibration target clock of the RTC is: osc32.768k internal clock (ocsp 32.768k internal clock may be understood as a typical example of clk (local)), and the basic calibration period t (cali) time span is 32 seconds, which corresponds to example OSC32.768K herein, and in other embodiments, the time span of the basic calibration period may be adjusted as needed.
The calibration period is determined according to a basic calibration period and a calibration period expansion coefficient, after the calibration period expansion coefficient is determined, the time span of the calibration period corresponds to a constant time interval, and the calibration period T (cali _ ext) = T (cali) x N (coe). The calibration period expansion coefficient N (core) also considers solving possible irregularity of the instantaneous frequency deviation of the clock CLK (local) to be calibrated while adjusting the calibration period corresponding to different calibration precision levels, so as to better obtain the error statistical average value in the proper calibration period.
The invention discloses a method for dynamically calibrating a real-time clock, which comprises the following basic steps: the method comprises the steps of monitoring and aligning phases of a reference clock and a local clock to be calibrated, obtaining a calibration period according to a period expansion coefficient and a basic calibration period, counting the local clock in each calibration period, obtaining a dynamic calibration target set, and calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
Correspondingly, the device for dynamically calibrating the real-time clock of the invention comprises: the device comprises a calibration period generation module, a frequency offset error analysis and extraction module and a calibration output module. And the calibration period generation module monitors the phases of the reference clock and the local clock and obtains a calibration period. And the frequency offset error analysis and extraction module counts the local clock in each calibration period and obtains a frequency offset error and a dynamic calibration target set. And the calibration output module calibrates the local clock according to the dynamic calibration target set of the previous calibration period.
As shown in fig. 1 and fig. 4, the calibration period generation module mainly includes three parts, namely a reference clock and local clock start phase alignment monitoring unit, a calibration period start event generation unit, and a calibration period end event generation unit.
The reference clock and local clock start phase alignment monitoring unit generates a precise check period by using the reference clock CLK (accurate), and after the reference clock CLK (accurate) starts counting, the local clock CLK (local) is started to generate the count of the error analysis corresponding counter CNT (analysis). If there is no processing of the reference clock and the local clock start phase alignment monitoring unit, the error analysis is uncertain about the start time of the count of the counter cnt (analysis), the earliest count start time may be at least one clk (accurate) delay after the calibration period is generated, the latest count start time may be at least one clk (local) delay after the calibration period is generated, clk (accurate) is an M-level clock, clk (local) is a K-level clock, both of which have a clock frequency of the order of 1000, obviously introducing an uncertain error value before entering the calibration operation. The reference clock and local clock starting phase alignment monitoring unit is an asynchronous clock phase monitoring module, and the reference clock and local clock starting phase alignment monitoring unit is used for avoiding uncertain errors caused by uncertainty of clock phases of a reference Clock (CLK) (clock) and a local Clock (CLK) (local) in consideration of the fact that in an actual circuit, the phase relationship of the high-precision reference Clock (CLK) (clock) and the local clock is random. The reference clock and local clock starting phase alignment monitoring unit can be a clock phase monitoring circuit or an asynchronous signal sampling mechanism in digital circuit design, both are a specific implementation form based on the phase alignment idea of the invention, and the introduction of an uncertain error analysis result can be avoided through the preprocessing of the reference clock and local clock starting phase alignment monitoring unit.
The calibration period starting event generating unit is used for determining the starting counting time of the reference clock CLK (clock) generating verification period and also determining the starting counting time of the local clock CLK (local) in the calibration period by the reference clock and local clock starting phase alignment monitoring unit. In a preferred embodiment, the calibration period start event generation time is the reference clock clk (accurate) to local clock clk (local) falling edge detection time, so that after the reference clock clk (accurate) generates the calibration period window, the counting operation corresponding to the error analysis of clk (local) rising edge is started immediately after 0.5 clk (local) clock period. The 0.5 clk (local) clock cycle is a deterministic count delay, which can be accounted for in the error analysis results. The calibration period window referred to herein is illustrated as "32 seconds with the base calibration period constant". If the reference clock clk (accurate) is 50M, a base calibration period of 32 seconds corresponds to an upper count limit of 50x1000x1000x32, counting based on 50M clock, the range from 0 to 50x1000x1000x32 corresponds to a "base calibration period window", and the calibration period window needs to incorporate a calibration period expansion coefficient.
The calibration CYCLE end event generating unit is configured to use the reference clock clk (accurate) as a counting start point when the calibration CYCLE start event is the calibration CYCLE start event, and assume that the total number of CYCLEs is CALI _ CYCLE _ MAX based on the total number of CYCLEs of the reference clock clk (accurate) corresponding to the calibration CYCLE T (CALI _ ext), and when the calibration CYCLE corresponding counter cnt (ref) reaches the CALI _ CYCLE _ MAX counting time, the time is defined as the calibration CYCLE end event.
The calibration period identification indication signal generation unit shown in the figure is not actually an actual hardware unit, but classifies two signals, and generates an indication signal of a corresponding calibration period span interval based on a calibration period starting event and a calibration period ending event.
As shown in fig. 2 and fig. 4, the frequency offset error analyzing and extracting module includes an error analyzing counter cnt (analysis), a local clock frequency offset error analyzing and extracting unit.
The calibration period is between the calibration period start event and the calibration period end event, the error analysis of the local clock CLK (local) takes the calibration period start event and the calibration period end event as the interval reference, and when the error analysis corresponding counter CNT (analysis) occurs at the calibration start event, the count is cleared by 0; the count is continued at step 1 before the end of calibration period event occurs. In a preferred embodiment, when the expansion coefficient n (coe) is defined as an integer value greater than 1, the error analysis counter CNT (analysis) will present a number of CYCLE counts, the number of CYCLE counts is consistent with the defined value or configuration of the calibration period expansion coefficient n (coe), the upper limit of the CYCLE count is the number of CYCLEs of the basic calibration period t (cali) corresponding to the local clock clk (local), the number of CYCLEs is defined as CNT _ CYCLE _ MAX, and the count result of the error analysis counter CNT (analysis) can be quickly associated with the error analysis result by using the CYCLE count method. After the end event of the calibration period, the error analysis counterpart counter cnt (analysis) keeps the count history until the count of the error analysis counterpart counter cnt (analysis) is cleared to 0 after the next calibration start event.
The local clock frequency offset error analysis and extraction unit extracts an error analysis result CALI _ PARA, and each updated value of the parameter of the error analysis result CALI _ PARA occurs at the time when one calibration period is finished. The error analysis result CALI _ PARA may be an average value corresponding to the calibration analysis of multiple cycles, or may be a real-time value corresponding to the calibration analysis of each cycle. In a preferred embodiment, after the end event of the calibration period occurs, the error analysis counter cnt (analysis) keeps the count history value as the error analysis result CALI _ PARA.
After the local clock frequency deviation error analysis extraction unit extracts an error analysis result CALI _ PARA, the condition of entering the automatic calibration process is that an effective calibration interval defined by the invention must be met, and for OSC with large frequency deviation error, subsequent calibration of possible inherent defects has no engineering practice significance, and the invention can provide the idea of screening OSC with crystal oscillator error exceeding the effective calibration interval. When the error analysis result CALI _ PARA exceeds the definition range of the effective calibration interval, the action of automatically calibrating the clock will not be generated, but the status information of the OSC serious error is fed back, and the information can be output in real time in the modes of status, interruption, trigger event and the like.
The dynamic calibration target set of the invention comprises: error analysis results, and one of an up-compensation calibration operation, a down-compensation calibration operation, and a compensation-less calibration operation. The parameter CFG (expect ppm max) defining the valid calibration interval. In a preferred embodiment, when the error analysis result CALI _ PARA belongs to [ CNT _ CYCLE _ MAX-CFG (expect _ ppm _ MAX), CNT _ CYCLE _ MAX ] is correspondingly subjected to the frequency-up compensation calibration operation; and when the CALI _ PARA is equal to CNT _ CYCLE _ MAX, the compensation calibration operation is not needed correspondingly.
The dynamic calibration target set is dynamic data based on the results of the error analysis for each calibration cycle or for several calibration cycles. The three compensation operations of the dynamic calibration target set are mutually exclusive within the same time interval (the same time interval corresponds to the minimum unit: e.g. a calibration period). In a special application scenario, for example, when the temperature drift of the actual operating environment of the OSC is large (the OSC needs to be calibrated at multiple ambient temperatures, i.e., normal temperature, low temperature, and high temperature, the up-conversion compensation calibration operation, the down-conversion compensation calibration operation, and the calibration operation without compensation are performed in different time intervals. To better understand the three compensation operations in the dynamic calibration target set described in this disclosure, illustrated below, T1(temperature1), T2(temperature2), and T3(temperature3) represent the time span of three consecutive calibration cycles, including three different ambient temperatures. After the end event of the calibration period of T1, T2, T3, a different compensation operation occurs in the limit case, possibly case 1: { an up-conversion compensation calibration operation, a down-conversion compensation calibration operation, and a compensation-free calibration operation }; possible case 2{ no compensation calibration operation, up-compensation calibration operation, down-compensation calibration operation }: possible case 3: { down-compensation calibration operation, up-compensation calibration operation, no-compensation calibration operation }. Under the condition that the calibration period is taken as granularity, the dynamic calibration target set defined by the invention can meet the requirements of the specific implementation of dynamic calibration.
As shown in fig. 3 and fig. 4, the calibration output module includes a local clock in-phase derivation unit, a local clock anti-phase derivation unit, and a derived clock fusion output unit.
The local clock in-phase derivation unit is used to generate an in-phase derived clock CLK _ p (derivative) signal with a duty cycle different from 50% (20% duty cycle is a preferred embodiment). The clock of the in-phase derived clock CLK _ P (derived) and the local clock CLK (local) are in-frequency and in-phase.
The local clock phase inversion derivation unit is used for generating an inversion derivation clock CLK _ N (drive) signal with a duty ratio of 50% (the duty ratio of 20% is the better embodiment); the back derived clock CLK _ N (derived) and the local clock CLK (local) are 180 DEG out of phase.
The derived clock fusion output unit is used for outputting the calibrated real-time clock according to the dynamic calibration target set.
Specifically, calibrating the local clock based on the frequency-up compensation calibration operation specifically includes: generating an in-phase derived clock with a duty cycle different from 50%, wherein the in-phase derived clock and a local clock have the same frequency and the same phase; generating an inversely derived clock with a duty cycle of not 50%, wherein the inversely derived clock and the local clock have the same frequency and are 180 degrees out of phase; defining a compensation time slot counter of the reverse derivative clock CLK _ N (derivative), wherein the maximum counting value of the compensation time slot counter is an error analysis result; and at the jumping time of each compensation time slot counter, extracting a clock of the appointed compensation time slot in the reverse derivative clock, and fusing the clock with the equidirectional derivative clock to generate a fast compensation clock as a calibrated real-time clock.
The counting range of the compensation time slot counter is monotonically increased, the maximum value is the error analysis result CALI _ PARA of the dynamic calibration target set, and the jump time of the compensation time slot counter is the fast compensation time slot defined by the invention. After the fast compensation time slot is determined, the clock pulses of the in-phase derived clock CLK _ p (derived) and the inverted derived clock CLK _ n (derived) which are the total error analysis result CALI _ PARA may be extracted, and in the above-mentioned preferred embodiment, the duty ratios of the in-phase derived clock CLK _ p (derived) and the inverted derived clock CLK _ n (derived) are 20%, which is beneficial to avoiding the situation of glitch and clock overlap in the generation process of the fast compensation clock CLK (merge _ fast).
In the sub-second level real-time clock, the application of accessing the real-time clock in continuous microsecond level is often focused, and in a preferred embodiment, the monotonically increasing counting behavior of the compensation slot counter is uniformly distributed in the whole check period, and the microsecond time of accessing the real-time clock from the application perspective is approximately equivalent to the OSC timing system with very high access precision. In the generation process of the fast compensation clock CLK (merge _ fast), the frequency is uniformly increased or flattened in the calibration period, so that the step jump problem of continuous access of sub-second time can be effectively avoided.
Calibrating the local clock based on the downconversion compensation calibration operation specifically includes: generating an in-phase derived clock with a duty cycle of not 50%, wherein the in-phase derived clock and the local clock have the same frequency and the same phase; defining a shielding time slot counter, wherein the maximum counting value of the shielding time slot counter is an error analysis result; and at the jumping moment of each shielding time slot counter, shielding the clock pulse corresponding to the in-phase derived clock, and generating a slow compensation clock as a calibrated real-time clock. In a preferred embodiment, the duty cycle of the in-phase derived clock CLK _ p (derived) is 20%, which is beneficial for avoiding glitch and clock overlap during the generation of the fast compensated clock CLK (merge _ fast).
In the generation process of the slow compensation clock CLK (merge _ slow), the calibration period is uniformly subjected to frequency reduction or flattened frequency reduction, so that the problem of rebound of continuous access of sub-second time can be avoided.
The clock switching action of the derived clock fusion output unit is based on a dynamic calibration target set (up-compensation calibration operation flag, down-compensation calibration operation flag, no-compensation calibration operation flag), and the source of the calibrated derived clock clk (cali) (also referred to as the calibrated real-time clock) includes the following three possibilities: outputting CLK (merge _ fast) when the up-conversion compensation is required; outputting CLK (merge _ slow) when the down operation compensation is required; when no clock compensation is required (no error in the local OSC), CLK (local) or CLK _ p (drive) or CLK _ n (drive) can be directly output, and in the derived clock scheme described in this invention, the three clocks are the same frequency, but differ in phase difference.
The clock switching action of the derived clock fusion output unit is based on a dynamic calibration target set (an up-conversion compensation calibration operation mark, a down-conversion compensation calibration operation mark and a compensation-free calibration operation mark), and the calibration target set corresponding to the current calibration period is registered and acts on the next calibration period to perform any one of up-conversion, down-conversion and compensation-free calibration operations. The error analysis and the calibration operation, both of which approximate to the pipeline operation task, achieve the expectation of the dynamic calibration mentioned in the invention, ensure to select the 'up-frequency compensation calibration operation' or the 'down-frequency compensation calibration operation' or the 'no compensation calibration operation' in the range of the calibration period being the granularity, and achieve the effect of dynamically calibrating the real-time clock with the calibration period being the granularity.
On the basis of dynamically calibrating the real-time clock, in a more preferred embodiment, a process of performing recalibration confirmation on the derived clock clk (cali) is further designed, that is, the derived clock feed-forward accuracy confirmation corresponds to an iterative calibration mode in the specific embodiment, as shown in fig. 6 and 7. The mode corresponding to the iterative calibration mode is a non-iterative calibration mode, as shown in fig. 5.
The method comprises the steps of confirming the front feedback precision of the derived clock, additionally adding a reference clock calibration period generating unit, additionally adding a local clock frequency offset error analyzing and extracting unit and a local clock calibration output unit, obtaining the derived clock CLK (cali) by utilizing a high-precision clock source of the reference clock CLK (accrate) and performing early calibration, and then carrying out calibration confirmation. When the corresponding dynamic calibration target set, error analysis result cai _ PARA = CNT _ CYCLE _ MAX, indicates that the derived clock Clk (CALI) has been calibrated as desired, meeting the accuracy calibration expectation. Otherwise, according to an additionally added local clock frequency offset error analysis and extraction module, a dynamic calibration target set (an ascending frequency compensation calibration operation mark and a descending frequency compensation calibration operation mark) in the module is analyzed and extracted, and the additionally added local clock calibration output module is utilized to perform corresponding ascending frequency compensation calibration operation or descending frequency compensation calibration operation.
As shown in fig. 6 and 7, the calibrated real-time clock may be used as a local clock to be calibrated to perform basic steps, that is, the phases of the reference clock and the local clock to be calibrated are monitored and aligned, a calibration period is obtained according to the period expansion coefficient and the basic calibration period, the local clock is counted in each calibration period, a dynamic calibration target set is obtained, and the local clock is calibrated according to the dynamic calibration target set of the previous calibration period. The basic steps may be repeated one or more times until the calibrated real-time clock reaches a preset calibration expectation.
The calibration clock generated in the non-iterative calibration mode is CLK (cali), and CLK (cali) is the local clock CLK (local) which generates the calibration clock after passing through the local clock frequency offset error analysis and extraction module and the local clock calibration output module.
The calibration clock generated in the iterative calibration mode is CLK (cali-fix), the CLK (cali-fix) defines CLK (cali) as a real-time clock to be calibrated, and the iterative calibration clock is generated after the CLK (cali) is processed by an additionally added reference clock calibration period generation module, an additional local clock frequency offset error analysis and extraction module and an additional local clock calibration output module.
The iteration frequency of the calibration clock generated in the iterative calibration mode is not limited to 1 time, and can also be expanded to multiple times, and the number of the reference clock calibration period generation module, the local clock frequency offset error analysis extraction module and the local clock calibration output module needs to be correspondingly increased after the iteration is performed for multiple times. According to the method, the local clock CLK (local) to be calibrated is subjected to calibration precision confirmation or secondary calibration by using an iterative calibration mode, CLK (cali-fix), CLK (cali-fix2) and CLK (cali-fix3) are derived, and the precision calibration expectation of the local clock CLK (local) can be approached.
Because the invention adopts hardware to realize dynamic iteration, the CLK (cali) of the Nth calibration period and the CLK (cali-fix) of the (N-1) th calibration period can be processed in parallel, and N is more than 1. The CLK (cali) of the Nth calibration period, the CLK (cali-fix) of the (N-1) th calibration period and the CLK (cali-fix2) of the (N-2) th calibration period can be processed in parallel, N is larger than 2, and so on, on the basis of realizing dynamic iteration, the calibration of the real-time clock can still meet the delay time requirement of a user.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (14)
1. A method of dynamically calibrating a real time clock, comprising:
step 1, monitoring and aligning phases of a reference clock and a local clock to be calibrated, and obtaining a calibration period according to a period expansion coefficient and a basic calibration period;
step 2, counting the local clock in each calibration period, and obtaining a dynamic calibration target set;
and 3, calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
2. A method of dynamically calibrating a real-time clock as recited in claim 1, wherein the start of the calibration period is the time of detection of a falling edge of the local clock by the reference clock.
3. The method of dynamically calibrating a real-time clock according to claim 1, wherein said set of dynamic calibration targets comprises: error analysis results, and one of an up-compensation calibration operation, a down-compensation calibration operation, and a compensation-less calibration operation.
4. The method of dynamically calibrating a real-time clock as defined in claim 3, wherein calibrating the local clock based on the up-compensation calibration operation specifically comprises:
generating an in-phase derived clock with a duty cycle different from 50%, wherein the in-phase derived clock and a local clock have the same frequency and the same phase;
generating an inversely derived clock with a duty cycle of not 50%, wherein the inversely derived clock and the local clock have the same frequency and are 180 degrees out of phase;
defining a compensation time slot counter, wherein the maximum counting value of the compensation time slot counter is the error analysis result;
and at the jumping time of each compensation time slot counter, extracting a clock of the appointed compensation time slot in the reverse derivative clock, and fusing the clock with the equidirectional derivative clock to generate a fast compensation clock serving as a calibrated real-time clock.
5. The method of dynamically calibrating a real-time clock as defined in claim 3, wherein calibrating the local clock based on the downconversion compensation calibration operation specifically comprises:
generating an in-phase derived clock with a duty cycle different from 50%, wherein the in-phase derived clock and a local clock have the same frequency and the same phase;
defining a shielding time slot counter, wherein the maximum counting value of the shielding time slot counter is the error analysis result;
and at the jumping moment of each shielding time slot counter, shielding the clock pulse corresponding to the in-phase derived clock, and generating a slow compensation clock as a calibrated real-time clock.
6. A method of dynamically calibrating a real-time clock as defined in claim 4, wherein said in-phase derived clock has a duty cycle of 20%.
7. The method for dynamically calibrating a real-time clock according to claim 5, wherein said inversely derived clock has a duty cycle of 20%.
8. A method for dynamically calibrating a real-time clock as claimed in claim 4 or 5, wherein said steps 1 to 3 are performed with the calibrated real-time clock as the local clock to be calibrated again until the calibrated real-time clock reaches a preset calibration expectation.
9. A method of dynamically calibrating a real-time clock as recited in claim 3, wherein the error analysis results in an average value corresponding to a plurality of calibration cycle calibration analyses or a real-time value corresponding to each calibration cycle calibration analysis.
10. A method for dynamically calibrating a real-time clock as defined in claim 3, wherein in step 3, the local clock is calibrated only when the error analysis result satisfies the valid calibration interval.
11. An apparatus for dynamically calibrating a real-time clock, comprising a reference clock and a local clock to be calibrated, wherein the local clock is dynamically calibrated using the method of any one of claims 1 to 10, further comprising:
the calibration period generation module is used for monitoring the phases of the reference clock and the local clock and obtaining a calibration period;
the frequency offset error analysis and extraction module counts the local clock in each calibration period and obtains a frequency offset error and a dynamic calibration target set;
and the calibration output module is used for calibrating the local clock according to the dynamic calibration target set of the previous calibration period.
12. The apparatus for dynamically calibrating a real-time clock according to claim 11, wherein said calibration period generation module comprises: the device comprises a reference clock and local clock starting phase alignment monitoring unit, a calibration period starting event generating unit and a calibration period ending event generating unit.
13. The apparatus for dynamically calibrating a real-time clock as defined in claim 11, wherein said frequency offset error analysis extraction module comprises: the error analysis corresponds to the counter CNT (analysis), the local clock frequency deviation error analysis extraction unit.
14. The apparatus for dynamically calibrating a real-time clock according to claim 11, wherein said calibration output module comprises: the local clock fusion output unit comprises a local clock in-phase derivation unit, a local clock anti-phase derivation unit and a derivation clock fusion output unit.
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