CN114430253B - Signal amplification circuit - Google Patents
Signal amplification circuit Download PDFInfo
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- CN114430253B CN114430253B CN202210104090.3A CN202210104090A CN114430253B CN 114430253 B CN114430253 B CN 114430253B CN 202210104090 A CN202210104090 A CN 202210104090A CN 114430253 B CN114430253 B CN 114430253B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application discloses a signal amplification circuit, which comprises an amplification unit and a bias current source, wherein the bias current source is set to be a nanoamp level; one end of the bias current source is connected with the bias current input end of the amplifying unit, and the other end of the bias current source is grounded; the amplifying unit is used for acquiring the bias current of the nano-ampere level through the bias current input end and determining an amplified working point according to the bias current of the nano-ampere level so as to maintain the working state of the amplifying unit. The method and the device can work in an ultra-low power consumption state.
Description
Technical Field
The present application relates to the field of electronic circuit technology, and in particular, to a signal amplification circuit.
Background
As a key module of an analog signal processing circuit, an analog signal amplifier is widely applied to a voice recognition sensor, augmented reality and virtual reality equipment, an intelligent household appliance, a wearable medical sensor and the like due to the characteristics of low power consumption and low noise. In the application scene of the internet of things, an analog signal amplifier amplifies weak analog signals such as voice, vision, bioelectric signals and the like in the environment by the signal amplitude, the amplification factor is usually 100-1000 times, and the amplified analog signals are converted into digital signals through a high-precision analog-to-digital converter, can be used for various signal processing and analysis in a digital domain, and are transmitted to an external terminal processor in a wired or wireless mode. Although existing internet of things devices can already handle various tasks in a practical scenario, in order to further increase the endurance time of the internet of things devices, the power consumption needs to be further reduced, which poses a great challenge to the design of analog signal amplifiers.
Disclosure of Invention
In view of the above technical problem, the present application provides a signal amplification circuit capable of operating in an ultra-low power consumption state.
The embodiment of the application provides a signal amplification circuit, which comprises an amplification unit and a bias current source, wherein the bias current is set to be a nano-ampere level;
one end of the bias current source is connected with the bias current input end of the amplifying unit, and the other end of the bias current source is grounded;
the amplifying unit is used for acquiring the bias current of the nano-ampere level through the bias current input end and determining an amplified working point according to the bias current of the nano-ampere level so as to maintain the working state of the amplifying unit.
Optionally, the amplifying unit comprises a first amplifying subunit and a second amplifying subunit;
the first end of the first amplification subunit and the first end of the second amplification subunit are both used for inputting analog signals;
the second end of the first amplification subunit and the second end of the second amplification subunit are both used for outputting amplified signals obtained by amplifying the analog signals;
the third end of the first amplification subunit and the third end of the second amplification subunit are connected and used as power supply voltage input ends;
and the fourth end of the first amplification subunit and the fourth end of the second amplification subunit are connected and used as the bias current input end.
Optionally, the first amplification subunit includes a first N-type field effect transistor and a first P-type field effect transistor, and the second amplification subunit includes a second N-type field effect transistor and a second P-type field effect transistor:
the grid electrode of the first N-type field effect transistor is connected with the grid electrode of the first P-type field effect transistor and is used as the first end of the first amplification subunit; the grid electrode of the second N-type field effect transistor is connected with the grid electrode of the second P-type field effect transistor and serves as the first end of the second amplification subunit;
the drain electrode of the first N-type field effect transistor is connected with the drain electrode of the first P-type field effect transistor and serves as a second end of the first amplification subunit; the drain electrode of the second N-type field effect transistor is connected with the drain electrode of the second P-type field effect transistor to serve as a second end of the second amplification subunit;
the source electrode of the first P-type field effect transistor is the third end of the first amplification subunit, and the source electrode of the second P-type field effect transistor is the third end of the second amplification subunit;
the source electrode of the first N-type field effect transistor is the fourth end of the first amplification subunit, and the source electrode of the second N-type field effect transistor is the fourth end of the second amplification subunit.
Optionally, the width-to-length ratios of the first N-type field effect transistor and the second N-type field effect transistor are both a first preset value, and the width-to-length ratios of the first P-type field effect transistor and the second P-type field effect transistor are both a second preset value.
Optionally, the signal amplification circuit comprises a regulation unit;
the first end of the regulating unit is used for inputting working voltage, the second end of the regulating unit is connected with the power supply voltage input end, and the third end of the regulating unit is used for inputting bias voltage.
Optionally, the adjusting unit is a third P-type field effect transistor;
the source electrode of the third P-type field effect transistor is the first end of the adjusting unit, the grid electrode of the third P-type field effect transistor is the third end of the adjusting unit, and the drain electrode of the third P-type field effect transistor is the second end of the adjusting unit.
Optionally, the signal amplification circuit includes a first resistor, a second resistor, a first capacitor, and a second capacitor;
one end of the first resistor is connected with the first end of the first amplification subunit, and the other end of the first resistor is connected with the second end of the first amplification subunit;
one end of the second resistor is connected with the first end of the second amplification subunit, and the other end of the second resistor is connected with the second end of the second amplification subunit;
one end of the first capacitor is connected with the first end of the first amplification subunit, and the other end of the first capacitor is connected with the second end of the first amplification subunit;
one end of the second capacitor is connected with the first end of the second amplification subunit, and the other end of the second capacitor is connected with the second end of the second amplification subunit.
Optionally, the signal amplification circuit includes a first switch unit, a second switch unit, and a detection unit;
the first end of the first switch unit is connected with the first end of the first amplification subunit, the second end of the first switch unit is connected with the second end of the first amplification subunit, the third end of the first switch unit is connected with the first output end of the detection unit, and the first switch unit and the second switch unit form a path when the third end of the first switch unit receives an abnormal control signal, and input a first common mode voltage through the fourth end of the first switch unit, and output the first common mode voltage from the first end of the first switch unit and the second end of the first switch unit;
the first end of the second switch unit is connected with the first end of the second amplification subunit, the second end of the second switch unit is connected with the second end of the second amplification subunit, the third end of the second switch unit is connected with the second output end of the detection unit, and the second switch unit is used for forming a path with the second end of the second switch unit when the third end of the second switch unit receives an abnormal control signal, inputting a second common-mode voltage through the fourth end of the second switch unit, and outputting the second common-mode voltage from the first end of the second switch unit and the second end of the second switch unit;
the first input end of the detection unit is connected with the second end of the first amplification subunit, the second input end of the detection unit is connected with the second end of the second amplification subunit, and the detection unit is used for outputting an abnormal control signal or a normal control signal through the first output end of the detection unit and the second output end of the detection unit according to an amplification signal obtained from the first input end of the detection unit and the second input end of the detection unit.
Optionally, the first switching unit includes a first switching subunit, a second switching subunit, a third switching subunit, and a fourth switching subunit;
the first end of the first switch subunit, the first end of the second switch subunit and the first end of the third switch subunit are connected with the first end of the fourth switch subunit and serve as the fourth end of the first switch unit;
the second end of the first switch subunit is connected with the second end of the second switch subunit and serves as the first end of the first switch unit;
the second end of the third switch subunit is connected with the second end of the fourth switch subunit and is used as the second end of the first switch subunit;
and the control end of the first switch subunit, the control end of the second switch subunit, the control end of the third switch subunit and the control end of the fourth switch subunit are the third end of the first switch unit.
Optionally, the first switch subunit and the third switch subunit are both N-type field effect transistors, and the second switch subunit and the fourth switch subunit are both P-type field effect transistors.
Optionally, the second switch unit includes a fifth switch subunit, a sixth switch subunit, a seventh switch subunit, and an eighth switch subunit;
the first end of the fifth switch subunit, the first end of the sixth switch subunit and the first end of the seventh switch subunit are connected with the first end of the eighth switch subunit and serve as the fourth end of the second switch unit;
the second end of the fifth switch subunit is connected with the second end of the sixth switch subunit and serves as the first end of the second switch unit;
the second end of the seventh switch subunit is connected with the second end of the eighth switch subunit and serves as the second end of the second switch unit;
and the control end of the fifth switch subunit, the control end of the sixth switch subunit, the control end of the seventh switch subunit and the control end of the eighth switch subunit are the third end of the second switch unit.
Optionally, the fifth switch subunit and the seventh switch subunit are both N-type field effect transistors, and the sixth switch subunit and the eighth switch subunit are both P-type field effect transistors.
Optionally, the detection unit includes a first subtraction unit, a second subtraction unit, a first comparison unit, a second comparison unit, a logic unit, and a trigger unit;
the first input end of the first subtraction unit is the first input end of the detection unit, the output end of the first subtraction unit is connected with the first input end of the first comparison unit, and the first subtraction unit is used for subtracting a first preset voltage input through the second input end of the first subtraction unit from a voltage value of the inverted analog signal input through the first input end of the first subtraction unit, and outputting an obtained first difference value through the output end of the first subtraction unit;
the first input end of the second subtraction unit is the second input end of the detection unit, the output end of the second subtraction unit is connected with the first input end of the second comparison unit, and the second subtraction unit is used for subtracting a second preset voltage input through the second input end of the second subtraction unit from the voltage value of the positive-phase analog signal input through the first input end of the second subtraction unit, and outputting an obtained second difference value through the output end of the second subtraction unit;
the second input end of the first comparing unit is the second input end of the detecting unit, the output end of the first comparing unit is connected with the first input end of the logic unit, and the first comparing unit is used for comparing the first difference value with the voltage value of the normal-phase analog signal input by the second input end of the first comparing unit and outputting a first comparing result through the output end of the first comparing unit;
a second input end of the second comparing unit is a first input end of the detecting unit, an output end of the second comparing unit is connected with a second input end of the logic unit, and the second comparing unit is used for comparing the second difference value with a voltage value of an inverted analog signal input by the second input end of the second comparing unit and outputting a second comparison result through an output end of the second comparing unit;
the output end of the logic unit is connected with the input end of the trigger unit and is used for carrying out logic judgment according to the first comparison result and the second comparison result and outputting the judgment result through the output end of the logic unit;
the output end of the trigger unit is divided into a first output end of the detection unit and a second output end of the detection unit, and is used for generating a normal control signal or an abnormal control signal according to the judgment result and outputting the normal control signal or the abnormal control signal through the output end of the trigger unit.
Optionally, the logic unit is an or gate logic circuit.
Optionally, the trigger unit is a shift register composed of a plurality of D flip-flops.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the signal amplification circuit provided by the embodiment of the application comprises an amplification unit and a bias current source with a bias current set to be a nano-ampere level; one end of the bias current source is connected with the bias current input end of the amplifying unit, and the other end of the bias current source is grounded; the amplifying unit is used for obtaining the bias current of the nano-ampere level through the bias current input end, and determining an amplified working point according to the bias current of the nano-ampere level so as to maintain the working state of the amplifying unit. Therefore, the bias current source provides a nano-ampere level bias current to the amplifying unit, so that the amplifying unit amplifies the analog signal input to the amplifying unit in the working state of the nano-ampere level bias current. The existing analog signal amplifier needs microampere-level or even milliamp-level bias current, the signal amplification circuit of the application can enable the amplification unit to be in a working state only by the nanoamp-level bias current, and compared with the existing analog signal amplifier, the signal amplification circuit of the application needs smaller bias current, so that the power consumption is lower.
Drawings
Fig. 1 is a schematic diagram of a first structure of a signal amplification circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of an amplifying unit provided in an embodiment of the present application;
fig. 3 is a schematic diagram of a second structure of a signal amplifying circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a third structure of a signal amplifying circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a first switch unit provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a second switch unit provided in an embodiment of the present application;
FIG. 7 is a schematic structural diagram of a detection unit provided in an embodiment of the present application;
1000, a bias current source; 1100. an amplifying unit; 1110. a first amplification subunit; 1120. a second amplification subunit; 1111. a first P-type field effect transistor; 1112. a first N-type field effect transistor; 1121. a second P-type field effect transistor; 1122. a second N-type field effect transistor; 1130. an adjustment unit; 1131. a third P-type field effect transistor; 1201. a first resistor; 1202. a second resistor; 1203. a first capacitor; 1204. a second capacitor; 1310. a first switch unit; 1320. a second switching unit; 1311. a first switch subunit; 1312. a second switch subunit; 1313. a third switch subunit, 1314, a fourth switch subunit; 1321. a fifth switch subunit; 1322. a sixth switch subunit; 1323. a seventh switch subunit; 1324. an eighth switch subunit; 1410. a detection unit; 1411. a first subtraction unit; 1412. a second subtraction unit; 1421. a first comparing unit; 1422. a second comparing unit; 1430. a logic unit; 1440. and a trigger unit.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of a first structure of a signal amplifying circuit according to an embodiment of the present disclosure. The signal amplifying circuit includes an amplifying unit 1100, and a bias current source 1000 whose bias current is set to nano-ampere level; one end of the bias current source 1000 is connected to the bias current input terminal of the amplifying unit 1100, and the other end of the bias current source 1000 is grounded; it is understood that the bias current source 1000 with the bias current set to be nano-ampere level refers to the bias current source 1000 only providing the bias current of 0nA to 1000nA, so the bias current source 1000 of the present application can provide the nano-ampere level bias current with different values, such as 100nA, 255nA, 400nA, 550nA, 700nA, not to mention here.
Preferably, the bias current source 1000 provides a bias current of 400 nanoamperes to 700 nanoamperes.
It is understood that when the bias current is less than 400 nanoamperes, the bias current is too small to function adequately; when the bias current is larger than 700 nanoamperes, although the bias effect can be exerted, the power consumption is improved at the same time. Accordingly, the bias current source 1000 supplies a bias current of 400 nanoamperes to 700 nanoamperes, and power consumption can be reduced while supplying a normal bias current to the amplification unit 1100.
The amplifying unit 1100 is configured to obtain a nano-ampere bias current through the bias current input terminal, and determine an amplified operating point according to the nano-ampere bias current to maintain an operating state thereof.
In this embodiment, after obtaining the dc voltage and the nano-ampere level bias current provided by the bias current source 1000, the amplifying unit 1100 determines an amplifying operating point according to the nano-ampere level bias current to amplify the analog signal input to the amplifying unit 1100, and the amplified analog signal is output by the amplifying unit 1100. The amplifying unit 1100 of this embodiment may be a first-stage amplifying circuit, a second-stage amplifying circuit, or a multi-stage amplifying circuit with more than three stages, but the circuit architecture of the amplifying unit 1100 of this embodiment of the present application adopts a first-stage amplifying circuit, which is beneficial to reducing electronic devices in the circuit, and avoiding more electronic devices from causing higher energy consumption, thereby reducing the power consumption of the whole circuit.
It will be appreciated that a disadvantage of the prior art analog signal amplifier is that a bias current in the order of microamperes or even milliamps is required. The characteristic of high power consumption current of this level limits the application prospect of the existing analog signal amplifier in a low-power consumption internet of things system or a wearable device. However, the bias current source 1000 of the present embodiment provides a nano-ampere bias current to the amplifying unit 1100, so that the amplifying unit 1100 amplifies the analog signal input to the amplifying unit 1100 in the operating state of the nano-ampere bias current. Compared with the prior analog signal amplifier which needs microampere-level or even milliamp-level bias current, the signal amplification circuit of the application can enable the amplification unit 1100 to be in a working state only needing nanoamp-level bias current, so that the signal amplification circuit of the application needs smaller bias current and has lower power consumption.
In one embodiment, the amplification unit 1100 includes a first amplification subunit 1110 and a second amplification subunit 1120; the first end of the first amplification subunit 1110 and the first end of the second amplification subunit 1120 are both used for inputting analog signals; the second end of the first amplifying subunit 1110 and the second end of the second amplifying subunit 1120 are both configured to output the amplified signal of the analog signal after amplification; the third terminal of the first amplification subunit 1110 and the third terminal of the second amplification subunit 1120 are connected to each other and serve as a power supply voltage input terminal; the fourth terminal of the first amplification subunit 1110 and the fourth terminal of the second amplification subunit 1120 are connected and used as the bias current input terminal.
In this embodiment, when the input analog signals include a first input signal Vinp and a second input signal Vinn, the first input signal Vinp is transmitted from the first terminal of the first amplification subunit 1110 to the first amplification subunit 1110, and after being amplified by the first amplification subunit 1110, a first output signal Voutn is output from the second terminal of the first amplification subunit 1110; the second input signal Vinn is transmitted from the first end of the second amplifying sub-unit 1120 to the second amplifying sub-unit 1120, and after being amplified by the second amplifying sub-unit 1120, the second output signal Voutp is output from the second analog signal output end.
It is understood that the first amplification sub-unit 1110 and the second amplification sub-unit 1120 of the present embodiment enable the signal amplification circuit to process analog signals with a positive phase signal and a negative phase signal in parallel, thereby improving the signal processing capability of the signal amplification circuit, and the signal amplification circuit receives and amplifies different types of analog signals, thereby improving the compatibility of the signal amplification circuit with respect to various analog signals.
In one embodiment, the first amplification subunit 1110 and the second amplification subunit 1120 are both transistor pair transistors, the first amplification subunit 1110 is a first transistor pair transistor, and the second amplification subunit 1120 is a second transistor pair transistor, so that the circuit architectures of the first amplification subunit 1110 and the second amplification subunit 1120 in the embodiment of the present application are both one-stage amplification circuits, which is beneficial to reducing electronic devices in the circuits, and avoiding higher energy consumption caused by more electronic devices, thereby reducing the power consumption of the entire circuit.
Optionally, the first amplifying subunit 1110 includes a first NPN transistor and a first PNP transistor, and the second amplifying subunit 1120 includes a second NPN transistor and a second PNP transistor.
The gate of the first NPN transistor is connected to the gate of the first PNP transistor, and serves as the first end of the first amplification subunit 1110; the gate of the second NPN transistor is connected to the gate of the second PNP transistor and serves as the first end of the second amplification subunit 1120.
The drain of the first NPN transistor is connected to the drain of the first PNP transistor, and serves as the second end of the first amplification subunit 1110; the drain of the second NPN transistor is connected to the drain of the second PNP transistor, which serves as the second terminal of the second amplification subunit 1120.
The source of the first PNP transistor is the third terminal of the first amplification sub-unit 1110, and the source of the second PNP transistor is the third terminal of the second amplification sub-unit 1120. The source of the first NPN transistor is the fourth terminal of the first amplification subunit 1110, and the source of the second NPN transistor is the fourth terminal of the second amplification subunit 1120.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an amplifying unit 1100 according to an embodiment of the present disclosure.
Optionally, the first amplification sub-unit 1110 includes a first N-type fet 1112 and a first P-type fet 1111, and the second amplification sub-unit 1120 includes a second N-type fet 1122 and a second P-type fet 1121.
The gate of the first N-fet 1112 is connected to the gate of the first P-fet 1111 and serves as the first terminal of the first amplification subunit 1110; the gate of the second N-fet 1122 is connected to the gate of the second P-fet 1121 and serves as the first terminal of the second amplifier sub-unit 1120.
The drain of the first N-fet 1112 is connected to the drain of the first P-fet 1111 and serves as the second terminal of the first amplifier subunit 1110; the drain of the second N-fet 1122 is connected to the drain of the second P-fet 1121 to serve as the second terminal of the second amplifier subunit 1120.
The source of the first pfet 1111 is the third terminal of the first amplifier subunit 1110, and the source of the second pfet 1121 is the third terminal of the second amplifier subunit 1120; the source of the first N-fet 1112 is the fourth terminal of the first amplifier sub-unit 1110, and the source of the second N-fet 1122 is the fourth terminal of the second amplifier sub-unit 1120.
In the present embodiment, the width-to-length ratios of the first N-type fet 1112 and the second N-type fet 1122 are both a first predetermined value, and the width-to-length ratios of the first P-type fet 1111 and the second P-type fet 1121 are both a second predetermined value.
It is understood that the present application provides various embodiments of the first N-fet 1112, the second N-fet 1122, the first P-fet 1111, and the second P-fet 1121 with different aspect ratios, for example, the aspect ratios of the first N-fet 1112 and the second N-fet 1122 are both 250, and the aspect ratios of the first P-fet 1111 and the second P-fet 1121 are both 150; alternatively, the width-to-length ratios of the first N-type fet 1112 and the second N-type fet 1122 are both 80, and the width-to-length ratios of the first P-type fet 1111 and the second P-type fet 1121 are both 180. Various embodiments are not listed here. In this embodiment, the first N-fet 1112, the second N-fet 1122, the first P-fet 1111, and the second P-fet 1121 with different aspect ratios are all in the sub-threshold state.
It can be understood that after the first input signal Vinp and the second input signal Vinn are amplified by the first amplifying sub-unit 1110 and the second amplifying sub-unit 1120, the corresponding output second output signal Voutp and first output signal Voutn may have a large amplitude difference.
In one embodiment, the signal amplification circuit includes a conditioning unit 1130; a first terminal of the adjusting unit 1130 is used for inputting a working voltage, a second terminal of the adjusting unit 1130 is connected to the power voltage input terminal, and a third terminal of the adjusting unit 1130 is used for inputting a bias voltage.
It can be understood that the adjusting unit 1130 of the embodiment of the present application is used for adjusting the common-mode voltage of the amplified analog signal, so that the common-mode voltage of the amplified analog signal is more stable, and the large difference between the amplitude of the second output signal Voutp and the amplitude of the first output signal Voutn is eliminated.
In this embodiment, the adjusting unit 1130 is a transistor, and the adjusting unit 1130 may be a transistor or a MOS transistor.
Optionally, in an embodiment, the adjusting unit 1130 is a third P-type fet 1131; the source of the third P-type fet 1131 is the first end of the regulating unit 1130, the gate of the third P-type fet 1131 is the third end of the regulating unit 1130, and the drain of the third P-type fet 1131 is the second end of the regulating unit 1130.
In this embodiment, a bias voltage Vcm from the outside is inputted from the gate of the third pfet 1131 to control the switch of the third pfet 1131 according to the bias voltage Vcm, thereby controlling the opening or closing of the path between the source and the drain. The magnitude of the dc voltage input from the source of the third pfet 1131 is controlled through the path between the source and the drain, and the common mode voltage of the amplified analog signal is adjusted by using the dc voltage, so as to adjust the amplitude of the second output signal Voutp and the amplitude of the first output signal Voutn, thereby stabilizing the amplified analog signal.
It can be understood that after the first input signal Vinp and the second input signal Vinn are amplified by the first amplifying sub-unit 1110 and the second amplifying sub-unit 1120, respectively, it is possible to amplify the input noise of the first input signal Vinp and the second input signal Vinn, thereby reducing the signal-to-noise ratio of the amplified second output signal Voutp and the first output signal Voutn.
Input noise of the signal amplification circuit of the present embodiment
Can be expressed by equation (1):
wherein, g m Is the transconductance value of the transistor pair; WL is the size of the transistor pair; f is the operating frequency of the signal amplification circuit. As shown in equation (1), noise is input
Mainly comprises thermal noise and flicker noise of the transistor pair; wherein the first term->
For thermal noise, the second term->
Is flicker noise.
First, according to the characteristics of the thermal noise of the transistor, the noise power spectrum thereof is uniformly distributed in the entire frequency domain, and the bandwidth of the signal amplifying circuit of the present embodiment is designed to be 100 to 10kHz. By limiting the maximum bandwidth to 10kHz without affecting the bandwidth of the speech input signal, the effect of thermal noise in the high frequency range above 10kHz is greatly reduced. Meanwhile, thanks to the amplifying unit 1100 of the embodiment, the transconductance value gm of the signal amplifying circuit is greatly increased, and according to the formula (1), the increase of the transconductance value gm can effectively reduce the influence caused by the thermal noise.
Second, according to the characteristics of the transistor flicker noise, the noise power spectrum distribution thereof increases with the decrease of the frequency f, and the transistor flicker noise is a dominant noise in the low frequency range.
Referring to fig. 3, fig. 3 is a schematic diagram of a second structure of a signal amplifying circuit according to an embodiment of the present disclosure.
In one embodiment, the signal amplification circuit of the present embodiment includes a first resistor 1201, a second resistor 1202, a first capacitor 1203, and a second capacitor 1204; one end of the first resistor 1201 is connected to the first end of the first amplification subunit 1110, and the other end of the first resistor 1201 is connected to the second end of the first amplification subunit 1110; one end of the second resistor 1202 is connected to a first end of the second amplifying subunit 1120, and the other end of the second resistor 1202 is connected to a second end of the second amplifying subunit 1120; one end of the first capacitor 1203 is connected to the first end of the first amplification sub-unit 1110, and the other end of the first capacitor 1203 is connected to the second end of the first amplification sub-unit 1110; one end of the second capacitor 1204 is connected to the first end of the second amplifying sub-unit 1120, and the other end of the second capacitor 1204 is connected to the second end of the second amplifying sub-unit 1120.
In this embodiment, the first resistor 1201, the second resistor 1202, the first capacitor 1203 and the second capacitor 1204 form a 100Hz high-pass filter, so that the flicker noise with a low frequency less than 100Hz can be suppressed, and the influence caused by the flicker noise of the transistor can be reduced.
Optionally, a first terminal of the first amplification subunit 1110 is connected to one terminal of a third capacitor, and the other terminal of the third capacitor is used for inputting the first input signal Vinp; a first end of the second amplifying subunit 1120 is connected to one end of a fourth capacitor, and the other end of the fourth capacitor is used for inputting a second input signal Vinn.
It can be understood that, according to the formula (1), the influence of flicker noise can be effectively reduced by increasing the size of the transistor pair. Therefore, the transistor size of the analog signal amplifying circuit according to the present invention is optimally designed based on the circuit area and the input noise requirement.
Preferably, in an embodiment, the width-to-length ratios of the first N-type fet 1112 and the second N-type fet 1122 are both 160, and the width-to-length ratios of the first P-type fet 1111 and the second P-type fet 1121 are both 360.
In the present embodiment, since the bias current is at nanoamp level, the gate voltages Vgs of the first N-type fet 1112 and the second N-type fet 1122 are approximately equal to the threshold voltage VT, and the gate voltages Vgs of the first P-type fet 1111 and the second P-type fet 1121 are approximately equal to the threshold voltage VT, so that the first N-type fet 1112, the second N-type fet 1122, the first P-type fet 1111, and the second P-type fet 1121 all operate at sub-threshold state. The first amplification subunit 1110 formed by the first N-type fet 1112 and the first P-type fet 1111, and the second amplification subunit 1120 formed by the second N-type fet 1122 and the second P-type fet 1121 greatly improve the input noise efficiency coefficient NEF and the transconductance value gm of the signal amplification circuit, and provide a sufficient open-loop gain (open-loop gain) for the signal amplification circuit, the open-loop gain being 30-40dB, and the signal amplification circuit being capable of providing the maximum closed-loop gain required by the chip application in the closed-loop connection state, the maximum closed-loop gain being 20dB.
Under the working state of the nanoamp-level bias current, the root mean square RMS input noise of the conventional signal amplifier is greatly improved to reach 10-20 microvolts, so that the signal to noise ratio is greatly reduced, and the perception accuracy of weak analog signals such as voice, vision, bioelectric signals and the like is reduced. Different from the existing signal amplifier, the signal amplification circuit of the embodiment optimizes the size of the transistor based on the advanced 55 nm manufacturing process, and is also configured with a 100Hz high-pass filter and a maximum bandwidth limit of 10kHz, so that the power consumption of the signal amplification circuit of the embodiment is reduced to a nano watt level, and simultaneously, the RMS (root mean square) input noise of less than 7 microvolts is realized in a frequency domain of 100 to 10kHz.
It is understood that, in the above embodiment, in order to implement low-frequency-domain high-pass filtering, the impedances of the first resistor 1201 and the second resistor 1202 are very large, and reach 50-500G Ω, and the capacitance values of the first capacitor 1203 and the second capacitor 1204 are picofarad, when the input terminal VIP and the input terminal VIN of the signal amplifying circuit are stepped, the signal amplifying circuit starts to enter a step response, and the power-on setup time thereof is determined by the time constants of the first resistor 1201, the second resistor 1202, the first capacitor 1203 and the second capacitor 1204:
τ＝CR AC (2)
wherein τ represents a time constant, R AC A resistance value of the first resistor 1201 and a resistance value of the second resistor 1202 are indicated, and C indicates capacitance values of the first capacitor 1203 and the second capacitor 1204.
The calculation of equation (2) can be used to obtain that the power-on setup time of the above embodiment is greatly increased, and the response time for dealing with the input abnormality is also longer, which may cause the power-on operation delay of the related product to be too long, and greatly affect the user experience.
In order to solve the above technical problem, the present application provides an embodiment, in which a signal amplification circuit of the present embodiment includes an amplification unit 1100, a bias current source 1000 with a bias current set to a nano-ampere level, a switch unit, and a detection unit 1410; one end of the bias current source 1000 is connected to the bias current input terminal of the amplifying unit 1100, and the other end of the bias current source 1000 is grounded.
The amplifying unit 1100 is configured to obtain a bias current of a nanoamp level through the bias current input terminal, and determine an amplified operating point according to the bias current of the nanoamp level to maintain an operating state thereof.
The input end of the detecting unit 1410 is connected to the output end of the amplifying unit 1100, and the output end of the detecting unit 1410 is connected to the control end of the switch unit, and is configured to output an abnormal control signal or a normal control signal to the switch unit according to the amplified signal output by the output end of the amplifying unit 1100.
The first end of the switch unit is connected to the input end of the amplifying unit 1100, and the second end of the switch unit is connected to the output end of the amplifying unit 1100, so that when the control end of the switch unit receives an abnormal control signal, the first end of the switch unit and the second end of the switch unit form a path, and a common mode voltage is input through the fourth end of the switch unit, and the common mode voltage is output from the first end of the switch unit and the second end of the switch unit.
It can be understood that the switch unit can assist the amplifying unit 1100 to quickly power up and restore to normal by providing a common mode voltage to the input signal and the output signal of the amplifying unit 1100, thereby greatly reducing the power-up setup time and the abnormal response time.
Referring to fig. 4, fig. 4 is a schematic diagram of a third structure of a signal amplifying circuit according to an embodiment of the present disclosure.
Optionally, in an embodiment, the signal amplifying circuit includes a first switching unit 1310, a second switching unit 1320, and a detecting unit 1410.
The first terminal of the first switch unit 1310 is connected to the first terminal of the first amplification subunit 1110, the second terminal of the first switch unit 1310 is connected to the second terminal of the first amplification subunit 1110, the third terminal of the first switch unit 1310 is connected to the first output terminal of the detection unit 1410, when the third terminal of the first switch unit 1310 receives an abnormal control signal, the first terminal of the first switch unit 1310 and the second terminal of the first switch unit 1310 form a path, a first common mode voltage is input through the fourth terminal of the first switch unit 1310, and the first common mode voltage is output from the first terminal of the first switch unit 1310 and the second terminal of the first switch unit 1310.
A first terminal of the second switching unit 1320 is connected to the first terminal of the second amplifying subunit 1120, a second terminal of the second switching unit 1320 is connected to the second terminal of the second amplifying subunit 1120, a third terminal of the second switching unit 1320 is connected to the second output terminal of the detecting unit 1410, and when the third terminal of the second switching unit 1320 receives an abnormal control signal, the first terminal of the second switching unit 1320 and the second terminal of the second switching unit 1320 form a path, a second common mode voltage is input through the fourth terminal of the second switching unit 1320, and the second common mode voltage is output from the first terminal of the second switching unit 1320 and the second terminal of the second switching unit 1320.
A first input end of the detection unit 1410 is connected to the second end of the first amplification subunit 1110, a second input end of the detection unit 1410 is connected to the second end of the second amplification subunit 1120, and the detection unit is configured to output an abnormal control signal or a normal control signal through a first output end of the detection unit 1410 and a second output end of the detection unit 1410 according to the amplification signals acquired from the first input end of the detection unit 1410 and the second input end of the detection unit 1410.
In the present embodiment, the detecting unit 1410 is driven by a low frequency digital clock signal CLK to monitor the second output signal Voutp and the first output signal Voutn in real time. Detecting whether the second output signal Voutp and the first output signal Voutn are in an abnormal state, wherein when the amplifying unit 1100 is in a power-on state or input is abnormal, the second output signal Voutp and the first output signal Voutn output by the amplifying unit 1100 are abnormal. The abnormal state of the second output signal Voutp and the first output signal Voutn includes that the voltage values of the second output signal Voutp and the first output signal Voutn are substantially increased or decreased at the same time, or that one of the voltage values of the second output signal Voutp or the first output signal Voutn is substantially increased or decreased.
If the first output signal Voutn is detected to be in an abnormal state, the first control signal output terminal of the detection unit 1410 sends an abnormal control signal INN _ C at this time. When the first control signal input end receives the abnormal control signal INN _ C, the first power supply voltage end is connected with the first voltage input end and the first voltage output end, so that the first input signal Vinp and the first output signal Voutn obtain a common-mode voltage Vcm; similarly, if it is detected that the second output signal Voutp is in an abnormal state, the first control signal output end of the detection unit 1410 sends out an abnormal control signal INP _ C at this time. When the second control signal input terminal receives the abnormal control signal INP _ C, the second power voltage terminal is connected to the second voltage input terminal and the second voltage output terminal, so that the second input signal Vinn and the second output signal Voutp obtain a common mode voltage Vcm.
In this embodiment, when the second output signal Voutp or the first output signal Voutn is abnormal, the detecting unit 1410 may correspondingly output the abnormal control signal INP _ C or INN _ C to the first switch unit 1310 or the second switch unit 1320, and the first switch unit 1310 or the second switch unit 1320 may assist the amplifying unit 1100 to quickly power up and restore to normal by providing a common mode voltage Vcm to the input signal and the output signal of the amplifying unit 1100, and control the power-up setup time and the abnormal response time within a range of 0.1 to 0.3 seconds, thereby achieving the purpose of greatly reducing the power-up setup time and the abnormal response time.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a first switch unit 1310 according to an embodiment of the present disclosure.
Specifically, the first switching unit 1310 includes a first switching subunit 1311, a second switching subunit 1312, a third switching subunit 1313, and a fourth switching subunit 1314; the first terminal of the first switching subunit 1311, the first terminal of the second switching subunit 1312, and the first terminal of the third switching subunit 1313 are connected to the first terminal of the fourth switching subunit 1314, and serve as the fourth terminal of the first switching unit 1310; a second terminal of the first switch subunit 1311 is connected to a second terminal of the second switch subunit 1312 and serves as a first terminal of the first switch unit 1310; a second terminal of the third switching subunit 1313 is connected to a second terminal of the fourth switching subunit 1314, and serves as a second terminal of the first switching unit 1310; the control terminal of the first switch subunit 1311, the control terminal of the second switch subunit 1312, the control terminal of the third switch subunit 1313 and the control terminal of the fourth switch subunit 1314 are the third terminals of the first switch unit 1310.
In a normal state, the control terminal of the first switch subunit 1311, the control terminal of the second switch subunit 1312, the control terminal of the third switch subunit 1313 and the control terminal of the fourth switch subunit 1314 receive normal control signals, and the first switch subunit 1311, the second switch subunit 1312, the third switch subunit 1313 and the fourth switch subunit 1314 are in an open state, so that the common-mode voltage Vcm, the first input signal Vinp and the first output signal Voutn are not connected to each other.
In an abnormal state, the control terminal of the first switch subunit 1311, the control terminal of the second switch subunit 1312, the control terminal of the third switch subunit 1313 and the control terminal of the fourth switch subunit 1314 receive the abnormal control signal INP _ C or the abnormal control signal INN _ C, and the first switch subunit 1311, the second switch subunit 1312, the third switch subunit 1313 and the fourth switch subunit 1314 are in a closed state, so that the common mode voltage Vcm, the first input signal Vinp and the first output signal Voutn are connected to each other.
Optionally, the first switch subunit 1311 and the third switch subunit 1313 are both N-type fets, and the second switch subunit 1312 and the fourth switch subunit 1314 are both P-type fets.
Optionally, the first switch subunit 1311 and the third switch subunit 1313 are both NPN transistors, and the second switch subunit 1312 and the fourth switch subunit 1314 are both PNP transistors.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a second switch unit 1320 according to an embodiment of the present disclosure.
Specifically, the second switching unit 1320 includes a fifth switching subunit 1321, a sixth switching subunit 1322, a seventh switching subunit 1323, and an eighth switching subunit 1324; a first terminal of the fifth switch subunit 1321, a first terminal of the sixth switch subunit 1322, and a first terminal of the seventh switch subunit 1323 are connected to a first terminal of the eighth switch subunit 1324, and serve as a fourth terminal of the second switch unit 1320; a second end of the fifth switch subunit 1321 is connected to a second end of the sixth switch subunit 1322, and serves as the first end of the second switch unit 1320; a second terminal of the seventh switching subunit 1323 is connected to a second terminal of the eighth switching subunit 1324 and serves as a second terminal of the second switching unit 1320; the control terminal of the fifth switch subunit 1321, the control terminal of the sixth switch subunit 1322, the control terminal of the seventh switch subunit 1323, and the control terminal of the eighth switch subunit 1324 are all the third terminals of the second switch unit 1320.
Similarly, in a normal state, the control terminal of the fifth switch subunit 1321, the control terminal of the sixth switch subunit 1322, the control terminal of the seventh switch subunit 1323, and the control terminal of the eighth switch subunit 1324 receive a normal control signal, and the fifth switch subunit 1321, the sixth switch subunit 1322, the seventh switch subunit 1323, and the eighth switch subunit 1324 are in an open state, so that the common mode voltage Vcm, the first input signal Vinp, and the first output signal Voutn are not connected to each other.
In the abnormal state, the control terminal of the fifth switch subunit 1321, the control terminal of the sixth switch subunit 1322, the control terminal of the seventh switch subunit 1323 and the control terminal of the eighth switch subunit 1324 receive the abnormal control signal INP _ C or the abnormal control signal INN _ C, and the fifth switch subunit 1321, the sixth switch subunit 1322, the seventh switch subunit 1323 and the eighth switch subunit 1324 are in the closed state, so that the common mode voltage Vcm, the first input signal Vinp and the first output signal Voutn are connected to each other.
Optionally, the fifth switch subunit 1321 and the seventh switch subunit 1323 are both N-type fets, and the sixth switch subunit 1322 and the eighth switch subunit 1324 are both P-type fets.
Optionally, the fifth switching subunit 1321 and the seventh switching subunit 1323 are both NPN transistors, and the sixth switching subunit 1322 and the eighth switching subunit 1324 are both PNP transistors.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a detecting unit 1410 provided in the present embodiment.
Specifically, the detecting unit 1410 includes a first subtracting unit 1411, a second subtracting unit 1412, a first comparing unit 1421, a second comparing unit 1422, a logic unit 1430 and a triggering unit 1440.
A first input terminal of the first subtraction unit 1411 is a first input terminal of the detection unit 1410, an output terminal of the first subtraction unit 1411 is connected to a first input terminal of the first comparison unit 1421, and is configured to subtract a first preset voltage input through a second input terminal of the first subtraction unit 1411 from a voltage value of an inverted analog signal input through the first input terminal of the first subtraction unit 1411, and output an obtained first difference value through an output terminal of the first subtraction unit 1411.
A first input terminal of the second subtraction unit 1412 is a second input terminal of the detection unit 1410, an output terminal of the second subtraction unit 1412 is connected to the first input terminal of the second comparison unit 1422, and is configured to subtract the second preset voltage input through the second input terminal of the second subtraction unit 1412 from the voltage value of the positive-phase analog signal input through the first input terminal of the second subtraction unit 1412, and output a second difference value through the output terminal of the second subtraction unit 1412.
A second input terminal of the first comparing unit 1421 is a second input terminal of the detecting unit 1410, an output terminal of the first comparing unit 1421 is connected to the first input terminal of the logic unit 1430, and is configured to compare the first difference value with a voltage value of the positive-phase analog signal input by the second input terminal of the first comparing unit 1421, and output a first comparison result through the output terminal of the first comparing unit 1421.
A second input terminal of the second comparing unit 1422 is a first input terminal of the detecting unit 1410, an output terminal of the second comparing unit 1422 is connected to a second input terminal of the logic unit 1430, and is configured to compare the second difference with a voltage value of the inverted analog signal input by the second input terminal of the second comparing unit 1422, and output a second comparison result through the output terminal of the second comparing unit 1422.
The output end of the logic unit 1430 is connected to the input end of the trigger unit 1440, and is configured to perform logic determination according to the first comparison result and the second comparison result, and output the determination result through the output end of the logic unit 1430.
The output terminal of the triggering unit 1440 is divided into the first output terminal of the detecting unit 1410 and the second output terminal of the detecting unit 1410, and is used for generating a normal control signal or an abnormal control signal according to the determination result, and outputting the normal control signal or the abnormal control signal through the output terminal of the triggering unit 1440.
Optionally, the logic unit 1430 is an or gate logic circuit.
Optionally, the trigger unit 1440 is a shift register composed of several D flip-flops.
Preferably, the first predetermined voltage and the second predetermined voltage are the same, and the first predetermined voltage and the second predetermined voltage are 300mV.
In this embodiment, when the first subtracting unit 1411 receives the first output signal Voutn, it subtracts the first preset voltage Vsub from the voltage value of the first output signal Voutn, and transmits the first difference Voutn-Vsub to the first comparing unit 1421; similarly, when the second subtraction unit 1412 receives the second output signal Voutp, it subtracts the second preset voltage Vsub from the voltage value of the second output signal Voutp, and transmits the second difference Voutp-Vsub to the second comparing unit 1422.
The first comparing unit 1421 compares the first difference Voutn-Vsub with the second output signal Voutp to obtain a first comparison result Com1, and transmits the first comparison result Com1 to the logic unit 1430; similarly, the second comparing unit 1422 compares the second difference Voutp-Vsub with the first output signal Voutn to obtain a second comparison result Com2, and transmits the second comparison result Com2 to the logic unit 1430.
The logic unit 1430 is an or gate logic circuit, and outputs a high level or a low level to the flip-flop unit 1440 according to the first comparison result Com1 and the second comparison result Com 2.
The flip-flop 1440 is formed by connecting n D flip-flops in series, and the D flip-flops are driven by the low frequency digital clock signal CLK, and emit a high level or a low level according to the frequency of the low frequency digital clock signal CLK, which is usually 50Hz, as a normal control signal or an abnormal control signal.
In a normal state, the first difference Voutn-Vsub is always smaller than the second output signal Voutp, the second difference Voutp-Vsub is always smaller than the first output signal Voutn, the first comparison result Com1 and the second comparison result Com2 are both 0, and the logic unit 1430 outputs a low level, so that the triggering unit 1440 outputs a normal control signal.
When an abnormality occurs, i.e. the amplifying module is in a power-on state or an input abnormality, which causes the first output signal Voutn and the second output signal Voutp to be in an abnormal state, the first difference value Voutn-Vsub will be greater than the second output signal Voutp for a period of time or the second difference value Voutp-Vsub will be greater than the first output signal Voutn for a period of time, which causes the first comparison result Com1 or the second comparison result Com2 to be 1, which further causes the triggering unit 1440 to activate the abnormal control signal INN _ C or the abnormal control signal INP _ C. When the normal state is restored again, the first output signal Voutn and the second output signal Voutp are restored to normal, the first difference Voutn-Vsub is smaller than the second output signal Voutp, the second difference Voutp-Vsub is smaller than the first output signal Voutn, the first comparison result Com1 and the second comparison result Com2 are both 0, and the logic unit 1430 outputs a low level, so that the flip-flop unit 1440 outputs a normal control signal.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "for example" is used to mean "serving as an example, instance, or illustration". Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (12)
1. A signal amplification circuit is characterized by comprising an amplification unit and a bias current source with bias current set to be nano-ampere level;
one end of the bias current source is connected with the bias current input end of the amplifying unit, and the other end of the bias current source is grounded;
the amplifying unit is used for acquiring the nano-ampere level bias current through the bias current input end and determining an amplified working point according to the nano-ampere level bias current so as to maintain the working state of the amplifying unit;
the amplifying unit comprises a first amplifying subunit and a second amplifying subunit;
the first end of the first amplification subunit and the first end of the second amplification subunit are both used for inputting analog signals;
the second end of the first amplification subunit and the second end of the second amplification subunit are both used for outputting amplified signals obtained by amplifying the analog signals;
the third end of the first amplification subunit and the third end of the second amplification subunit are connected and are used as a power supply voltage input end;
the fourth end of the first amplification subunit and the fourth end of the second amplification subunit are connected and used as the bias current input end;
the signal amplification circuit further comprises a first resistor, a second resistor, a first capacitor and a second capacitor;
one end of the first resistor is connected with the first end of the first amplification subunit, and the other end of the first resistor is connected with the second end of the first amplification subunit;
one end of the second resistor is connected with the first end of the second amplification subunit, and the other end of the second resistor is connected with the second end of the second amplification subunit;
one end of the first capacitor is connected with the first end of the first amplification subunit, and the other end of the first capacitor is connected with the second end of the first amplification subunit;
one end of the second capacitor is connected with the first end of the second amplification subunit, and the other end of the second capacitor is connected with the second end of the second amplification subunit;
the signal amplification circuit further comprises a first switch unit, a second switch unit and a detection unit;
the first end of the first switch unit is connected with the first end of the first amplification subunit, the second end of the first switch unit is connected with the second end of the first amplification subunit, the third end of the first switch unit is connected with the first output end of the detection unit, and the first switch unit and the second switch unit form a path when the third end of the first switch unit receives an abnormal control signal, and a first common mode voltage is input through the fourth end of the first switch unit and is output from the first end of the first switch unit and the second end of the first switch unit;
the first end of the second switching unit is connected with the first end of the second amplifying subunit, the second end of the second switching unit is connected with the second end of the second amplifying subunit, the third end of the second switching unit is connected with the second output end of the detection unit, and when the third end of the second switching unit receives an abnormal control signal, the first end of the second switching unit and the second end of the second switching unit form a path, a second common-mode voltage is input through the fourth end of the second switching unit, and the second common-mode voltage is output from the first end of the second switching unit and the second end of the second switching unit;
the first input end of the detection unit is connected with the second end of the first amplification subunit, the second input end of the detection unit is connected with the second end of the second amplification subunit, and the detection unit is used for outputting an abnormal control signal or a normal control signal through the first output end of the detection unit and the second output end of the detection unit according to amplification signals acquired from the first input end of the detection unit and the second input end of the detection unit.
2. The signal amplification circuit of claim 1, wherein the first amplification subunit comprises a first N-type field effect transistor and a first P-type field effect transistor, and the second amplification subunit comprises a second N-type field effect transistor and a second P-type field effect transistor:
the grid electrode of the first N-type field effect transistor is connected with the grid electrode of the first P-type field effect transistor and serves as the first end of the first amplification subunit; the grid electrode of the second N-type field effect transistor is connected with the grid electrode of the second P-type field effect transistor and serves as the first end of the second amplification subunit;
the drain electrode of the first N-type field effect transistor is connected with the drain electrode of the first P-type field effect transistor and is used as a second end of the first amplification subunit; the drain electrode of the second N-type field effect transistor is connected with the drain electrode of the second P-type field effect transistor to serve as a second end of the second amplification subunit;
the source electrode of the first P-type field effect transistor is the third end of the first amplification subunit, and the source electrode of the second P-type field effect transistor is the third end of the second amplification subunit;
the source electrode of the first N-type field effect transistor is the fourth end of the first amplification subunit, and the source electrode of the second N-type field effect transistor is the fourth end of the second amplification subunit.
3. The signal amplification circuit of claim 2, wherein the width-to-length ratios of the first N-type fet and the second N-type fet are both a first predetermined value, and the width-to-length ratios of the first P-type fet and the second P-type fet are both a second predetermined value.
4. The signal amplification circuit according to claim 1, comprising an adjustment unit;
the first end of the regulating unit is used for inputting working voltage, the second end of the regulating unit is connected with the power supply voltage input end, and the third end of the regulating unit is used for inputting bias voltage.
5. The signal amplification circuit of claim 4, wherein the adjustment unit is a third P-type field effect transistor;
the source electrode of the third P-type field effect transistor is the first end of the adjusting unit, the grid electrode of the third P-type field effect transistor is the third end of the adjusting unit, and the drain electrode of the third P-type field effect transistor is the second end of the adjusting unit.
6. The signal amplification circuit of claim 1, wherein the first switching unit comprises a first switching subunit, a second switching subunit, a third switching subunit, and a fourth switching subunit;
the first end of the first switch subunit, the first end of the second switch subunit and the first end of the third switch subunit are connected with the first end of the fourth switch subunit and serve as the fourth end of the first switch unit;
the second end of the first switch subunit is connected with the second end of the second switch subunit and serves as the first end of the first switch unit;
the second end of the third switch subunit is connected with the second end of the fourth switch subunit and is used as the second end of the first switch unit;
and the control end of the first switch subunit, the control end of the second switch subunit, the control end of the third switch subunit and the control end of the fourth switch subunit are the third end of the first switch unit.
7. The signal amplification circuit of claim 6, wherein the first switch subunit and the third switch subunit are both N-type field effect transistors, and the second switch subunit and the fourth switch subunit are both P-type field effect transistors.
8. The signal amplification circuit according to claim 1 or 6, wherein the second switching unit comprises a fifth switching subunit, a sixth switching subunit, a seventh switching subunit, and an eighth switching subunit;
the first end of the fifth switch subunit, the first end of the sixth switch subunit and the first end of the seventh switch subunit are connected with the first end of the eighth switch subunit and serve as the fourth end of the second switch unit;
the second end of the fifth switch subunit is connected with the second end of the sixth switch subunit and serves as the first end of the second switch unit;
the second end of the seventh switch subunit is connected with the second end of the eighth switch subunit and serves as the second end of the second switch unit;
and the control end of the fifth switch subunit, the control end of the sixth switch subunit, the control end of the seventh switch subunit and the control end of the eighth switch subunit are the third ends of the second switch unit.
9. The signal amplifying circuit according to claim 8, wherein the fifth switching subunit and the seventh switching subunit are both N-type field effect transistors, and the sixth switching subunit and the eighth switching subunit are both P-type field effect transistors.
10. The signal amplification circuit according to claim 1, wherein the detection unit includes a first subtraction unit, a second subtraction unit, a first comparison unit, a second comparison unit, a logic unit, and a trigger unit;
the first input end of the first subtraction unit is the first input end of the detection unit, the output end of the first subtraction unit is connected with the first input end of the first comparison unit, and the first subtraction unit is used for subtracting a first preset voltage input through the second input end of the first subtraction unit from a voltage value of the inverted analog signal input through the first input end of the first subtraction unit, and outputting an obtained first difference value through the output end of the first subtraction unit;
the first input end of the second subtraction unit is the second input end of the detection unit, the output end of the second subtraction unit is connected with the first input end of the second comparison unit, and the second subtraction unit is used for subtracting a second preset voltage input through the second input end of the second subtraction unit from the voltage value of the positive-phase analog signal input through the first input end of the second subtraction unit, and outputting an obtained second difference value through the output end of the second subtraction unit;
the second input end of the first comparing unit is the second input end of the detecting unit, the output end of the first comparing unit is connected with the first input end of the logic unit, and the first comparing unit is used for comparing the first difference value with the voltage value of the normal-phase analog signal input by the second input end of the first comparing unit and outputting a first comparing result through the output end of the first comparing unit;
a second input end of the second comparing unit is a first input end of the detecting unit, an output end of the second comparing unit is connected with a second input end of the logic unit, and the second comparing unit is used for comparing the second difference value with a voltage value of an inverted analog signal input by the second input end of the second comparing unit and outputting a second comparison result through an output end of the second comparing unit;
the output end of the logic unit is connected with the input end of the trigger unit and is used for carrying out logic judgment according to the first comparison result and the second comparison result and outputting the judgment result through the output end of the logic unit;
the output end of the trigger unit is divided into a first output end of the detection unit and a second output end of the detection unit, and is used for generating a normal control signal or an abnormal control signal according to the judgment result and outputting the normal control signal or the abnormal control signal through the output end of the trigger unit.
11. The signal amplification circuit of claim 10, wherein the logic cell is an or gate logic circuit.
12. The signal amplification circuit of claim 10, wherein the flip-flop is a shift register comprising a plurality of D flip-flops.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210104090.3A CN114430253B (en) | 2022-01-27 | 2022-01-27 | Signal amplification circuit |
| PCT/CN2023/072540 WO2023143230A1 (en) | 2022-01-27 | 2023-01-17 | Signal amplification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210104090.3A CN114430253B (en) | 2022-01-27 | 2022-01-27 | Signal amplification circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114430253A CN114430253A (en) | 2022-05-03 |
| CN114430253B true CN114430253B (en) | 2023-04-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210104090.3A Active CN114430253B (en) | 2022-01-27 | 2022-01-27 | Signal amplification circuit |
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| CN (1) | CN114430253B (en) |
| WO (1) | WO2023143230A1 (en) |
Families Citing this family (1)
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| CN114430253B (en) * | 2022-01-27 | 2023-04-14 | 深圳市九天睿芯科技有限公司 | Signal amplification circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315179A (en) * | 1992-09-28 | 1994-05-24 | Motorola, Inc. | BICMOS level converter circuit |
| CN101777877A (en) * | 2010-01-05 | 2010-07-14 | 南京广嘉微电子有限公司 | Wide band radio-frequency low noise amplifier with single-ended input and differential output |
| JP4988883B2 (en) * | 2010-03-01 | 2012-08-01 | 株式会社半導体理工学研究センター | Comparator circuit |
| JP5846840B2 (en) * | 2011-10-14 | 2016-01-20 | ルネサスエレクトロニクス株式会社 | Filter circuit and receiver |
| JP5503671B2 (en) * | 2012-01-30 | 2014-05-28 | 株式会社半導体理工学研究センター | Differential amplifier circuit |
| CN103595356B (en) * | 2013-11-12 | 2016-08-17 | 四川和芯微电子股份有限公司 | High frequency bandwidth amplifying circuit |
| US10432155B2 (en) * | 2018-02-07 | 2019-10-01 | Dialog Semiconductor (Uk) Limited | Fast startup bias current generator |
| CN109546974B (en) * | 2018-11-16 | 2021-09-21 | 华南理工大学 | Multichannel current multiplexing chopper amplifier and chip |
| CN112448721B (en) * | 2019-08-29 | 2023-05-05 | 天津大学青岛海洋技术研究院 | Low-power consumption comparator with low delay distortion characteristic of self-bias circuit |
| CN114430253B (en) * | 2022-01-27 | 2023-04-14 | 深圳市九天睿芯科技有限公司 | Signal amplification circuit |
-
2022
- 2022-01-27 CN CN202210104090.3A patent/CN114430253B/en active Active
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2023
- 2023-01-17 WO PCT/CN2023/072540 patent/WO2023143230A1/en unknown
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| Publication number | Publication date |
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| CN114430253A (en) | 2022-05-03 |
| WO2023143230A1 (en) | 2023-08-03 |
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