CN111766555A - Data synchronization method for distribution network CT error checking process - Google Patents
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Abstract
The embodiment of the application provides a data synchronization method for a distribution network CT error checking process, which is suitable for a synchronization process of output signals of at least two direct current transformers. Sampling output data of each current transformer according to a preset sampling frequency; acquiring fixed time delay, and sending output data obtained by sampling to a merging unit after the fixed time delay; and performing synchronous processing on the obtained output data in a resampling synchronization mode in the merging unit. Because the resampling algorithm uses the homologous FPGA clock to carry out interpolation operation on the data of the collector, and simultaneously, the resampling algorithm adopts the parabolic interpolation algorithm, the resampling algorithm has high accuracy and can meet the requirement of the data accuracy of a direct current system.
Description
Technical Field
The invention belongs to the field of data processing, and particularly relates to a data synchronization method for a distribution network CT error check process.
Background
With the development of urbanization, in order to improve the power supply reliability of a distribution network and improve the service quality and meet the requirement of the beautiful life of people on high-quality power supply service, countries and companies all invest a large amount of manpower and material resources to strengthen the construction, upgrading and transformation of the distribution network. Especially, a large number of distribution network automation devices all contain mutual inductor equipment (such as PT or CT), and the equipment cannot meet the requirements of live operation due to the quality, process, structure and the like, so that accidents occur. Therefore, aiming at the research of the uninterrupted operation technology of the distribution network automation equipment containing the mutual inductor, the problem that the equipment is damaged or broken due to improper operation to affect the safety of the equipment and operators can be reduced or avoided, the research of the uninterrupted operation technology of the distribution network automation equipment is developed for the first time, the blank of the company in the aspect is filled, the power failure of engineering prearrangement is reduced, and the power supply reliability is improved.
The live-line disconnection drainage wire is the most basic conventional live-line work project of a 10kV overhead distribution line and accounts for about 60% of the live-line work times of each unit of a power company every year. In order to ensure the safety of live working, safety regulations require that when a no-load line is disconnected and connected in a live state, a circuit breaker (switch) and an isolating switch (knife switch) at the other end of the line are required to be confirmed to be disconnected, and a transformer and a voltage transformer which are connected to the line side can be carried out after the transformer and the voltage transformer are confirmed to be withdrawn from operation. However, with the overall progress of the automatic transformation work of the distribution lines of the urban power grid, various load switches are widely used, and a transformer (energy-taking PT for short) for providing power for a controller and an operating device of the load switch cannot quit operation during live-line work. Whether the energy taking PT can be installed in a charged state or not and the drainage wire with the PT is disconnected become the difficult problems which need to be solved urgently in the current charged work.
The mutual inductor is an important component of an electric energy metering device and is a legal metering appliance for performing fair and fair trade settlement between a power generation company and a power grid company, between the power grid company and a power supply company, between the power supply company and power users and accurately calculating and checking technical and economic indexes in a power system. According to the current national verification regulations, the transformers (including voltage transformers and current transformers) used for metering in the power grid must be regularly subjected to error characteristic detection. According to the conventional detection method, the error characteristic detection can be carried out only by taking an operating transformer off-line, which inevitably affects the power supply reliability. And the electric power system in China has a huge number of power transformers, the error performance workload of the power system in power failure test is huge, time and labor are wasted, and real data in a three-phase electrified state cannot be obtained.
Disclosure of Invention
In order to solve the defects and shortcomings in the prior art, the invention provides a data synchronization method for a distribution network CT error check process, which is suitable for the synchronization process of output signals of at least two direct current transformers.
Specifically, the data synchronization method for the distribution network CT error check process includes:
sampling output data of each current transformer according to a preset sampling frequency;
acquiring fixed time delay, and sending output data obtained by sampling to a merging unit after the fixed time delay;
and performing synchronous processing on the obtained output data in a resampling synchronization mode in the merging unit.
Optionally, the performing, in the merging unit, synchronization processing on the obtained output data in a resampling synchronization manner includes:
performing time operation based on the FPGA clock in the merging unit to obtain marked time;
and performing secondary acquisition on the obtained output data by taking the marking time as a time reference to finish synchronous processing.
Optionally, the performing time operation based on the FPGA clock in the merging unit to obtain the marked time includes:
and calling FPGA hardware logic in the merging unit to carry out protocol analysis, and adding an operating frequency count value of the FPGA to carry out interpolation operation on the collector data to obtain the marking time.
Optionally, the performing, by using the marked time as a time reference, secondary acquisition on the obtained output data to complete synchronous processing includes:
the A/D conversion modules of different channels start data acquisition by taking the time reference as the time reference, and the data synchronization and message framing module takes the time reference as a message sequence number zero clearing mark to realize data synchronization among different channels.
Optionally, the obtaining the fixed time delay includes:
applying current or voltage to the merging unit by using a current booster or a voltage booster, testing the current or voltage analog quantity by using an electronic transformer tester, and receiving a digital message output by the merging unit;
and calculating the angular difference and the ratio difference of the two to obtain the fixed time delay.
Optionally, a data preprocessing method is further included before sampling the output data of each current transformer according to a preset sampling frequency.
Optionally, the data preprocessing method includes:
receiving a pulse per second synchronization signal sent by a GPS unit;
judging the correctness of the pulse per second signal, and selectively generating a sampling signal sent to an A/D converter according to different judgment results;
after the A/D converter receives the sampling signal, the first signal connected to the input end of the A/D converter is converted, and the converted signal is transmitted to the data synchronization module;
and the control data receiving module transmits the received second signal to the data synchronization module, and the data synchronization module carries out synchronization processing on the received converted signal and the second signal.
Optionally, the determining the correctness of the pulse per second signal and selectively generating the sampling signal sent to the a/D converter according to different determination results includes:
if the second pulse signal format is correct, sending a sampling signal representing the actual time interval to the A/D converter;
if the pulse per second signal is in error, a sampling signal of a standard time interval is sent to the A/D converter.
Optionally, if the format of the pulse per second signal is correct, sending a sampling signal representing the actual time interval to the a/D converter includes:
when the pulse per second signal format is correct, a signal time interval between pulse per second signals is acquired, a sampling signal format is determined based on the time interval, and the sampling signal is sent to the A/D converter.
The technical scheme provided by the invention has the beneficial effects that:
because the resampling algorithm uses the homologous FPGA clock to carry out interpolation operation on the data of the collector, and simultaneously, the resampling algorithm adopts the parabolic interpolation algorithm, the resampling algorithm has high accuracy and can meet the requirement of the data accuracy of a direct current system.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a data synchronization method for a distribution network CT error checking process according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a data preprocessing method according to an embodiment of the present application;
fig. 3 is a schematic diagram of a preprocessing step performed by the merging unit according to an embodiment of the present application.
Detailed Description
To make the structure and advantages of the present invention clearer, the structure of the present invention will be further described with reference to the accompanying drawings.
Example one
In a high-voltage direct-current transmission project and a flexible direct-current transmission project, a direct-current merging unit merges and processes current and voltage data signals converted by direct-current measuring devices at different measuring points such as a valve hall, a polar line, a neutral line and the like, converts the current and voltage data signals into digital signals according to IEC60044-7/8 standard specifications and outputs the digital signals to devices such as a protection device, a valve control device and the like, and in order to realize local sampling synchronization and ensure the synchronous sampling of all alternating current and direct current analog quantity acquisition of a direct-current converter station, the merging unit meets the requirements of data sampling synchronization and errors.
Specifically, as shown in fig. 1, the data synchronization method for the distribution network CT error check process includes:
11. sampling output data of each current transformer according to a preset sampling frequency;
12. acquiring fixed time delay, and sending output data obtained by sampling to a merging unit after the fixed time delay;
13. and performing synchronous processing on the obtained output data in a resampling synchronization mode in the merging unit.
In implementation, the merging unit generally receives all current and voltage channel data for one interval (dc field region). The synchronization of the merging units includes two aspects:
1) synchronization among all direct current transformers, namely synchronization of current and voltage data of the interval;
2) and synchronization among the merging units, namely synchronization of current and voltage data of different intervals.
For synchronization between direct current transformers, there are two methods, namely, hardware pulse synchronization and differential synchronization (software). The merging unit is usually synchronized in a resampling mode. After data sampling is carried out among all the transformers according to set frequency, the data are sent to a merging unit after fixed time delay, the merging unit carries out protocol analysis by using FPGA hardware logic, and an operation frequency counting value of the FPGA is added.
The resampling algorithm uses the homologous FPGA clock to perform interpolation operation on the collector data. The resampling algorithm adopts a parabolic interpolation algorithm, has high accuracy and can meet the data accuracy requirement of a direct current system.
Optionally, the performing, in the merging unit, synchronization processing on the obtained output data in a resampling synchronization manner includes:
performing time operation based on the FPGA clock in the merging unit to obtain marked time;
and performing secondary acquisition on the obtained output data by taking the marking time as a time reference to finish synchronous processing.
In implementation, when a synchronous pulse method is adopted, different merging units of the same transformer substation start data acquisition at a clock pulse edge depending on a station-level synchronous clock, so that data have the same sampling time sequence and time mark, and data synchronization among different merging units is realized. For a certain merging unit, the synchronous processing module receives a station-level synchronous clock, analyzes a Pulse Per Second (PPS) signal from the station-level synchronous clock, starts data acquisition by taking the time reference of the different channel A/D conversion module, and finally achieves data synchronization among different channels by taking the time reference as a message sequence number zero clearing mark of the data synchronization and message framing module.
When the synchronous processing module resolves the synchronous clock at the station level, a time difference T1 exists between the output PPS and the input CLK, and the time difference can be represented as T1＝t11-t12Where t11 is the time delay associated with the hardware composition and hardware processing method of the synchronous processing module, and t12 is the random time fluctuation associated with the operating environment and the operating state of the crystal oscillator. T11 is generally different for different merge units; for different types of station level synchronous clocks, the process method will not be uniform and will also cause t11 to vary. But in the same transformer substation, the type of the station level synchronous clock is fixed, and the hardware of the synchronous processing module is determinedThe time delay t11 is relatively stable.
For the analog input merging unit, the external synchronization state of the access station level synchronous clock is called a time synchronization state, and T1 represents a time synchronization error; the internal synchronization state after the loss of the station-level synchronization clock is called a time-keeping state, and T1 represents a time-keeping error. The time setting and time keeping errors are related to the performance of the synchronous processing module and are reflected in the phase of the voltage and current data, and in a theoretical situation, a 1 mu s time error brings a 1.08' phase error.
When a fixed time delay method is adopted, the merging unit does not depend on a station-level synchronous clock, but carries out point-to-point communication in a cascade mode, the preceding merging unit continuously samples at the sampling frequency of the preceding merging unit and sends SV messages according to fixed rated time delay and rated time intervals, and the subsequent merging unit or other metering equipment carries out compensation and interpolation calculation on the received messages according to the fixed time delay so as to realize data synchronization among channels.
The commonly used interpolation method is a software synchronization method and is also a method commonly applied to most merging units in China at present. By establishing an interpolation function and then substituting the known sampling value and the corresponding time scale into the interpolation function, the voltage and current sampling values at the middle designated moment can be approximately obtained.
Optionally, the performing, by using the marked time as a time reference, secondary acquisition on the obtained output data to complete synchronous processing includes:
the A/D conversion modules of different channels start data acquisition by taking the time reference as the time reference, and the data synchronization and message framing module takes the time reference as a message sequence number zero clearing mark to realize data synchronization among different channels.
In the fixed time delay method, data synchronization is not required between the preceding stage merging units, and the subsequent stage device performs interpolation calculation according to the fixed time delay parameters to ensure the data synchronization of each channel in the SV message. The fixed time delay Td can be expressed as:
Td＝T2+Ts+Trin the formula, T2The response time of the SV message of the preceding merging unit is the intrinsic parameter of the merging unit; t issFor the message transmission delay, the length of the data packet,The data transmission distance is related and relatively stable; t isrThe message receiving time of the rear-stage metering equipment and the SV message receiving processing time are related to the digital quantity processing capacity.
In the interpolation calculation, the time delay T is fixeddThe size will affect the synchronous precision of the resampling data and directly reflect the synchronous precision to the phase of the voltage and current sampling value. Generally, the fixed delay is an amount of time in ms, and the error of the fixed delay will introduce a large phase error, which seriously affects the power metering.
The testing method for merging unit time delay generally includes two types: testing the time delay of the merging unit by using an electronic transformer tester; and simultaneously outputting the time delay of the analog quantity test merging unit and the digital quantity test merging unit.
At present, the time delay of a merging unit is tested by an internal electronic transformer tester in the following mode: and applying current or voltage to the merging unit by using a current booster or a voltage booster, testing the current or voltage analog quantity by using an electronic transformer tester, receiving the digital message output by the merging unit, and calculating the angular difference and the ratio difference of the two to obtain the time delay of the merging unit.
Because the testing is carried out by adopting externally applied steady-state current or voltage, the electronic mutual inductor tester can not directly control the voltage and the current, so the method can not form a closed-loop testing environment, only one path of signal can be tested at one time, the measuring efficiency is low, and the voltage, the current and the message need to be synchronized at the same time. And because a steady-state signal test is adopted, when the analog quantity signal and the digital quantity signal have a whole cycle, the time delay is carried out, the waveforms are overlapped on the electronic transformer tester, and the condition that the identification phase difference is zero can occur. Therefore, for the case of the delay being a full cycle, the method may not be able to test the merging unit delay.
The relay protection tester can simultaneously output analog quantity and digital quantity, can output analog quantity current and voltage, and can also output and receive digital quantity transmitted by optical fiber, and it completely integrates the test function of merging unit. The concrete mode is as follows: the relay protection instrument directly outputs voltage and current to the merging unit, receives and analyzes messages output by the merging unit, and measures time delay, namely phase difference between the two.
The method can form a closed-loop test environment, and the relay protection instrument can directly control the steady-state output and the transient-state output of the voltage and the current, so that the time delay of the merging unit can be really tested. When the analog quantity signal and the digital quantity signal have the time delay of the whole cycle, because the relay protection instrument can apply the transient signal, the waveform starting edge can be clearly observed during waveform identification, so that the real time delay can be accurately calculated, and the condition of the time delay of the whole cycle can be completely tested.
At present, the relay protection instrument can output 6 paths of voltage and 6 paths of current, can measure time delay and specific difference of all channels of combined unit messages at one time, can complete work without using a current booster and a voltage booster, and greatly improves testing efficiency. The relay protection instrument is also provided with a multi-channel optical fiber port, the multi-channel optical signals output by one merging unit can be simultaneously accessed, the time delay of the multi-channel optical signals can be accurately measured at one time, the testing efficiency is improved, and the phase discreteness deviation of the multi-channel digital signals can be tested.
The inside of the tester synchronously controls the output voltage and current, and simultaneously receives the message output by the merging unit and records the message time; and calculating the waveform of the message by taking the actually output voltage and current waveforms as reference to obtain the ratio difference and the angle difference of the merging unit. Because the actual analog quantity is used as a reference, the merging unit can test whether receiving the pulse per second or not or the B code synchronization. During testing, the value of 0 is output for 3 seconds, then the corresponding voltage or current is output, and the actual time delay can be measured by utilizing the step waveform output by the tester to be compared with the waveform output by the merging unit for calculation
Optionally, a data preprocessing method is further included before sampling the output data of each current transformer according to a preset sampling frequency. As shown in fig. 2, the data preprocessing method includes:
21. a pulse per second synchronization signal sent by the GPS unit;
22. judging the correctness of the pulse per second signal, and selectively generating a sampling signal sent to an A/D converter according to different judgment results;
23. after the A/D converter receives the sampling signal, the first signal connected to the input end of the A/D converter is converted, and the converted signal is transmitted to the data synchronization module;
24. and the control data receiving module transmits the received second signal to the data synchronization module, and the data synchronization module carries out synchronization processing on the received converted signal and the second signal.
In the implementation, in a high-voltage direct-current transmission project and a flexible direct-current transmission project, a direct-current merging unit merges and processes data signals of current and voltage converted by direct-current measuring devices at different measuring points such as a valve hall, a polar line, a neutral line and the like, converts the data signals into digital signals according to IEC60044-7/8 standard specifications and outputs the digital signals to protection, valve control and other devices, and in order to realize local sampling synchronization and ensure that all alternating-current and direct-current analog quantity acquisition synchronous sampling of a direct-current converter station, the merging unit needs to meet the requirements of data sampling synchronization and errors. Fig. 3 is a schematic diagram corresponding to the preprocessing steps performed by the merging units, where a synchronization signal 1 is a pulse-per-second clock signal synchronized between the merging units, and a synchronization signal 2 is a sampling signal sent by the merging unit to each converter. The synchronization process is as follows: generating a pulse per second synchronization signal 1 by a GPS; the merging unit receives a synchronous signal 1; judging the correctness of the synchronous signal 1, if the signal is wrong, sending an alarm signal, and sending an equispaced synchronous signal 2 to each converter by adopting a self time-keeping signal; when the synchronization signal 1 is correct, the synchronization signal 2 is transmitted to each converter at equal intervals.
Optionally, the determining the correctness of the pulse per second signal and selectively generating the sampling signal sent to the a/D converter according to different determination results includes:
if the second pulse signal format is correct, sending a sampling signal representing the actual time interval to the A/D converter; when the pulse per second signal format is correct, a signal time interval between pulse per second signals is acquired, a sampling signal format is determined based on the time interval, and the sampling signal is sent to the A/D converter.
If the pulse per second signal is in error, a sampling signal of a standard time interval is sent to the A/D converter.
The sequence numbers in the above embodiments are merely for description, and do not represent the sequence of the assembly or the use of the components.
The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The data synchronization method for the distribution network CT error check process is suitable for the synchronization process of output signals of at least two direct current transformers, and is characterized by comprising the following steps:
sampling output data of each current transformer according to a preset sampling frequency;
acquiring fixed time delay, and sending output data obtained by sampling to a merging unit after the fixed time delay;
and performing synchronous processing on the obtained output data in a resampling synchronization mode in the merging unit.
2. The data synchronization method for the distribution network CT error checking process according to claim 1, wherein the synchronizing the obtained output data in the merging unit by means of resampling synchronization includes:
performing time operation based on the FPGA clock in the merging unit to obtain marked time;
and performing secondary acquisition on the obtained output data by taking the marking time as a time reference to finish synchronous processing.
3. The data synchronization method for the distribution network CT error checking process according to claim 2, wherein the performing time operation based on the FPGA clock in the merging unit to obtain the marked time comprises:
and calling FPGA hardware logic in the merging unit to carry out protocol analysis, and adding an operating frequency count value of the FPGA to carry out interpolation operation on the collector data to obtain the marking time.
4. The data synchronization method for the distribution network CT error checking process according to claim 2, wherein the performing of the secondary acquisition of the obtained output data with the marked time as the time reference to complete the synchronization process comprises:
the A/D conversion modules of different channels start data acquisition by taking the time reference as the time reference, and the data synchronization and message framing module takes the time reference as a message sequence number zero clearing mark to realize data synchronization among different channels.
5. The data synchronization method for the distribution network CT error checking process as claimed in claim 1, wherein said obtaining a fixed time delay comprises:
applying current or voltage to the merging unit by using a current booster or a voltage booster, testing the current or voltage analog quantity by using an electronic transformer tester, and receiving a digital message output by the merging unit;
and calculating the angular difference and the ratio difference of the two to obtain the fixed time delay.
6. The data synchronization method for the distribution network CT error checking process as recited in claim 1, further comprising a data preprocessing method before sampling the output data of each current transformer according to a preset sampling frequency.
7. The data synchronization method for the distribution network CT error checking process according to claim 6, wherein the data preprocessing method comprises:
receiving a pulse per second synchronization signal sent by a GPS unit;
judging the correctness of the pulse per second signal, and selectively generating a sampling signal sent to an A/D converter according to different judgment results;
after the A/D converter receives the sampling signal, the first signal connected to the input end of the A/D converter is converted, and the converted signal is transmitted to the data synchronization module;
and the control data receiving module transmits the received second signal to the data synchronization module, and the data synchronization module carries out synchronization processing on the received converted signal and the second signal.
8. The data synchronization method for the distribution network CT error checking process according to claim 7, wherein the determining the correctness of the pulse per second signal and selectively generating the sampling signal to be sent to the a/D converter according to the determination result comprises:
if the second pulse signal format is correct, sending a sampling signal representing the actual time interval to the A/D converter;
if the pulse per second signal is in error, a sampling signal of a standard time interval is sent to the A/D converter.
9. The method of claim 8, wherein sending a sampling signal representative of the actual time interval to the a/D converter if the pulse-per-second signal is in the correct format comprises:
when the pulse per second signal format is correct, a signal time interval between pulse per second signals is acquired, a sampling signal format is determined based on the time interval, and the sampling signal is sent to the A/D converter.
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| CN113453330A (en) * | 2021-07-12 | 2021-09-28 | 北京四方继保自动化股份有限公司 | Wireless transmission method based on power distribution network terminal differential service data |
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