CN114071041A - Line-column subtraction reading circuit based on composite dielectric gate double-transistor photosensitive detector - Google Patents
Line-column subtraction reading circuit based on composite dielectric gate double-transistor photosensitive detector Download PDFInfo
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- H—ELECTRICITY
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
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Abstract
The invention discloses a row-column subtraction reading circuit based on a composite dielectric gate double-transistor photosensitive detector. The circuit comprises a transistor array, a word line selection module, an odd bit line selection module, an even bit line selection module, a current subtraction module and the like, wherein the transistor array is composed of a plurality of composite gate dielectric transistors, and in the transistor array: all the transistor grids in the same row are connected to form a word line, and the word line is connected with the word line selection module; the drains of all transistors in the odd rows and the odd columns are connected to form odd bit lines, and the odd bit lines are connected with the odd bit line selection module; the drains of all transistors in even rows and columns are connected to form even bit lines, and the even bit lines are connected with the even bit line selection module; the source electrodes of all transistors in the same column are connected to form a source line; the odd bit line selection module and the even bit line selection module are connected with the current subtraction module, and the current subtraction module is sequentially connected with the current-voltage conversion module and the digital-to-analog conversion module. The reading circuit has the advantages of small area, low power consumption, low noise and high precision.
Description
Technical Field
The invention relates to a row-column current subtraction reading circuit based on a composite dielectric gate double-transistor photosensitive detector, belonging to the field of integrated circuits.
Background
The common imaging devices in the imaging field are CCD and CMOS-APS, but both have many disadvantages in practical applications. For the CCD, it is difficult to make the size small in consideration of transfer efficiency. For CMOS-APS, the occupied area is large due to the complexity of the reading circuit, so that the actual photosensitive area is difficult to be large and the full-well charge quantity is small.
Chinese patent publication No. CN 102938409B proposes a two-transistor photosensitive detector. Compared with CCD and CMOS-APS, the double-transistor photosensitive detector does not need a complex reading part, the area can be greatly reduced, the photosensitive area can be larger, and the charge quantity of a full well is large. However, for the conventional photosensitive detector, the output is usually subtracted in the digital domain, which may cause problems of large area, large power consumption, high noise, low precision, and the like.
Disclosure of Invention
The invention aims to provide a row-column current subtraction reading circuit based on a composite dielectric gate two-transistor photosensitive detector, which can realize current subtraction reading between pixel rows and between pixel columns.
The technical scheme of the invention is as follows:
the row-column subtraction reading circuit based on the composite dielectric gate double-transistor photosensitive detector comprises a transistor array, a word line selection module, an odd bit line selection module, an even bit line selection module, a current subtraction module, a current-voltage conversion module and a digital-to-analog conversion module, wherein the transistor array is composed of a plurality of composite gate dielectric transistors; all transistor grids in the same row in the transistor array are connected to form a word line and connected with the output end of the word line selection module; the drain electrodes of all transistors in odd rows and columns in the transistor array are connected to form odd bit lines, and the odd bit lines are connected with the output end of the odd bit line selection module; all transistor drains of even rows and columns in the transistor array are connected to form even bit lines and are connected with the output end of the even bit line selection module; all transistor source electrodes of the transistor arrays in the same column are connected to form a source line; the output end of the odd bit line selection module and the output end of the even bit line selection module are both connected with the input end of the current subtraction module, the output end of the current subtraction module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the digital-to-analog conversion module.
Furthermore, the word line selection module comprises a word line selection decoder and a word line level conversion circuit, wherein the input end of the word line selection decoder is connected with a word line address signal, and the output ends of the word line selection decoder are connected with the input ends of the word line level conversion circuit in a one-to-one correspondence manner; and the output end of the word line level conversion circuit is used as the output end of the word line selection module and is connected with the word lines of the transistor array in a one-to-one correspondence manner.
Furthermore, the odd bit line selection module comprises an odd bit line selection decoder and an odd bit line level conversion circuit, wherein the input end of the odd bit line selection decoder is connected with an odd bit line address signal, and the output end of the odd bit line selection decoder is connected with the input end of the odd bit line level conversion circuit in a one-to-one correspondence manner; and the output end of the odd bit line level conversion circuit is used as the output end of the odd bit line selection module and is connected with the odd bit lines of the transistor array in a one-to-one correspondence manner.
Furthermore, the even bit line selection module comprises an even bit line selection decoder and an even bit line level conversion circuit, wherein the input end of the even bit line selection decoder is connected with the even bit line address signal, and the output end of the even bit line selection decoder is connected with the input end of the even bit line level conversion circuit in a one-to-one correspondence manner; and the output end of the even bit line level conversion circuit is used as the output end of the even bit line selection module and is connected with the even bit lines of the transistor array in a one-to-one correspondence manner.
Further, the current subtraction module comprises an odd-even row current mirror subtraction circuit, an odd-even row odd-even column current mirror subtraction circuit, and an even-even row odd-even column current mirror subtraction circuit; the input end of the odd-even row current mirror subtraction circuit is connected with the odd bit line and the even bit line in the same column, and the output end of the odd-even row current mirror subtraction circuit is used as the output end of the current subtraction module; the input end of the odd row odd-even column current mirror subtraction circuit is connected with the odd bit lines of every two adjacent columns in the transistor array, and the output end of the odd row odd-even column current mirror subtraction circuit is used as the output end of the current subtraction module; the input end of the even row odd-even column current mirror subtraction circuit is connected with the even bit lines of every two adjacent columns in the transistor array, and the output end of the even row odd-even column current mirror subtraction circuit is used as the output end of the current subtraction module and is connected with the input end of the current-voltage conversion module.
Furthermore, the current-voltage conversion module is a capacitor module with a pre-charge function, an output end of the current-voltage conversion module is connected with an input end of the digital-to-analog conversion module, and the digital-to-analog conversion module is a single-slope digital-to-analog converter.
Further, the transistor array uses a current subtraction module; in a transistor array, one odd-even row current mirror subtraction circuit is used for odd bit lines and even bit lines of each column, one odd-even row current mirror subtraction circuit is used for odd bit lines of each two adjacent columns, and one even-even row current mirror subtraction circuit is used for even bit lines of each two adjacent columns.
The invention provides a row-column current subtraction reading circuit in an analog domain, which has the following technical effects:
in a read mode, word lines of two adjacent rows of the composite gate dielectric transistor array are controlled to be gated through a word line address signal in one read period, and all odd bit lines and all even bit lines of the composite gate dielectric transistor array are controlled to be gated through odd bit line address signals and even bit line address signals respectively. Current subtraction reading of odd rows and even rows and odd columns and even columns is achieved through the odd-even row current mirror subtraction circuit, the odd-even row and odd-even column current mirror subtraction circuit and the even-even row and odd-even column current mirror subtraction circuit. The row-column current subtraction reading circuit has the advantages of small area, low power consumption, low noise and high precision.
Drawings
FIG. 1 is a block diagram of a composite dielectric gate two-transistor photosensitive detector array and various circuit modules,
fig. 2 is a schematic diagram of the connection mode of each port of the composite dielectric gate two-transistor photosensitive detector array in the read-out mode.
Detailed Description
The embodiment provides a row-column current subtraction reading circuit based on a composite dielectric gate double-transistor photosensitive detector, which comprises an array formed by a plurality of composite gate dielectric transistors, a word line selection module, an odd bit line selection module, an even bit line selection module, a current subtraction module, a current-voltage conversion module and a digital-to-analog conversion module. All the transistor gates in the same row in the transistor array are connected to form a word line (denoted as WL) which is connected to the output of the word line select block. The drains of all transistors in odd rows and columns in the transistor array are connected to form odd bit lines (called BLO) connected to the output of the odd bit line selection block. The drains of all transistors in even rows and columns in the transistor array are connected to form an even bit line (denoted as BLE) which is connected to the output terminal of the even bit line selection module. The transistor array is connected to all transistor sources in a column to form a source line (denoted as SL). And the output end of the odd bit line selection module and the output end of the even bit line selection module are connected with the input end of the current subtraction module. The output end of the current subtraction module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the digital-to-analog conversion module.
The word line selection module comprises a word line selection decoder and a word line level conversion circuit. The input end of the word line selection decoder is connected with the word line address signal, and the output end of the word line selection decoder is connected with the input end of the word line level conversion circuit in a one-to-one correspondence mode. The output ends of the word line level conversion circuits are correspondingly connected with the word lines of the transistor array one by one.
The odd bit line selection module includes an odd bit line selection decoder and an odd bit line level shifter circuit. The input end of the odd bit line selection decoder is connected with an odd bit line address signal, and the output end of the odd bit line selection decoder is connected with the input end of the odd bit line level conversion circuit in a one-to-one correspondence mode. The output ends of the odd bit line level conversion circuits are correspondingly connected with the odd bit lines of the transistor array one by one.
The even bit line selection module comprises an even bit line selection decoder and an even bit line level conversion circuit. The input end of the even bit line selection decoder is connected with the even bit line address signal, and the output end of the even bit line selection decoder is connected with the input end of the even bit line level conversion circuit in a one-to-one correspondence mode. The output ends of the even bit line level conversion circuits are correspondingly connected with the even bit lines of the transistor array one by one.
The current subtraction module comprises an odd-even row current mirror subtraction circuit, an odd-even row current mirror subtraction circuit and an even-even row current mirror subtraction circuit. The input end of the odd-even row current mirror subtraction circuit is connected with the odd bit line and the even bit line in the same column, and the output end of the odd-even row current mirror subtraction circuit is connected with the input end of the current-voltage conversion module. The input end of the odd row odd-even column current mirror subtraction circuit is connected with the odd bit lines of every two adjacent columns in the transistor array, and the output end of the odd row odd-even column current mirror subtraction circuit is connected with the input end of the current-voltage conversion module. The input end of the even row odd-even column current mirror subtraction circuit is connected with the even bit lines of every two adjacent columns in the transistor array, and the output end of the even row odd-even column current mirror subtraction circuit is connected with the input end of the current-voltage conversion module. The output end of the current-voltage conversion module is connected with the input end of the digital-to-analog conversion module.
The word line of the transistor array formed by the composite gate dielectric transistors corresponds to a word line selection module, and a unique word line selection decoder is arranged in the word line selection module. The odd bit line of the transistor array formed by a plurality of composite gate dielectric transistors corresponds to an odd bit line selection module, and a unique odd bit line selection decoder is arranged in the odd bit line selection module. The even bit lines of the array formed by the multiple composite gate dielectric transistors correspond to one even bit line selection module, and a unique even bit line selection decoder is arranged in the even bit line selection module. A transistor array formed by a plurality of composite gate dielectric transistors corresponds to one current subtraction module. The odd bit line and the even bit line of each column in the transistor array formed by a plurality of composite gate dielectric transistors correspond to an odd-even row current mirror subtraction circuit. The odd bit lines of every two adjacent columns in the transistor array formed by a plurality of composite gate dielectric transistors correspond to an odd row odd-even column current mirror subtraction circuit. And the even bit lines of every two adjacent columns in the transistor array formed by a plurality of composite gate dielectric transistors correspond to one even row odd-even column current mirror subtraction circuit.
Preferably, the current-voltage conversion module is a capacitor module with a precharge function. The digital-to-analog conversion module is a single slope digital-to-analog converter.
In a read mode, word lines of two adjacent rows of the composite gate dielectric transistor array are controlled to be gated through a word line address signal in one read period, and all odd bit lines and all even bit lines of the composite gate dielectric transistor array are controlled to be gated through odd bit line address signals and even bit line address signals respectively.
As shown in fig. 2, taking WL <0>, WL <1> BLO <0>, BLO <1>, BLE <0>, BLE <1> gating as an example, four transistors (i.e. transistors in the 1 st row, 1 st column, 2 nd column, and 1 st column, 2 nd row, respectively denoted as M11, M12, M21, M22) located at the upper left corner of the composite gate dielectric transistor array are turned on, so that the conduction current enters the current subtraction module. Current subtraction of M11 and M21 and current subtraction of M12 and M22 are realized through an odd-even row current mirror subtraction circuit; current subtraction of M11 and M12 is realized through odd row odd-even column current mirror subtraction circuits; current subtraction of M21 and M22 is achieved by even row odd and even column current mirror subtraction circuits. The subtraction current output by the above is output by the current-voltage conversion module and the digital-to-analog conversion module.
Claims (7)
1. A row-column subtraction reading circuit based on a composite dielectric gate double-transistor photosensitive detector comprises a transistor array, a word line selection module, an odd bit line selection module, an even bit line selection module, a current subtraction module, a current-voltage conversion module and a digital-to-analog conversion module, wherein the transistor array is composed of a plurality of composite gate dielectric transistors; the drain electrodes of all transistors in odd rows and columns in the transistor array are connected to form odd bit lines, and the odd bit lines are connected with the output end of the odd bit line selection module; all transistor drains of even rows and columns in the transistor array are connected to form even bit lines and are connected with the output end of the even bit line selection module; all transistor source electrodes of the transistor arrays in the same column are connected to form a source line; the output end of the odd bit line selection module and the output end of the even bit line selection module are both connected with the input end of the current subtraction module, the output end of the current subtraction module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the digital-to-analog conversion module.
2. The row-column subtraction reading circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 1, wherein the word line selection module comprises a word line selection decoder and a word line level conversion circuit, wherein the input end of the word line selection decoder is connected with a word line address signal, and the output end of the word line selection decoder is connected with the input end of the word line level conversion circuit in a one-to-one correspondence manner; and the output end of the word line level conversion circuit is used as the output end of the word line selection module and is connected with the word lines of the transistor array in a one-to-one correspondence manner.
3. The row-column subtraction reading circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 1, wherein the odd bit line selection module comprises an odd bit line selection decoder and an odd bit line level conversion circuit, wherein the input end of the odd bit line selection decoder is connected with an odd bit line address signal, and the output end of the odd bit line selection decoder is connected with the input end of the odd bit line level conversion circuit in a one-to-one correspondence manner; and the output end of the odd bit line level conversion circuit is used as the output end of the odd bit line selection module and is connected with the odd bit lines of the transistor array in a one-to-one correspondence manner.
4. The row-column subtraction reading circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 1, wherein the even bit line selection module comprises an even bit line selection decoder and an even bit line level conversion circuit, wherein the input end of the even bit line selection decoder is connected with the even bit line address signal, and the output end of the even bit line selection decoder is connected with the input end of the even bit line level conversion circuit in a one-to-one correspondence manner; and the output end of the even bit line level conversion circuit is used as the output end of the even bit line selection module and is connected with the even bit lines of the transistor array in a one-to-one correspondence manner.
5. The row-column subtraction readout circuit based on the composite dielectric gate two-transistor photosensitive detector according to claim 1, wherein the current subtraction module comprises an odd-even row current mirror subtraction circuit, an odd-even row current mirror subtraction circuit and an even-even row odd-even column current mirror subtraction circuit; the input end of the odd-even row current mirror subtraction circuit is connected with the odd bit line and the even bit line in the same column, and the output end of the odd-even row current mirror subtraction circuit is used as the output end of the current subtraction module; the input end of the odd row odd-even column current mirror subtraction circuit is connected with the odd bit lines of every two adjacent columns in the transistor array, and the output end of the odd row odd-even column current mirror subtraction circuit is used as the output end of the current subtraction module; the input end of the even row odd-even column current mirror subtraction circuit is connected with the even bit lines of every two adjacent columns in the transistor array, and the output end of the even row odd-even column current mirror subtraction circuit is used as the output end of the current subtraction module and is connected with the input end of the current-voltage conversion module.
6. The row-column subtraction readout circuit based on the composite dielectric gate dual-transistor photosensitive detector as claimed in claim 1, wherein the current-voltage conversion module is a capacitor module with a pre-charge function, and the output terminal of the current-voltage conversion module is connected to the input terminal of a digital-to-analog conversion module, and the digital-to-analog conversion module is a single-slope digital-to-analog converter.
7. The row-column subtraction readout circuit of a composite dielectric gate two-transistor photosensitive detector according to claim 1, wherein the transistor array uses a current subtraction module; in a transistor array, one odd-even row current mirror subtraction circuit is used for odd bit lines and even bit lines of each column, one odd-even row current mirror subtraction circuit is used for odd bit lines of each two adjacent columns, and one even-even row current mirror subtraction circuit is used for even bit lines of each two adjacent columns.
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| CN213960195U (en) * | 2020-12-31 | 2021-08-13 | 南京威派视半导体技术有限公司 | Pixel merging circuit based on composite dielectric gate double-transistor photosensitive detector |
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2021
- 2021-11-10 CN CN202111323667.1A patent/CN114071041B/en active Active
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| US20110215227A1 (en) * | 2009-02-18 | 2011-09-08 | Feng Yan | Photosensitive Detector with Composite Dielectric Gate MOSFET Structure and Its Signal Readout Method |
| CN102938409A (en) * | 2012-11-07 | 2013-02-20 | 南京大学 | Composite dielectric grating metal-oxide-semiconductor field effect transistor (MOSFET) based dual-transistor light-sensitive detector and signal reading method thereof |
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