CN114068564A - Floating gate memory and preparation method thereof - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 64
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 230000005641 tunneling Effects 0.000 claims abstract description 61
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 230000000903 blocking effect Effects 0.000 claims description 38
- 238000002955 isolation Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 28
- 229910052582 BN Inorganic materials 0.000 claims description 13
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical group N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- ROUIDRHELGULJS-UHFFFAOYSA-N bis(selanylidene)tungsten Chemical compound [Se]=[W]=[Se] ROUIDRHELGULJS-UHFFFAOYSA-N 0.000 claims description 6
- -1 copper indium phosphorus sulfide Chemical compound 0.000 claims description 6
- 229910021389 graphene Inorganic materials 0.000 claims description 6
- NRJVMVHUISHHQB-UHFFFAOYSA-N hafnium(4+);disulfide Chemical compound [S-2].[S-2].[Hf+4] NRJVMVHUISHHQB-UHFFFAOYSA-N 0.000 claims description 6
- AKUCEXGLFUSJCD-UHFFFAOYSA-N indium(3+);selenium(2-) Chemical compound [Se-2].[Se-2].[Se-2].[In+3].[In+3] AKUCEXGLFUSJCD-UHFFFAOYSA-N 0.000 claims description 6
- MHWZQNGIEIYAQJ-UHFFFAOYSA-N molybdenum diselenide Chemical compound [Se]=[Mo]=[Se] MHWZQNGIEIYAQJ-UHFFFAOYSA-N 0.000 claims description 6
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000002207 thermal evaporation Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910001868 water Inorganic materials 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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Abstract
The invention provides a floating gate memory, which comprises a substrate, an insulating medium layer, a gate, a barrier layer, a gate contact material layer, a floating gate layer, a tunneling layer, a channel layer, an isolating insulating medium layer, a source electrode and a drain electrode, wherein the isolating insulating medium layer is formed at the part of one surface of the channel layer, which is opposite to the tunneling layer, so that the channel layer is prevented from being oxidized by air, and the reliability of the floating gate memory is further improved, the barrier layer, the floating gate layer, the tunneling layer, the channel layer and the isolating insulating medium layer are made of two-dimensional materials, the advantages of two-dimensional materials without a dangling bond can be utilized, the interface defect is reduced, the threshold voltage of the floating gate memory is reduced, the power consumption of the floating gate memory is further reduced, the charge in the channel layer is favorably captured by the floating gate layer due to the two-dimensional materials, thereby improving the erasing speed of the floating gate memory. The invention also provides a preparation method of the floating gate loss memory.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a floating gate memory and a preparation method thereof.
Background
The floating gate memory has longer storage time and service life, but the floating gate memory has higher working voltage in the erasing and writing process, so that the power consumption of the floating gate memory is higher, and a large number of interface dangling bonds exist on the surface of a silicon body of the traditional floating gate memory, so that the performance of the floating gate memory is seriously degraded, the reliability of the floating gate memory is reduced, and the further development of the floating gate memory is limited.
Therefore, there is a need to develop a new floating gate memory and a method for manufacturing the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a floating gate memory and a preparation method thereof, so as to reduce the power consumption of the floating gate memory and further improve the erasing speed and reliability of the floating gate memory.
In order to achieve the above object, the present invention provides a floating gate memory, which includes a substrate, an insulating medium layer, a gate, a blocking layer, a gate contact material layer, a floating gate layer, a tunneling layer, a channel layer, an isolating insulating medium layer, a source electrode and a drain electrode, wherein the insulating medium layer covers one surface of the substrate, the gate covers one surface of the insulating medium layer facing away from the substrate, the blocking layer covers a portion of one surface of the gate facing away from the insulating medium layer, the gate contact material layer covers a portion of one surface of the gate facing away from the insulating medium layer, the blocking layer is not in contact with the gate contact material layer, the floating gate layer covers one surface of the blocking layer facing away from the gate, the tunneling layer covers one surface of the floating gate layer facing away from the blocking layer, the channel layer covers one surface of the tunneling layer facing away from the floating gate layer, the isolation insulating medium layer covers the part of one surface, back to the tunneling layer, of the channel layer, the source electrode and the drain electrode cover the part of one surface, back to the tunneling layer, of the channel layer, and the source electrode and the drain electrode are oppositely arranged on two sides of the isolation insulating medium layer, wherein the grid electrode, the blocking layer, the floating gate layer, the tunneling layer, the channel layer and the isolation insulating medium layer are made of two-dimensional materials.
The floating gate memory has the beneficial effects that: the grid covers one surface of the insulating medium layer, which is back to the substrate, the blocking layer covers the part of one surface of the grid, which is back to the insulating medium layer, the floating gate layer covers one surface of the blocking layer, which is back to the grid, the tunneling layer covers one surface of the floating gate layer, which is back to the blocking layer, the channel layer covers one surface of the tunneling layer, which is back to the floating gate layer, and the isolation insulating medium layer covers the part of one surface of the channel layer, which is back to the tunneling layer, wherein the grid, the blocking layer, the floating gate layer, the tunneling layer, the channel layer and the isolation insulating medium layer are made of two-dimensional materials, and the isolation insulating medium layer made of the two-dimensional materials is arranged on one surface of the channel layer, which is back to the tunneling layer, so that the channel layer is prevented from being oxidized by air, and the reliability of the floating gate memory is improved, by forming the grid electrode, the blocking layer, the floating gate layer, the tunneling layer and the channel layer which are made of two-dimensional materials, the advantages of two-dimensional materials without dangling bonds can be utilized, the interface defect is reduced, the threshold voltage of the floating gate memory is reduced, the power consumption of the floating gate memory is further reduced, the material of the channel layer is two-dimensional materials, the charges in the channel layer are captured by the floating gate layer, and the erasing speed of the floating gate memory is further improved.
Optionally, the insulating dielectric layer is made of boron nitride. The beneficial effects are that: the channel layer can be prevented from being oxidized by air, and the reliability of the floating gate memory is improved.
Optionally, the material of the blocking layer and the tunneling layer is at least one of copper indium phosphorus sulfide and boron nitride. The beneficial effects are that: the advantage that two-dimensional materials of copper, indium, phosphorus, sulfur and boron nitride have no dangling bonds can be utilized, the interface defect is reduced, the threshold voltage of the floating gate memory is reduced, and the power consumption of the floating gate memory is further reduced.
Optionally, the floating gate layer and the channel layer are made of any one of indium selenide, hafnium disulfide, molybdenum disulfide, tungsten diselenide, and molybdenum diselenide. The beneficial effects are that: the floating gate memory is beneficial to trapping charges in the channel layer by the floating gate layer, and the erasing speed of the floating gate memory is improved.
Optionally, the gate is made of graphene. The beneficial effects are that: the advantage of no dangling bond of the two-dimensional material graphene can be utilized, the interface defect is reduced, the threshold voltage of the floating gate memory is reduced, and the power consumption of the floating gate memory is further reduced.
Optionally, the substrate is made of silicon, and the insulating medium layer is made of silicon dioxide.
Optionally, the source electrode, the drain electrode and the gate contact material layer are made of any one of a Ti/Au stack, a Cr/Au stack and a Ti/Pt stack.
The invention also provides a preparation method of the floating gate loss memory, which comprises the following steps:
s1: providing a substrate, forming an insulating medium layer on one surface of the substrate, and then forming a grid on one surface of the insulating medium layer, which is opposite to the substrate, wherein the grid is made of a two-dimensional material;
s2: forming a blocking layer on the part of one surface of the grid electrode, which is back to the insulating medium layer, then forming a floating gate layer on the surface of the blocking layer, which is back to the grid electrode, then forming a tunneling layer on the surface of the floating gate layer, which is back to the blocking layer, then forming a channel layer on the surface of the tunneling layer, which is back to the floating gate layer, and then forming an isolating insulating medium layer on the part of one surface of the channel layer, which is back to the tunneling layer, wherein the blocking layer, the floating gate layer, the tunneling layer, the channel layer and the isolating insulating medium layer are made of two-dimensional materials;
s3: and forming a source electrode and a drain electrode which are oppositely arranged at two sides of the isolation insulating medium layer on the part of one surface of the channel layer, which is opposite to the tunneling layer, and then forming a grid electrode contact material layer which is not in contact with the barrier layer on the part of one surface of the grid electrode, which is opposite to the insulating medium layer.
The preparation method of the floating gate loss memory has the advantages that: forming a grid on one surface of the insulating medium layer, which is opposite to the substrate, wherein the grid is made of a two-dimensional material; forming a blocking layer on the part of one surface of the grid electrode, which is back to the insulating medium layer, then forming a floating gate layer on the surface of the blocking layer, which is back to the grid electrode, then forming a tunneling layer on the surface of the floating gate layer, then forming a channel layer on the surface of the tunneling layer, which is back to the floating gate layer, then forming an isolation insulating medium layer on the part of one surface of the channel layer, which is back to the tunneling layer, and arranging the isolation insulating medium layer made of a two-dimensional material on the surface of the channel layer, which is back to the tunneling layer, so that the channel layer is prevented from being oxidized by air, and the reliability of the floating gate memory is improved The floating gate layer, the tunneling layer and the channel layer can utilize the advantage of two-dimensional material without a dangling bond, reduce interface defects, reduce the threshold voltage of the floating gate memory and further reduce the power consumption of the floating gate memory, and the material of the channel layer is two-dimensional material and is beneficial to trapping charges in the channel layer by the floating gate layer, so that the erasing speed of the floating gate memory is improved.
Optionally, the step S1 further includes: cleaning the substrate by acetone, ethanol and deionized water, and drying the cleaned substrate.
Optionally, the forming of the source and the drain on the surface of the channel layer opposite to the tunneling layer, the source and the drain being disposed on two sides of the isolation insulating medium layer, includes:
coating photoresist on the surface of the channel layer opposite to the tunneling layer, forming a source electrode pattern and a drain electrode pattern on the surface of the channel layer opposite to the photoresist by using an electron beam exposure machine, forming a source electrode on the surface of the source electrode pattern opposite to the channel layer by using an electron beam evaporation method or a thermal evaporation method, forming a drain electrode on the surface of the drain electrode pattern opposite to the channel layer, and arranging the source electrode and the drain electrode on the two sides of the isolation insulating medium layer.
Drawings
FIG. 1 is a schematic structural diagram of a floating gate memory according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a floating gate memory according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In order to solve the problems in the prior art, embodiments of the present invention provide a floating gate memory including a substrate, an insulating medium layer, a gate, a blocking layer, a gate contact material layer, a floating gate layer, a tunneling layer, a channel layer, an isolation insulating medium layer, a source electrode and a drain electrode, and a method for manufacturing the floating gate memory, so as to reduce power consumption of the floating gate memory and further improve erasing speed and reliability of the floating gate memory.
Fig. 1 is a schematic structural diagram of a floating gate memory according to an embodiment of the invention.
In the embodiment of the present invention, referring to fig. 1, the floating gate memory includes a substrate 200, an insulating medium layer 201, a gate 202, a blocking layer 203, a gate contact material layer 210, a floating gate layer 204, a tunneling layer 205, a channel layer 206, an isolation insulating medium layer 207, a source 208, and a drain 209, where the insulating medium layer 201 covers one surface of the substrate 200, the gate 202 covers one surface of the insulating medium layer 201 facing away from the substrate 200, the blocking layer 203 covers a portion of one surface of the gate 202 facing away from the insulating medium layer 201, the gate contact material layer 210 covers a portion of one surface of the gate 202 facing away from the insulating medium layer 201, the blocking layer 203 and the gate contact material layer 210 are not in contact, the floating gate layer 204 covers one surface of the blocking layer 203 facing away from the gate 202, the tunneling layer 205 covers one surface of the floating gate layer 204 facing away from the blocking layer 203, the channel layer 206 covers one surface of the tunneling layer 205 facing away from the floating gate layer 204, the isolation insulating medium layer 207 covers a portion of one surface of the channel layer 206 facing away from the tunneling layer 205, the source 208 and the drain 209 cover portions of one surface of the channel layer 206 facing away from the tunneling layer 205, the source 208 and the drain 209 are oppositely arranged on two sides of the isolation insulating medium layer 207, wherein the gate 202, the blocking layer 203, the floating gate layer 204, the tunneling layer 205, the channel layer 206 and the isolation insulating medium layer 207 are made of two-dimensional materials.
In some embodiments, the two-dimensional material refers to a material in which electrons are free to move only in two dimensions on the nanometer scale. Specifically, the two-dimensional material may be, but is not limited to, boron nitride, copper indium phosphorus sulfide, indium selenide, hafnium disulfide, molybdenum disulfide, tungsten diselenide, molybdenum diselenide, and graphene.
In some embodiments, the material of the isolation insulating dielectric layer is boron nitride.
In some embodiments, the material of the blocking layer and the tunneling layer is at least one of copper indium phosphorus sulfide and boron nitride.
In some embodiments, the material of the floating gate layer and the channel layer is any one of indium selenide, hafnium disulfide, molybdenum disulfide, tungsten diselenide, and molybdenum diselenide.
In some embodiments, the material of the gate is graphene.
In some embodiments, the substrate is made of silicon, and the insulating dielectric layer is made of silicon dioxide.
In some embodiments, the material of the source electrode, the drain electrode and the gate contact material layer is any one of a Ti/Au stack, a Cr/Au stack and a Ti/Pt stack.
Fig. 2 is a schematic flow chart of a method for manufacturing a floating gate memory according to an embodiment of the present invention.
Referring to fig. 1 and 2, the preparation method of the floating gate memory comprises the following steps:
s1: providing a substrate 200, forming an insulating medium layer 201 on one surface of the substrate 200, and then forming a gate 202 on one surface of the insulating medium layer 201 opposite to the substrate 200, wherein the gate 202 is made of a two-dimensional material;
s2: forming a blocking layer 203 on a portion of one surface of the gate 202 opposite to the insulating medium layer 201, then forming a floating gate layer 204 on a surface of the blocking layer 203 opposite to the gate 202, then forming a tunneling layer 205 on a surface of the floating gate layer 204 opposite to the blocking layer 203, then forming a channel layer 206 on a surface of the tunneling layer 205 opposite to the floating gate layer 204, and then forming an isolating insulating medium layer 207 on a portion of one surface of the channel layer 206 opposite to the tunneling layer 205, wherein the blocking layer 203, the floating gate layer 204, the tunneling layer 205, the channel layer 206 and the isolating insulating medium layer 207 are made of two-dimensional materials;
s3: a source 208 and a drain 209 which are oppositely arranged at two sides of the isolation insulating medium layer 207 are formed at a part of one surface of the channel layer 206, which is opposite to the tunneling layer 205, and then a gate contact material layer 210 which is not in contact with the barrier layer 203 is formed at a part of one surface of the gate 202, which is opposite to the insulating medium layer 201.
The technical solution of the present invention is explained in detail by specific examples below.
Embodiments provide a floating gate memory, which is a floating gate memory based on two-dimensional materials.
In some embodiments, referring to fig. 1, the step S1 includes: single crystal silicon is provided as the substrate 200 of the floating gate memory.
In some embodiments, referring to fig. 1, the step S1 further includes: the substrate 200 is cleaned by acetone, ethanol and deionized water, and then the cleaned substrate 200 is dried. Specifically, acetone, ethanol and deionized water are respectively used as solvents, ultrasonic cleaning is carried out in an ultrasonic cleaning machine for 15min to remove particles and organic impurities adsorbed on the surface of the substrate 200, and then the substrate 200 is placed in an oven to be dried.
In some embodiments, referring to FIG. 1, the oxidizing agent is O at a thermal oxidation temperature of 950 ℃2And H2O、O2Under the conditions that the flow rate is 50L/min and the thermal oxidation time is 2h, silicon dioxide is grown on one surface of the dried substrate 200 through a thermal oxidation method to serve as the insulating medium layer 201. In some alternative embodiments, silicon dioxide may also be formed on one side of the dried substrate 200 by a chemical vapor deposition method to serve as the insulating dielectric layer 201.
In some embodiments, referring to fig. 1, graphene is formed as the gate 202 on a side of the insulating dielectric layer 201 opposite to the substrate 200 by a mechanical lift-off method or a chemical vapor deposition method.
In some embodiments, referring to fig. 1, the step S2 includes: boron nitride is formed as the barrier layer 203 at a portion of the gate 202 on a side facing away from the insulating dielectric layer 201 by a mechanical lift-off method. In some alternative embodiments, at least one of boron nitride and copper indium phosphorus sulfide may be further formed on a portion of a side of the gate 202 facing away from the insulating dielectric layer 201 by a mechanical lift-off method to serve as the barrier layer 203.
In some embodiments, referring to fig. 1, indium selenide is formed as the floating gate layer 204 on a side of the barrier layer 203 opposite to the gate 202 by a mechanical lift-off process. In some alternative embodiments, any one of hafnium disulfide, molybdenum disulfide, tungsten diselenide, and molybdenum diselenide may be formed as the floating gate layer 204 on a side of the blocking layer 203 facing away from the gate 202 by a mechanical stripping method.
In some embodiments, referring to fig. 1, boron nitride is formed as the tunneling layer 205 on a side of the floating gate layer 204 opposite to the blocking layer 203 by a mechanical lift-off process. In some alternative embodiments, at least one of boron nitride and copper indium phosphorus sulfide may be formed on a side of the floating gate layer 204 facing away from the barrier layer 203 as the tunneling layer 205 by a mechanical lift-off method.
In some embodiments, referring to fig. 1, indium selenide is formed as the channel layer 206 on a side of the tunneling layer 205 facing away from the floating gate layer 204 by a mechanical lift-off process. In some alternative embodiments, any one of hafnium disulfide, molybdenum disulfide, tungsten diselenide, and molybdenum diselenide may be formed on a side of the tunneling layer 205 facing away from the floating gate layer 204 by a mechanical lift-off method to serve as the channel layer 206.
In some embodiments, referring to fig. 1, boron nitride is formed on a portion of a side of the channel layer 206 opposite to the tunneling layer 205 by a mechanical lift-off method to serve as the isolation insulating dielectric layer 207, so as to prevent the channel layer 206 from being oxidized by air and affecting the reliability of the floating gate memory.
In some embodiments, referring to fig. 1, the step S3 includes: coating photoresist on the surface of the channel layer 206 opposite to the tunneling layer 205, and exposing the photoresist by using an electron beam exposure machine to form a source electrode pattern and a drain electrode pattern on the surface of the channel layer 206 coated with the photoresist, wherein the source electrode pattern and the drain electrode pattern are oppositely arranged on two sides of the isolation insulating medium layer 207. Then, any one of a Ti/Au stack, a Cr/Au stack, and a Ti/Pt stack is formed on a surface of the source electrode pattern facing away from the channel layer 206 as the source electrode 208 by an electron beam evaporation method or a thermal evaporation method, and then any one of a Ti/Au stack, a Cr/Au stack, and a Ti/Pt stack is formed on a surface of the drain electrode pattern facing away from the channel layer 206 as the drain electrode 209, and the source electrode 208 and the drain electrode 209 are oppositely disposed on both sides of the isolation insulating medium layer 207.
In some embodiments, referring to fig. 1, a gate contact material layer 210 that is not in contact with the barrier layer 203 is formed on a portion of a side of the gate 202 facing away from the insulating medium layer 201 by an electron beam evaporation method or a thermal evaporation method, and the gate contact material layer 210 is made of any one of a Ti/Au stack, a Cr/Au stack, and a Ti/Pt stack.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A floating gate memory comprises a substrate, an insulating medium layer, a gate, a barrier layer, a gate contact material layer, a floating gate layer, a tunneling layer, a channel layer, an isolation insulating medium layer, a source electrode and a drain electrode, wherein the insulating medium layer covers one surface of the substrate, the gate covers one surface of the insulating medium layer opposite to the substrate, the barrier layer covers part of one surface of the gate opposite to the insulating medium layer, the gate contact material layer covers part of one surface of the gate opposite to the insulating medium layer, the barrier layer is not in contact with the gate contact material layer, the floating gate layer covers one surface of the barrier layer opposite to the gate, the tunneling layer covers one surface of the floating gate layer opposite to the barrier layer, the channel layer covers one surface of the tunneling layer opposite to the floating gate layer, and the isolation insulating medium layer covers part of one surface of the channel layer opposite to the tunneling layer, the source electrode and the drain electrode cover the part of one surface, back to the tunneling layer, of the channel layer, the source electrode and the drain electrode are oppositely arranged on two sides of the isolation insulating medium layer, and the grid electrode, the blocking layer, the floating grid layer, the tunneling layer, the channel layer and the isolation insulating medium layer are made of two-dimensional materials.
2. The floating gate memory of claim 1, wherein the material of the isolation dielectric layer is boron nitride.
3. The floating gate memory of claim 1, wherein the material of the blocking layer and the tunneling layer is at least one of copper indium phosphorus sulfide and boron nitride.
4. The floating gate memory according to claim 1, wherein the material of the floating gate layer and the channel layer is any one of indium selenide, hafnium disulfide, molybdenum disulfide, tungsten diselenide, and molybdenum diselenide.
5. The floating gate memory of claim 1, wherein the material of the gate is graphene.
6. The floating gate memory according to claim 1, wherein the substrate is made of silicon and the insulating dielectric layer is made of silicon dioxide.
7. The floating gate memory of claim 1, wherein the material of the source, the drain and the gate contact material layer is any one of a Ti/Au stack, a Cr/Au stack, and a Ti/Pt stack.
8. A method of manufacturing a floating gate memory according to any of claims 1-7, comprising the steps of:
s1: providing a substrate, forming an insulating medium layer on one surface of the substrate, and then forming a grid on one surface of the insulating medium layer, which is opposite to the substrate, wherein the grid is made of a two-dimensional material;
s2: forming a blocking layer on the part of one surface of the grid electrode, which is back to the insulating medium layer, then forming a floating gate layer on the surface of the blocking layer, which is back to the grid electrode, then forming a tunneling layer on the surface of the floating gate layer, which is back to the blocking layer, then forming a channel layer on the surface of the tunneling layer, which is back to the floating gate layer, and then forming an isolating insulating medium layer on the part of one surface of the channel layer, which is back to the tunneling layer, wherein the blocking layer, the floating gate layer, the tunneling layer, the channel layer and the isolating insulating medium layer are made of two-dimensional materials;
s3: and forming a source electrode and a drain electrode which are oppositely arranged at two sides of the isolation insulating medium layer on the part of one surface of the channel layer, which is opposite to the tunneling layer, and then forming a grid electrode contact material layer which is not in contact with the barrier layer on the part of one surface of the grid electrode, which is opposite to the insulating medium layer.
9. The method for manufacturing a floating gate memory according to claim 8, wherein the step S1 further comprises: cleaning the substrate by acetone, ethanol and deionized water, and drying the cleaned substrate.
10. The method for manufacturing a floating gate memory according to claim 8, wherein forming a source and a drain on a surface of the channel layer opposite to the tunneling layer, the source and the drain being disposed on two sides of the isolation insulating medium layer, comprises:
coating photoresist on the surface of the channel layer opposite to the tunneling layer, forming a source electrode pattern and a drain electrode pattern on the surface of the channel layer opposite to the photoresist by using an electron beam exposure machine, forming a source electrode on the surface of the source electrode pattern opposite to the channel layer by using an electron beam evaporation method or a thermal evaporation method, forming a drain electrode on the surface of the drain electrode pattern opposite to the channel layer, and arranging the source electrode and the drain electrode on the two sides of the isolation insulating medium layer.
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