CN113990925B - 一种提高耐压设计精度的暂态抑制二极管结构 - Google Patents

一种提高耐压设计精度的暂态抑制二极管结构 Download PDF

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CN113990925B
CN113990925B CN202111246229.XA CN202111246229A CN113990925B CN 113990925 B CN113990925 B CN 113990925B CN 202111246229 A CN202111246229 A CN 202111246229A CN 113990925 B CN113990925 B CN 113990925B
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伍伟
李岩松
陈勇
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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Abstract

本发明公开了一种提高耐压设计精度的暂态抑制二极管结构，该结构借助薄片工艺，对暂态抑制二极管的结构进行精确的设计与加工，在P+高掺杂区二次注入深结，引入曲率效应，以固定器件的击穿点，避免了器件在边缘及结终端等不期望发生击穿的结构处发生击穿而无法达到预设耐压的问题，从而实现通过调整器件尺寸与垂直掺杂来精确设计器件耐压的效果。相比常规的暂态抑制二极管，本方案所提出结构因在器件体内引入曲率效应，确保器件在体内发生击穿，增大了器件耐压的设计范围并确保了耐压精度。

Description

一种提高耐压设计精度的暂态抑制二极管结构
技术领域
本发明涉及半导体领域，具体涉及一种提高耐压设计精度的暂态抑制二极管结构。
背景技术
功率开关，如IGBTs，在逆变器的谐振或硬开关拓扑结构中使用时，如果发生负载故障或直流链路故障，可能会在集电极与发射极间产生并输出一个瞬态电压。该瞬态电压幅值很大，可能会超过功率开关的额定最大电压从而造成损坏。为了避免这种损坏的发生，可以采用某种形式的钳位电路，将电压控制在预设特定值。有源钳位电路通常选用单个符合耐压需求的暂态抑制二极管或在高耐压需求下串联预选好的暂态抑制二极管。
无论是选用单个暂态抑制二极管还是串联使用，由于半导体表面不规整以及受其他杂质污染的影响，器件往往在达到预设耐压前就在表面处或者结终端提前发生击穿，器件的设计耐压值难以得到保证。
发明内容
针对暂态抑制二极管可能在器件表面或者结终端发生提前击穿的问题，本发明提供了一种提高耐压设计精度的暂态抑制二极管结构。
本发明解决上述技术问题所采用的技术方案是：一种提高耐压设计精度的暂态抑制二极管结构，其元胞结构包括P型发射区(1)、N型场截止层(2)和N型基区(3)，位于N型基区(3)上方的N+区(4)和P+型高掺杂区(6)，在P+型高掺杂区(6)二次注入形成P型深结(5)。二次注入形成的P型深结(5)，在P+型高掺杂区(6)底部制造一个高曲率曲面。
进一步地，P+型高掺杂区再次注入形成一个P型深结，在P+型高掺杂区底部制造一个高曲率曲面，由于曲率效应，二极管体内的电场会在P型深结处形成一个尖峰，为器件最先发生击穿的部位，从而确定器件的击穿点，确保器件的耐压精度。
进一步地，该器件结构的长度WB可调节，从而对器件的耐压进行设计。
进一步地，该结构的P型发射区(1)掺杂浓度可调节，影响注入效率和雪崩击穿，进而影响耐压。
进一步地，该器件耐压可设计，可通过对器件的掺杂与尺寸进行调整设计耐压，用单个该二极管替代二极管串联结构以应对不同钳位电路的需求。
本发明的有益效果为：本发明公开了一种提高耐压设计精度的暂态抑制二极管结构，该结构借助薄片工艺，对暂态抑制二极管的结构进行精确的设计与加工，在P+高掺杂区二次注入深结，引入曲率效应，以固定器件的击穿点，避免了器件在边缘及结终端等不期望发生击穿的结构处发生击穿而无法达到预设耐压的问题，从而实现通过调整器件尺寸与垂直掺杂来精确设计器件耐压的效果。相比常规的暂态抑制二极管，本方案所提出结构因在器件体内引入曲率效应，确保器件在体内发生击穿，增大了器件耐压的设计范围并确保了耐压精度。
附图说明
图1为本发明器件的结构示意图；
图2为本发明结构内部电场分布示意图；
具体实施方式
下面对本发明的具体实施方式进行描述，以便于本技术领域的技术人员理解本发明，但应该清楚，本发明不限于具体实施方式的范围，对本技术领域的普通技术人员来讲，只要各种变化在所附的权利要求限定和确定的本发明的精神和范围内，这些变化是显而易见的，一切利用本发明构思的发明创造均在保护之列。
本发明提出了一种耐压可设计的暂态抑制二极管结构，其元胞结构包括P型发射区(1)、N型场截止层(2)和N型基区(3)，位于N型基区(3)上方的N+区(4)和P+型高掺杂区(6)，在P+型高掺杂区(6)二次注入形成P型深结(5)。二次注入形成的P型深结(5)，在P+型高掺杂区(6)底部制造一个高曲率曲面。
本发明的方案相对常规的暂态抑制二极管，提供一种提高耐压设计精度的暂态抑制二极管结构，使用薄片工艺，按照上述结构设计二极管器件结构。P+型高掺杂区再次注入形成一个P型深结，在P+型高掺杂区底部制造一个高曲率曲面，由于曲率效应，二极管内电场分布发生改变，在P型深结处形成电场尖峰，如图2所示，从而确定二极管的击穿点，避免器件在边缘或结终端发生提前击穿，使得器件可以通过对内部结构参数的设置来实现对耐压的精确设计。调节所提供二极管结构的P型发射区(1)掺杂浓度、N型基区(3)掺杂浓度可以改变器件的耐压，同时也可通过调整器件尺寸WB来改变器件耐压。调节N型基区(3)掺杂浓度和器件尺寸WB可改变二极管内的电场斜率以及电场面积，从而影响器件耐压。调节P型发射区(1)掺杂浓度会影响注入效率与雪崩击穿，从而影响器件耐压。通过对掺杂与器件尺寸的协同调节，实现对器件耐压的精确设计，同时借助所述主结的增强曲面确保器件在体内发生击穿，使器件的真实击穿电压接近设计击穿电压。
在一次实施例中，通过对本发明的器件尺寸进行设计，期望其耐压为500V，实验测得器件平均耐压值为496V，且经多次测试，器件均在在P+主结处发生击穿。对比耐压规格为500V的常规暂态抑制二极管，实际平均击穿电压为485V，且有三分之一的概率，器件在边缘或结终端处提前发生击穿。故可以说明本发明所提出的器件具有更高的耐压精度，可以固定器件击穿点，避免器件在边缘或结终端处提前发生击穿。
进一步地，P+型高掺杂区再次注入形成一个P型深结，在P+型高掺杂区底部制造一个高曲率曲面，由于曲率效应，二极管体内的电场会在P型深结处形成一个尖峰，为器件最先发生击穿的部位，从而确定器件的击穿点，确保器件的耐压精度。
进一步地，该器件结构的长度WB可调节，从而对器件的耐压进行设计。
进一步地，该结构的P型发射区(1)掺杂浓度可调节，影响注入效率和雪崩击穿，进而影响耐压。
进一步地，该器件耐压可设计，可通过对器件的掺杂与尺寸进行调整设计耐压，用单个该二极管替代二极管串联结构以应对不同钳位电路的需求。
综上所述，本发明提供了一种提高耐压设计精度的暂态抑制二极管结构，该结构借助薄片工艺，对暂态抑制二极管的结构进行精确的设计与加工，在P+高掺杂区二次注入深结，引入曲率效应，以固定器件的击穿点，避免了器件在边缘及结终端等不期望发生击穿的结构处发生击穿而无法达到预设耐压的问题，从而实现通过调整器件尺寸与垂直掺杂来精确设计器件耐压的效果。相比常规的暂态抑制二极管，本方案所提出结构因在器件体内引入曲率效应，确保器件在体内发生击穿，增大了器件耐压的设计范围并确保了耐压精度。

Claims (4)

1.一种提高耐压设计精度的暂态抑制二极管结构，其元胞结构包括P型发射区(1)、N型场截止层(2)和N型基区(3)，位于N型基区(3)上方的N+区(4)和P+型高掺杂区(6)，在P+型高掺杂区(6)二次注入形成P型深结(5)；P型深结(5)位于P+型高掺杂区(6)下方，且位于N+区(4)上方；二次注入形成的P型深结(5)，在P+型高掺杂区(6)底部制造一个高曲率曲面。
2.根据权利要求1所述的暂态抑制二极管结构，其特征在于，P+型高掺杂区再次注入形成一个P型深结，在P+型高掺杂区底部制造一个高曲率曲面，由于曲率效应，二极管体内的电场会在P型深结处形成一个尖峰，为器件最先发生击穿的部位，从而确定器件的击穿点，确保器件的耐压精度。
3.根据权利要求1所述的暂态抑制二极管结构，其特征在于，该结构的纵向长度WB可调节，从而对器件的耐压进行设计。
4.根据权利要求1所述的暂态抑制二极管结构，其特征在于，该结构的P型发射区(1)的掺杂浓度可调节，影响器件的注入效率和雪崩击穿，进而影响耐压。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004140158A (ja) * 2002-10-17 2004-05-13 Nec Kansai Ltd 静電サージ保護用ダイオード
CN101501856A (zh) * 2006-08-10 2009-08-05 威世通用半导体公司 具有降低击穿电压的低电压瞬态电压抑制器
CN105702677A (zh) * 2014-12-09 2016-06-22 万国半导体股份有限公司 用于高浪涌和低电容的tvs结构
WO2017135940A1 (en) * 2016-02-03 2017-08-10 Microsemi Corporation Sic transient voltage suppressor
CN210956686U (zh) * 2019-12-20 2020-07-07 力特半导体（无锡）有限公司 瞬变电压抑制二极管

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004140158A (ja) * 2002-10-17 2004-05-13 Nec Kansai Ltd 静電サージ保護用ダイオード
CN101501856A (zh) * 2006-08-10 2009-08-05 威世通用半导体公司 具有降低击穿电压的低电压瞬态电压抑制器
CN105702677A (zh) * 2014-12-09 2016-06-22 万国半导体股份有限公司 用于高浪涌和低电容的tvs结构
WO2017135940A1 (en) * 2016-02-03 2017-08-10 Microsemi Corporation Sic transient voltage suppressor
CN210956686U (zh) * 2019-12-20 2020-07-07 力特半导体（无锡）有限公司 瞬变电压抑制二极管

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