CN111565042B

CN111565042B - Correction method suitable for two-step ADC

Info

Publication number: CN111565042B
Application number: CN202010449123.9A
Authority: CN
Inventors: 宁宁; 孟昊; 邓恒; 张启辉; 李靖; 于奇
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-05-25
Filing date: 2020-05-25
Publication date: 2022-03-29
Anticipated expiration: 2040-05-25
Also published as: CN111565042A

Abstract

A correction method suitable for two-step ADC, while two-step ADC is carrying on the normal quantization, correct the clamp of the fine slope and operate and amplify the maladjustment at first, in order to dispel the maladjustment to the influence of the linearity; the slope and the weight value of the step voltage of the coarse slope are corrected by using the fine slope, the coarse slope is enabled to continuously rise after the quantization is finished by delaying the time of the third switch which is switched off after the quantization of the coarse slope is finished, the voltage loaded on the capacitor is enabled to approach the ideal voltage, the actual voltage weight loaded on the capacitor by the coarse slope is further quantized, and the corresponding cycle number is delayed by the coarse slope to compensate the voltage attenuation caused by the factors such as capacitor parasitic and the like, so that the linearity of the system is greatly improved, and the precision of the ADC is improved; during normal quantization, only the delay processing needs to be performed on the original coarse slope, no additional analog device is introduced, and no great influence is caused on the whole circuit area.

Description

Correction method suitable for two-step ADC

Technical Field

The invention belongs to the technical field of analog-digital conversion, and particularly relates to a correction method suitable for a two-step ADC.

Background

With the rapid development of the field of integrated circuits, the integration level of the integrated circuits is higher and higher, and higher precision and higher density are required for circuit design. In the communication industry, an analog-to-digital converter (ADC) as an interface for converting digital information and analog information becomes more important under the background of continuous attention and rapid development in the fields of image processing, environmental monitoring and the like. This requires that the analog-to-digital converter be capable of higher speeds and to a higher degree of accuracy. In practical analog-to-digital converter circuits, in addition to low power consumption, low integral non-linearity (INL), low differential non-linearity (DNL), high Spurious Free Dynamic Range (SFDR), high signal-to-noise-distortion ratio (SNDR), high sampling rates and high input bandwidths are required for analog-to-digital converters. However, due to the mismatch, parasitic, coupling, and noise effects of the devices and the limitation of the circuit area, the test result of the actual analog-to-digital converter cannot achieve the same effect as the simulation design value, which poses a serious challenge to designers of the analog-to-digital converter.

An N-bit two-step single-slope analog-to-digital converter is shown in fig. 1 and includes a slope generator V-Ramp101, a switched capacitor module 102, a comparator CMP103, and a digital control Logic module slope Logic 104. The ramp generator 101 is used for generating a coarse ramp VrampC and a fine ramp VrampF. Sampling capacitor C in switched capacitor module 102_SOne terminal (hereinafter referred to as an upper stage plate) is connected to the "+" terminal of the input of the comparator 103, and the capacitor C is sampled_SThe other end (hereinafter referred to as a lower stage plate) passes through the first switch

Connected to an input signal V_in. Holding capacitor C_HOne end of the sampling capacitor is connected with_SThe other end of the lower plate passes through a third switch

Connected to a bias voltage V_refOr through a fifth switch

Is connected to a fine ramp VrampF generated by a ramp generator. Coarse ramp Vramp through fourth switch

Connected to a sampling capacitor C_SAnd a lower plate. The input "-" terminal of the comparator 103 is connected to the common mode level V_T. The digital logic module 104 switches the switch array of the switched capacitor module 102 accordingly by processing the relevant signal.

In a two-step, single-slope analog-to-digital converter, the timing control thereof includes a sampling phase and a quantization phase.

A sampling stage, driven by the control signal, of the first switch

Second switch

And a third switch

Closed, by sampling the capacitance C_SFor input signal V_inAnd (6) sampling. At this time, the capacitor C is sampled_SThe lower board of (1) follows the input signal V_in. At the end of sampling, the second switch is first opened

Then the first switch is turned off

Then the input information is stored in the sampling capacitor C_SThe above.

Coarse quantization stage, fourth switch

Closed, sampling capacitor C_SThe lower board is connected to a coarse ramp VrampC. The voltage V at the + end of the comparator after the switch is switched can be known through charge conservation_PIs represented by formula (1):

in the formula, Q_S1Is a second switch

Injection of charge, V_rampCIs a coarse ramp step voltage. Comparator pair input signal V_inAnd continuously comparing the signal with the coarse slope signal and outputting a result. Generating an EOL signal when the comparator result is flipped, thereby controlling the third switch

Is turned off while the holding capacitor C is turned on_HThe coarse ramp comparison is recorded. The step voltage of the coarse slope continues rising until the coarse slope is reset, and then the fourth switch is switched on

And (5) disconnecting. At this point, the coarse quantization stage ends, and the digital logic module 104 records the digital code value code when the comparator flips₁As a result of the coarse quantization.

At this time, the fifth switch

Closed through a holding capacitor C_HAnd (5) accessing a fine ramp signal, and enabling the system to enter a fine quantization stage. At this time, the voltage at the "+" input terminal of the comparator is as shown in formula (2):

in the formula, V_FSAnd V_C-rollThe voltage is the reset voltage of the coarse slope and the step voltage of the coarse slope when the output of the comparator turns over, V_rampFFor fine slope step voltage value, C_C1Is a sampling capacitor C_SParasitic capacitance of one-end node of upper board, C_C2Is a sampling capacitor C_SParasitic capacitance of one-end node of lower board, C_C3Is a holding capacitor C_HAnd switch

The parasitic capacitance of the connection node. V_OSThe detuning value for the charge injection is shown in formula (3):

in the formula, Q_S2Is a third switch

Injection of charge, Q_S3Is a fourth switch

And injecting charges. The voltage of the fine slope quantization step is increased continuously until the output of the comparator is turned overGenerating EOLF signal in time conversion to obtain fine quantized code value code₂Code combined with higher coarse quantized code values₁A final quantization result is obtained and a corresponding code value is output. The system resets and waits for the next sampling signal and repeats the above process to continuously quantize the input signal. This is the working principle of such a two-step, single-slope analog-to-digital converter.

The two-step monoclinic analog-to-digital converter has the characteristics of small area, high precision, high speed and the like, but under the condition of not using correction, due to the influences of parasitic capacitance, charge injection and the like, the output of the whole analog-to-digital converter has large errors, so that the whole precision problem is caused.

As can be seen from the equation (1), the parasitic capacitance C is caused in the coarse quantization step_C1A gain factor is introduced. Because the input signal and the coarse ramp quantization voltage are simultaneously influenced by the coarse ramp quantization voltage, the comparison result does not cause the problem of linearity, and only the input signal is attenuated by a fixed proportion compared with an ideal condition during comparison.

Comparing equation (1) with equation (2), the inversion voltage of the coarse slope is further attenuated by the influence of the parasitic capacitance when the fine slope is quantized, and since the input signal is not influenced, the residual error of the system obtained by coarse quantization changes when the fine quantization starts. FIG. 2 is a schematic diagram showing comparison between the ideal loaded rough ramp step voltage and the actual loaded rough ramp step voltage, where V_FB、V_FTIn order to generate the minimum value and the maximum value of the coarse ramp voltage, the quantization range of the coarse ramp is obtained, and along with the continuous increase of the code value of the coarse ramp voltage, the voltage actually loaded on the capacitor is reduced very seriously after the coarse quantization is finished, and the integral linearity is seriously influenced. Further, when the code value is large, the difference between the voltage loaded on the capacitor and the ideal condition is above 1LSB voltage of the coarse slope, so that the quantization interval of the fine slope is not enough to complete quantization, and the overall accuracy is seriously affected.

It can be seen that due to the influence of the nonlinear parasitic capacitance of the device and the charge injection of the switch, the output result of the actual quantization is far from the theoretical design value, which affects the correctness of the quantization result, and finally, various performance indexes of the analog-to-digital converter are difficult to meet the requirements, including Integral Nonlinearity (INL), Differential Nonlinearity (DNL), and stray-free dynamic range (SFDR).

Disclosure of Invention

Aiming at the influence of nonlinear parasitic capacitance and charge injection on the conversion characteristic of the analog-to-digital converter in the two-step single-slope analog-to-digital converter, the invention provides a correction method suitable for the two-step ADC (analog-to-digital converter). in the method, a coarse slope is corrected by using a fine slope, and a third switch is used for delaying the quantization of the coarse slope after the quantization of the coarse slope is finished

The time of disconnection enables the coarse slope to continue rising after the quantization is finished, the voltage loaded on the capacitor is enabled to approach the ideal voltage, and then the actual voltage weight loaded on the capacitor by the coarse slope is further quantized through the fine slope; during normal quantization, the third switch is turned off according to the number of delay cycles obtained by correction after the result is obtained by coarse slope quantization

The final quantized coarse ramp result is combined with the corrected voltage weight and the fine ramp quantization result to obtain a relatively accurate actual output code value, so that nonlinearity caused by voltage attenuation loaded on a capacitor when the coarse ramp is disconnected is eliminated, and the overall accuracy is improved.

The technical scheme of the invention is as follows:

a correction method suitable for a two-step ADC comprises a slope generator, a switched capacitor module, a comparator and a logic module, wherein the slope generator is used for generating a coarse slope step voltage and a fine slope step voltage, the switched capacitor module comprises a sampling capacitor, a holding capacitor, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, one end of the sampling capacitor is connected with one end of the holding capacitor and is respectively connected with an input signal through the first switch and the coarse slope step voltage through the fourth switch, and the other end of the sampling capacitor is connected with a positive input end of the comparator and is connected with a common-mode signal through the second switch; the other end of the holding capacitor is connected with a bias signal through a third switch and the fine slope step voltage through a fifth switch respectively; the negative input end of the comparator is connected with the common-mode signal, and the logic module controls the first switch, the second switch, the third switch, the fourth switch and the fifth switch to be switched on and off according to the output signal of the comparator and generates a coarse quantization code value and a fine quantization code value;

the slope generator comprises a coarse slope generating unit and a fine slope generating unit, wherein in the step voltage of the coarse slope generated by the coarse slope generating unit, the step voltage of the 1 st coarse slope is used as a fine slope clamping offset adjustment correction redundancy bit, and the step voltage of the 2 nd coarse slope is used as the step voltage of the 2 nd coarse slope^M+2 bits coarse slope step voltage as coarse slope quantization step voltage, 2 nd^MThe + 3bit coarse slope step voltage is used as a coarse slope voltage offset redundancy bit until all the remaining coarse slope step voltages are used as coarse slope voltage offset redundancy bits; the 1 st bit fine slope step voltage to the 2 nd bit fine slope step voltage in the fine slope step voltage generated by the fine slope generating unit^LUsing the +1 bit fine slope step voltage as a fine slope quantization step voltage, wherein M + L-1 ═ N, M, L, N are positive integers, and N is the number of bits of the two-step ADC;

the fine slope generation unit comprises an upper end clamp operational amplifier and a lower end clamp operational amplifier, the input voltage range of the lower end clamp operational amplifier is a first reference voltage to a second reference voltage, the input voltage range of the upper end clamp operational amplifier is a second reference voltage to a third reference voltage, the difference value of the first reference voltage and the second reference voltage is 2MLSB, the difference value of the second reference voltage and the third reference voltage is 2MLSB, the MLSB is a coarse slope least significant bit, the upper end clamp operational amplifier and the lower end clamp operational amplifier generate the output end through resistance voltage division 2^L+1 bit fine slope step voltage;

the correction method suitable for the two-step ADC comprises the following steps:

step one, before the two-step ADC starts to quantize, correcting clamping operational amplifier offset of the fine slope generating unit;

a1, input voltage of the lower end clamping operational amplifierThe average division of the first reference voltage to the second reference voltage is 2^mSub-lower end clamp operational amplifier input voltage, equally dividing the input voltage of the upper end clamp operational amplifier from a second reference voltage to a third reference voltage into 2^mThe sub-upper end clamping operational amplifier input voltage, the phase difference voltage value between the two adjacent sub-lower end clamping operational amplifier input voltages and the two adjacent sub-upper end clamping operational amplifier input voltages is the minimum reference voltage, and m is a positive integer;

a2, setting the input voltage of the upper end clamping operational amplifier to be 2^mSetting the maximum value of the input voltage of the sub-upper end clamping operational amplifier, namely the third reference voltage, to be 2^mThe minimum value of the sub-lower end clamping operational amplifier input voltage is the first reference voltage;

a3, the coarse ramp generating unit generates the 1 st bit coarse ramp quantization step voltage, samples the 1 st bit coarse ramp quantization step voltage, loads the 1 st bit coarse ramp quantization step voltage to a holding capacitor, and carries out fine quantization to obtain a fine quantization code value C₁(ii) a Resetting the system, wherein the coarse slope generating unit generates the fine slope clamping operational amplifier offset correction redundant bit, samples the fine slope clamping operational amplifier offset correction redundant bit, the coarse slope generating unit generates a1 st bit coarse slope quantization step voltage, loads the 1 st bit coarse slope quantization step voltage to a holding capacitor, and performs fine quantization to obtain a fine quantization code value C₂；

A4, judgment C₁-C₂≤2^L-1If the voltage is not satisfied, the input voltage of the upper end clamping operational amplifier is set to be the input voltage of the sub upper end clamping operational amplifier, which is smaller than the current input voltage of the sub upper end clamping operational amplifier by one minimum reference voltage, the step A3 is repeated, and then the judgment C is carried out₁-C₂≤2^L-1If the voltage is not satisfied, the input voltage of the lower end clamp operational amplifier is set to be the input voltage of the sub-lower end clamp operational amplifier which is larger than the current input voltage of the sub-lower end clamp operational amplifier by one minimum reference voltage, the step A3 is repeated, and then the judgment C is carried out₁-C₂≤2^L-1Whether or not to becomeIf yes, turning to A5, and if not, repeating the step A4;

a5, maintaining the input voltage of the lower end clamp operational amplifier and the upper end clamp operational amplifier of the fine slope generation unit at present for generating the fine slope step voltage, and taking the voltage at 3/4 of the difference value of the input voltage of the upper end clamp operational amplifier and the input voltage of the lower end clamp operational amplifier at the moment as the voltage value of the bias voltage;

step two, correcting the slope of the step voltage of the rough slope: in sequence to the 2^MPerforming a delay correction operation on the +1 bit coarse slope quantization step voltage, wherein the i bit coarse slope quantization step voltage is subjected to the delay correction by a method as follows, i is a positive integer and i belongs to [1,2 ]^M+1]：

Sampling the ith bit of the coarse slope quantization step voltage, loading the ith bit of the coarse slope quantization step voltage to the sampling capacitor, and performing fine quantization to obtain a fine quantization code value

Judgment of

Whether the result is true or not; if the sampling capacitor is not satisfied, loading the (i + 1) th bit of the coarse slope quantization step voltage to the sampling capacitor, and performing fine quantization to update the fine quantization code value

Judge this moment

Whether the result is true or not; if the values are not satisfied, continuously and sequentially loading the (i + 2) th bit coarse slope quantization step voltage, the (i + 3) th bit coarse slope quantization step voltage and … … to the sampling capacitor and updating the fine quantization code value

Judging the value of the fine quantization code after each update

If it is true, when loading to the i + z th_iThe coarse slope quantization step voltage is positioned to the sampling capacitor, and the obtained updated fine quantization code value can enable the coarse slope quantization step voltage to be positioned to the sampling capacitor

When the fine quantization code value is satisfied, the fine quantization code value at that time is recorded

And a corresponding number of delay periods z_i；

The weight value of the ith bit of the coarse slope quantization step voltage participating in coarse quantization is recorded as W_iAnd the corresponding actual step number j after the ith coarse slope quantization step voltage is subjected to delay correction_i＝i+z_iIs given a weight of W_jThen, then

Step three, correcting the weight value of the step voltage of the coarse slope: in sequence to the 2^MPerforming weight value correction operation on the +1 bit coarse slope quantization step voltage to obtain the actual weight of each bit of coarse slope quantization step voltage, wherein the operation method of the i-1 th bit of coarse slope quantization step voltage is as follows:

sampling the (i-1) th bit of the coarse slope quantization step voltage, and delaying the ith bit of the coarse slope quantization step voltage by the delay period number z_iIs loaded on the holding capacitor after being delayed, and fine quantization is carried out to obtain a fine quantization code value

Then

The coupling formula (4) or (5) can be obtained

Since the 1 st bit of the coarse slope quantization step voltage has no error, the coarse slope quantization step voltage has no error

Are obtained in sequence by accumulation according to equation (6)

Obtaining said 2 according to formula (4) or formula (5)^MActual weight of +1 bit coarse ramp quantization step voltage

To

Step four, the correction phase is finished, the two-step ADC carries out normal quantization, and each quantization comprises a sampling phase and a quantization phase;

in the sampling stage, the first switch, the second switch and the third switch are closed, the fourth switch and the fifth switch are opened, the sampling capacitor samples the input signal, and then the second switch and the first switch are sequentially opened;

the quantization stage firstly carries out coarse quantization, the fourth switch is closed, and the coarse slope generation unit sequentially generates the 2^MComparing the +1 bit coarse slope quantization step voltage with the input signal, and when the k bit coarse slope quantization step voltage is compared with the input signal to turn over the comparator result, determining the delay period number z corresponding to the k bit coarse slope quantization step voltage in the second step_kAfter the delay, the third switch is switched off, and the logic module obtains a coarse quantization code value and the actual weight of the k bit coarse slope quantization step voltage determined in the third step

The multiplication yields the actual coarse quantized code value, where k is a positive integer and k ∈ [1,2 ]^M+1](ii) a The coarse slope generating unit resets, the fourth switch is switched off, the fifth switch is switched on for fine quantization, and the fine slope generating unit sequentially generates 2^LAnd comparing the +1 bit fine slope quantization step voltage with an input signal, obtaining a fine quantization code value at the moment when the comparator result is inverted, and obtaining a final quantization result of the current quantization by combining the actual coarse quantization code value obtained in the coarse quantization stage.

Specifically, in the fine ramp generating unit, the upper clamp operational amplifier includes m upper input switching tubes connected in parallel and respectively controlled by a first control signal of an m-bit binary code, an input voltage of the upper input switching tube correspondingly controlled by a code value of 1 in the m-bit binary code of the first control signal is the third reference voltage, an input voltage of the upper input switching tube correspondingly controlled by a code value of 0 in the m-bit binary code of the first control signal is the second reference voltage, and the first control signal is controlled from a maximum value

Sequentially transformed to minimum value

The input voltage of the upper end clamping operational amplifier is adjusted to be gradually reduced from the third reference voltage to the second reference voltage, and the adjustment value of each conversion is the minimum reference voltage;

the lower end clamping operational amplifier comprises m lower end input switching tubes connected in parallel and respectively controlled by second control signals of m-bit binary codes, the input voltage of the lower end input switching tube correspondingly controlled by a code value of 1 in the m-bit binary codes of the second control signals is the second reference voltage, the input voltage of the lower end input switching tube correspondingly controlled by a code value of 0 in the m-bit binary codes of the second control signals is the first reference voltage, and the second control signals are controlled from the minimum value

In turn, theTo maximum value

The input voltage of the lower-end clamping operational amplifier is adjusted to be gradually increased from the first reference voltage to the second reference voltage, and the adjustment value of each conversion is the minimum reference voltage.

Specifically, the ith bit of the coarse ramp quantization step voltage obtained in the second step and the corresponding delay period number z are stored by using a delay chain logic circuit_iThe delay chain logic circuit comprises n memories, n digital comparators and n D flip-flops, and z with the same value is compared_iStoring the maximum value of the step number i into a memory according to the number z of delay periods_iIs arranged from small to large, the number n of memories being dependent on the number z of delay periods_iDetermining the numerical condition of (1);

n memories respectively output the number z of the delay cycles stored therein_iThe corresponding step number i is sent to the first input end of the corresponding n digital comparators, output signals of the n digital comparators respectively control the n D triggers to be opened, and the n D triggers are cascaded to realize delay;

in the fourth step, the number z of delay cycles corresponding to the k bit coarse slope quantization step voltage needs to be determined_kWhen the number of the steps k is larger than or equal to the number of the steps i input by the first input end of the digital comparator, the digital comparator controls the D trigger corresponding to the digital comparator to be opened, otherwise, the D trigger corresponding to the digital comparator is closed, and z is zero_kThe D flip-flops are opened so that the signal to be delayed can be delayed by z after passing through the cascaded n D flip-flops_kA delay period.

Specifically, the signal to be delayed input by the n cascaded D flip-flops is a signal for controlling the third switch to be turned off.

Specifically, in the second step and the third step, when the voltage of the coarse slope step is sampled, the second switch, the third switch and the fourth switch are closed, the first switch and the fifth switch are opened, and after the sampling is finished, the second switch is opened first and then the fourth switch is opened; when the coarse slope step voltage is loaded, the third switch and the fourth switch are closed, the first switch, the second switch and the fifth switch are disconnected, and the third switch is disconnected after the coarse slope step voltage is loaded; and when the fine quantization is performed, the fourth switch is opened, and the fifth switch is closed.

The invention has the beneficial effects that: the correction method provided by the invention belongs to foreground correction, and corrects fine slope clamping operational amplifier disorder by sampling and quantizing a coarse slope initial step before a two-step ADC is normally quantized, so as to eliminate the influence of the disorder on linearity; then, the slope and the weight of the coarse slope are corrected through the corrected fine slope, and the voltage attenuation caused by factors such as capacitance parasitic factors is compensated by delaying the corresponding period number by the coarse slope, so that the linearity of the system is greatly improved, and the precision of the ADC is improved; during normal quantization, the correction method provided by the invention only needs to perform delay processing on the original coarse slope and does not introduce additional analog devices, so that the whole circuit area is not greatly influenced.

Drawings

Fig. 1 is a circuit schematic diagram of a two-step single-slope analog-to-digital converter.

Fig. 2 is a schematic diagram of comparison between an ideal loaded coarse ramp step voltage and an actual loaded coarse ramp step voltage of a two-step ADC.

Fig. 3 is a logic diagram of a calibration method for a two-step ADC according to the present invention.

Fig. 4 is a schematic circuit diagram of a ramp generator in a calibration method for a two-step ADC according to the present invention.

Fig. 5 is a schematic diagram of a delay chain logic circuit in a calibration method for a two-step ADC according to the present invention.

Fig. 6 is a schematic diagram of a weight correction operation of a correction method for a two-step ADC according to the present invention.

Fig. 7 is a schematic diagram of a comparison result of MATLAB simulation with and without correction by using the correction method for the two-step ADC according to the present invention.

Detailed Description

The technical scheme of the invention is further explained by embodiments in the following with reference to the attached drawings.

Fig. 3 is a logic block diagram of a calibration method suitable for a two-step ADC according to the present invention, which works before the two-step ADC performs normal quantization, and includes three parts, namely, calibrating fine slope clamp offset, calibrating coarse slope, and calibrating coarse slope weight, and includes the following steps:

step one, before the two-step ADC starts to quantize, correcting the clamping offset of the fine slope generating unit. Fig. 4 is a circuit diagram of a ramp generator, which includes a coarse ramp generating unit 401 and a fine ramp generating unit 402, where the coarse ramp performs high M-bit quantization, the fine ramp performs low L-1 bit quantization, the fine ramp has one redundant bit, M + L-1 ═ N, M, L, N are positive integers, and N is the number of bits of the two-step ADC. Of the coarse ramp step voltages generated by the coarse ramp generation unit 401, the 1 st bit coarse ramp step voltage VT_CAs a fine slope clamping operational amplifier offset correction redundant bit, the 2 nd bit coarse slope step voltage V_C<0>To 2 nd^M+2 bit coarse slope step voltage

As coarse ramp quantization step voltage, 2 nd^M+ 3bit coarse slope step voltage

And all the voltage of the coarse slope steps are remained to be used as the offset redundancy bit of the coarse slope voltage.

The 1 st bit fine slope step voltage V in the fine slope step voltage generated by the fine slope generating unit_F<0>To 2 nd^L+1 bit fine slope step voltage

As the fine ramp quantization step voltage, the fine ramp quantization range is twice as large as the coarse ramp least significant bit (hereinafter, referred to as MLSB). The fine ramp generation unit 402 includes an upper clamp op-amp and a lower clamp op-amp, in which the fine ramp generation needs to be correctedThe clamp operational amplifier of the generation unit 402 is de-regulated, as shown in fig. 4, the input voltage range of the lower clamp operational amplifier is from a first reference voltage to a second reference voltage, the input voltage range of the upper clamp operational amplifier is from a second reference voltage to a third reference voltage, wherein the difference between the first reference voltage and the second reference voltage is 2MLSB, the difference between the second reference voltage and the third reference voltage is 2MLSB, the MLSB is the least significant bit of the coarse slope, i.e. the input clamp voltage ranges of the fine slope clamp operational amplifier are both 2MLSB, and 2 is generated between the output ends of the upper clamp operational amplifier and the lower clamp operational amplifier through resistance voltage division^L+1 bit fine slope step voltage V_F<0>To

The specific steps for correcting the clamp operational amplifier offset of the fine ramp generation unit 402 are as follows:

a1, dividing the input voltage of the lower clamp operational amplifier from the first reference voltage to the second reference voltage into 2^mSub-lower end clamp operational amplifier input voltage, which is divided into 2 from the second reference voltage to the third reference voltage^mAnd the voltage difference value between the input voltage of the sub-upper end clamping operational amplifier and the input voltage of the adjacent two sub-lower end clamping operational amplifiers and the input voltage of the adjacent two sub-upper end clamping operational amplifiers is the minimum reference voltage, and m is a positive integer.

A2, setting the input voltage of the upper end clamp operational amplifier to be 2^mSetting the input voltage of the lower end clamping operational amplifier to be 2^mThe sub-lower end clamps the minimum value of the operational amplifier input voltage, namely the first reference voltage. The first control signal D of the present embodiment is obtained by m bits binary digital code value_Cal1Controlling the switching of m parallel upper input switching tubes of the upper clamp operational amplifier, passing through a second control signal D of m-bit binary digital values_Cal2Controlling the switching of m parallel lower end input switching tubes of the lower end clamping operational amplifier, and a first control signal D_Cal1The code value of 1 in the m-bit binary code is correspondingly controlled, and the input voltage of the upper-end input switching tube is the third parameterReference voltage, first control signal D_Cal1The code value of 0 in the m-bit binary code is correspondingly controlled, the input voltage of the upper end input switching tube is a second reference voltage, and a second control signal D_Cal2The code value of 1 in the m-bit binary code is correspondingly controlled, the input voltage of the lower-end input switching tube is a second reference voltage, and the second control signal D_Cal2The code value of 0 in the m-bit binary code is correspondingly controlled, and the input voltage of the lower-end input switching tube is a first reference voltage; first control signal D of m-bit binary digital code value_Cal1From the maximum

Sequentially transformed to minimum value

Thereby controlling the input voltage of the upper end clamping operational amplifier to be sequentially and gradually reduced to the minimum second reference voltage from the maximum third reference voltage, and the adjustment value of each conversion is the minimum reference voltage; second control signal D of m-bit binary digital code value_Cal2From a minimum value

Sequentially transformed into maximum values

Therefore, the input voltage of the lower end clamping operational amplifier is controlled to be sequentially and gradually increased from the minimum value first reference voltage to the maximum value second reference voltage, and the adjustment value of each conversion is the minimum reference voltage.

A3, coarse ramp generating unit 401 generates 1 st bit coarse ramp quantization step voltage V_C<0>Quantizing the step voltage V for the 1 st bit coarse slope_C<0>Sampling and quantizing the step voltage V of the 1 st bit coarse slope_C<0>Loaded into holding capacitor C_HThen fine quantization is carried out to obtain fine quantization code value C₁(ii) a The system is reset, the coarse slope generating unit 401 generates the fine slope clamp offset correction redundancy bit VT_CCorrecting the offset of the fine slope clamp operational amplifier to the redundancy bit VT_CSampling, and generating a1 st bit coarse slope quantization step voltage V by a coarse slope generation unit_C<0>And quantizing the 1 st bit coarse slope into a step voltage V_C<0>Loaded into holding capacitor C_HThen fine quantization is carried out to obtain fine quantization code value C₂。

A4, judgment C₁-C₂≤2^L-1If the voltage is not satisfied, the input voltage of the upper end clamping operational amplifier is set to be the input voltage of the sub upper end clamping operational amplifier which is smaller than the current input voltage of the sub upper end clamping operational amplifier by a minimum reference voltage, the step A3 is repeated, and then the judgment C is carried out₁-C₂≤2^L-1If the voltage is not satisfied, the input voltage of the lower end clamp operational amplifier is set to be the input voltage of the sub-lower end clamp operational amplifier which is larger than the current input voltage of the sub-lower end clamp operational amplifier by a minimum reference voltage, the step A3 is repeated, and then the judgment C is carried out₁-C₂≤2^L-1If true, go to A5, if true, repeat step A4 if false.

A5, C in this step₁-C₂≤2^L-1If yes, maintaining the input voltages of the lower end clamp operational amplifier and the upper end clamp operational amplifier of the current fine slope generation unit for generating a fine slope step voltage, and taking the voltage at 3/4 of the difference value of the input voltage of the upper end clamp operational amplifier and the input voltage of the lower end clamp operational amplifier at the moment as a bias voltage V_refThe voltage value of (2). I.e. bias voltage V_refIs the voltage at 3/4 of the fine ramp quantization range.

The correction idea of the fine slope clamp operational amplifier for offset correction in the embodiment is as follows: the initial code value of the input tube of the clamp operational amplifier at the upper end of the fine slope is controlled to be the highest value by the correction logic

The input voltage of the upper-end input switch tube is a third reference voltage, and the initial code value of the lower-end operational amplifier input tube is the minimum value

With lower end fed into the switching tubeThe input voltage is a first reference voltage. Firstly, step voltage V is quantized to the 1 st bit coarse slope_C<0>Sampling, and quantizing the step voltage V of the 1 st bit coarse slope_C<0>Loaded to a holding capacitor C_H. Then, fine quantization is carried out by using a fine slope to obtain a code value C₁. After the system is reset, the fine slope clamping operational amplifier offset correction redundancy bit VT generated by the coarse slope generation unit 401_CSampling, and quantizing the step voltage V of the 1 st bit coarse slope_C<0>Loaded to a holding capacitor C_H. Then, fine quantization is carried out by using a fine slope to obtain a code value C₂. Judgment C₁-C₂≤2^L-1If the value is not true, the code value-1 of the input tube of the fine slope upper end clamp operational amplifier is changed into

Namely, the input voltages of the first m-1 upper-end input switch tubes are all third reference voltages, the input voltage of the mth upper-end input switch tube is a second reference voltage, the process is repeated after the thin slope is regenerated, and if the first reference voltage is not the second reference voltage, the code value +1 of the thin slope lower-end clamping operational amplifier input tube is changed into the code value +1 of the thin slope lower-end clamping operational amplifier input tube

The input voltage of the first m-1 lower-end input switch tubes is a first reference voltage, the input voltage of the mth lower-end input switch tube is a second reference voltage, and the process is repeated after the thin slope is generated again; if the input code value is not satisfied, the code value of the input tube of the fine slope upper end clamping operational amplifier is changed into a code value of a code-1 again

Controlling the switching of input voltage of the corresponding upper-end input switch tube, repeating the process after regenerating the fine slope, and changing the code value of the fine-slope lower-end clamping operational amplifier input tube into the value of +1 again if the value is not true

And controlling the switching of the input voltage of the corresponding lower-end input switching tube, and repeating the process after the fine slope is regenerated. Repeating the above flowTo C₁-C₂≤2^L-1If true, the code value for the ideal difference between the coarse slope steps is 2^L-1The fine slope offset correction is realized by approximating the result of the subtraction of the two code values to the difference value in such a way that the fine slope clamping voltage is changed, so that a fine slope with a smaller quantization range and a tighter code value is generated to approximate an ideal fine slope curve. In the process, the coarse ramp code value is quantized by using a fine ramp, and a coarse ramp result is not needed. Subsequently maintained so that C₁-C₂≤2^L-1And when the fine slope operational amplifier is in the right state, the code value of the input tube is used for normally generating a fine slope, and the step two is carried out.

Step two, correcting the slope of the step voltage of the coarse slope: in sequence to 2^MAnd performing delay correction operation on the +1 bit coarse slope quantization step voltage, wherein the method for performing delay correction on the ith bit coarse slope quantization step voltage is as follows, i is a positive integer and i belongs to [1,2 ]^M+1]：

Sampling ith bit coarse slope quantization step voltage and loading the ith bit coarse slope quantization step voltage to a sampling capacitor C_HPerforming fine quantization to obtain fine quantization code value

Judgment of

Whether the result is true or not; if not, loading the (i + 1) th bit coarse slope quantization step voltage to the sampling capacitor C_HPerforming fine quantization update on the fine quantization code value

Judge this moment

Whether the result is true or not; if the voltage does not hold, continuously and sequentially loading the (i + 2) th bit coarse slope quantization step voltage, the (i + 3) th bit coarse slope quantization step voltage and … … to the sampling capacitor C_HAnd updates the fine quantization code value

Determining fine quantization code values after each update

If it is true, when loading to the i + z th_iBit coarse slope quantization step voltage to sampling capacitor C_HThe obtained updated fine quantization code value enables

And a corresponding number of delay periods z_iI.e. the number z of final loading steps increased compared to i_i。

For all 2^MAfter the +1 bit coarse ramp quantization step voltage is executed, as shown in fig. 5, the i-th bit coarse ramp quantization step voltage obtained in the second step and the corresponding delay cycle number z are stored by using the delay chain logic circuit_iThe delay chain logic circuit comprises a delay chain logic 503 consisting of n memories 501, n digital comparators 502 and n D triggers, wherein the input end of the memory 501 is connected with an external FPGA, the output end of the memory 501 is connected with the reverse input end of the digital comparator 502, and z with the same value is compared_iStoring the maximum value of the step number i into the same memory according to the delay period number z_iN memories are arranged in descending order of the number of the delay cycles z, the number n of the memories being determined by the number of the delay cycles z_iThe numerical condition of (2) is determined. Due to the delay z required for many steps_iAre equal and the required delay z increases with the number of steps_iWill gradually increase so that only z needs to be stored_iThe corresponding value of the coarse ramp code when increasing can be confirmed by the digital comparator as the delay number required by the current coarse ramp. n memories respectively output the number z of the delay cycles stored therein_iThe corresponding step number i is connected to the reverse input end of the corresponding n digital comparators, the coarse slope output code value is connected with the forward input end of the digital comparator 502, the output of the digital comparator 502 is connected with the control end of the delay chain 503, the input end of the delay chain 503 is a ratioThe output end of the EOL signal generated when the comparator 103 is turned over is the delayed EOL signal, n digital comparators 502 respectively control n D flip-flops to be turned on, and the n D flip-flops are cascaded to realize the delay of the EOL signal.

Obtaining z corresponding to each bit coarse slope quantization step voltage delay through the one-step correction_iOne cycle later loading to the holding capacitor C_HThen, the fine quantization range can be ensured to be quantized enough to obtain a correct result, and the weight value of the ith bit coarse slope quantization step voltage participating in coarse quantization is recorded as W_iActually loading the ith step to the holding capacitor C after corresponding delay_HThe step above is denoted as j_iThe corresponding actual step number j after the delay correction is carried out on the ith coarse slope quantization step voltage_iIs given a weight of W_jThen, then

Thereby solving the problem of loading the holding capacitor C_HThe difference between the voltage of the step and the voltage of the coarse slope quantization step is large, so that the quantization range of the fine slope is insufficient.

And then, correcting the weight value of the step voltage of the coarse slope in the third step: in sequence to 2^MAnd performing weight value correction operation on the +1 bit coarse slope quantization step voltage to obtain the actual weight of each bit coarse slope quantization step voltage, wherein the operation method of the i-1 th bit coarse slope quantization step voltage is as follows:

sampling the ith-1 bit coarse slope quantization step voltage, and acquiring the delay period number z corresponding to the ith bit coarse slope quantization step voltage according to the second step_iThe number z of delay cycles can be determined by comparing the value of i input to the digital comparator shown in FIG. 5 with the value of the memory_i. The ith bit coarse slope quantization step voltage is subjected to delay cycle number z_iIs loaded into the holding capacitor C after a delay_HUp, a coarse ramp is loaded to the holding capacitance C_HThe voltage on is the ith bit coarse ramp quantization step voltage after a corresponding delay period z_iI.e. applying a voltage of jth_iA step is subsequently carried outFine quantization to obtain fine quantized code values

Then

After each coarse slope is correspondingly operated, each bit is quantized finely to obtain a code value

To

And (6) outputting. The coupling formula (8) or (9) can be obtained

Because the 1 st bit coarse slope quantization step voltage has no error, the method has the advantages of high precision, high precision and low cost

Are obtained in sequence by accumulation according to equation (10)

Then obtaining 2 according to formula (8) or formula (9)^MStep j after correction of each step of +1 bit coarse slope quantization step voltage_iActually loaded to holding capacitance C_HActual weight of

To

After the steps are completed, the two-step ADC carries out normal quantization, and each quantization comprises a sampling stage and a quantization stage;

sampling phase, first switch

Second switch

And a third switch

Closed, fourth switch

And a fifth switch

Disconnecting and sampling capacitor C_SFor input signal V_inSampling, and subsequently sequentially opening the second switch

And a first switch

Then the input signal V_inIs stored in a sampling capacitor C_SThe above.

The quantization stage firstly carries out coarse quantization and closes the fourth switch

The coarse ramp generation unit 401 sequentially generates 2^M+1 bit coarse slope quantization step voltage and input signal V_inComparing the voltage of the k bit coarse slope quantization step with the input signal V_inWhen the comparison is carried out to ensure that the comparator result is turned over, the delay period number z corresponding to the k bit coarse slope quantization step voltage determined in the step two_kAfter the delay, an EOL signal is generated to switch the third switch

Disconnecting, the logic module obtains the coarse quantization code value and compares the coarse quantization code value with the k-th quantization code value determined in the third stepBit coarse ramp quantization step voltage actual weight

The multiplication yields the actual coarse quantized code value, where k is a positive integer and k e 1,2^M+1](ii) a Then the coarse slope generating unit is reset, and the fourth switch is switched off

Close the fifth switch

Performing fine quantization, the fine ramp generating unit 402 sequentially generates 2^L+1 bit fine slope quantization step voltage and input signal V_inComparing, generating EOLF signal to turn off the third switch when comparator result is inverted

And obtaining the fine quantization code value at the moment, and combining the actual coarse quantization code value obtained in the coarse quantization stage to obtain the final quantization result of the current quantization.

The operation of the present invention will be further described below by taking the example of quantizing 5bits with high bits and quantizing 7 bits with low bits.

As shown in fig. 4, the coarse ramp step voltage signal V generated by the resistor array of the coarse ramp generating unit 401_C<0～32>Is a coarse ramp quantization step voltage for coarse quantization operation; residual redundancy V_C<33～41>The voltage offset redundancy bit of the coarse slope is used for correcting voltage offset caused by disconnection of the coarse slope; voltage VT_CThe fine slope clamp operational amplifier offset correction redundancy bit is used for correcting charge injection and fine slope clamp operational amplifier offset. The coarse ramp voltage outputs a coarse ramp signal V to the outside through an output circuit_RC。

The fine ramp generating unit 402 quantizes 8 bits for one bit redundancy to correct the voltage offset caused by the coarse ramp being turned off. The resistor array of the fine ramp generation unit 402 generates a fine ramp quantization step voltage V_F<0～256>For fine quantization operation, fine ramp quantization step voltage passAn output circuit for outputting a fine ramp signal V_RF. In this embodiment, the input transistors of the upper-end clamp operational amplifier and the lower-end clamp operational amplifier of the fine slope generation unit 402 are each composed of a 6-bit DAC array, and the magnitude of the fine slope clamp voltage is controlled by a digital code value. The whole correction circuit works before the normal quantization of the system starts, the offset of the fine slope clamping operational amplifier is corrected in the first step, a clock control signal is input to the correction logic by the FPGA outside the step, and the correction logic controls a first control signal D of the fine slope upper end clamping operational amplifier_Cal1The initial code value is 63 at the maximum value, the corresponding binary code is 111111, namely, all input switch tube input voltages of the upper end clamping operational amplifier are connected to a third reference voltage V_C<18>Second control signal D of lower end clamp operational amplifier_Cal2The initial code value is the minimum value 0, the corresponding binary code is 000000, namely, all input switch tube input voltages of the lower end clamp operational amplifier are connected to the first reference voltage V_C<14>. In this example, get V_C<14>Is a first reference voltage, V_C<16>Is a second reference voltage, V_C<18>The third reference voltage can be adjusted according to requirements. The correction logic controls the coarse ramp generating unit 401 to access the input signal V_C<0>The generated 1 st bit coarse slope quantizes the step voltage, and simultaneously opens the second switch

Third switch

And a fourth switch

Disconnect the first switch

And a fifth switch

Quantizing the step voltage V of the 1 st bit coarse slope_C<0>Sampling is carried out, and the second switch is disconnected after sampling is finishedClosing device

Then the fourth switch is turned off

Third switch for loading 1 st bit coarse slope quantization step voltage

And a fourth switch

Closed, first switch

Second switch

And a fifth switch

Disconnecting the 1 st bit coarse slope quantization step voltage V_C<0>Loaded to a holding capacitor C_HSubsequently opening the third switch

Then, fine quantization is carried out by using a fine slope to obtain a code value C₁. The system reset post-correction logic controls the coarse ramp generation unit 401 to generate the fine ramp clamp operational amplifier offset correction redundancy bit VT_CWhile simultaneously turning on the second switch

Third switch

And a fourth switch

Offset correction of redundant bits VT for fine slope clamped operational amplifiers_CSampling is performed. Coarse slope riseThe third switch is turned off after one cycle

Quantizing the 1 st bit coarse slope into step voltage V_C<0>Loaded to a holding capacitor C_H. Then, fine quantization is carried out by using a fine slope to obtain a code value C₂. Judgment C₁-C₂≤2^L-1If the voltage is not satisfied, changing the code value-1 of the clamp operational amplifier input tube at the upper end of the fine slope into the corresponding binary code 111110, switching the switches of the input tube of the clamp operational amplifier unit at the upper end of the fine slope, and changing the input voltage of the input tube of the input switch corresponding to the binary code 0 from the third reference voltage V_C<18>Becomes the second reference voltage V_C<16>Repeating the process after regenerating the fine slope, changing the value of the input tube code of the clamp operational amplifier at the lower end of the fine slope to 000001 if the value of the input tube code of the clamp operational amplifier at the lower end of the fine slope is not satisfied, switching the input switch tube switch of the clamp operational amplifier at the lower end of the fine slope, and enabling the input voltage of the input switch tube corresponding to the binary code of 1 to be converted from the first reference voltage V_C<14>Instead, the second reference voltage V_C<16>The process is repeated after the fine ramp is regenerated. Repeating the above process until C₁-C₂≤2^L-1If so, the quantization range of the fine slope is about 2MLSB, the offset caused by the coarse slope clamp voltage and the fine slope clamp operational amplifier is eliminated, and the value of the input transistor of the fine slope operational amplifier is maintained to normally generate the fine slope. Simultaneously according to the current first control signal D through an external FPGA_Cal1And a second control signal D_Cal2Is calculated to obtain D_Cal0Control V_C<14>And V_C<18>The voltage at 3/4 is the bias voltage V, which is the voltage at the quantization range of the fine ramp_ref。D_Cal0Is a 7-bit DAC, pair D_Cal1Most significant complement 1 and D_Cal2The highest bit complement 0 can be regarded as V_C<14>To V_C<18>DAC code value of 7 bits in voltage interval by calculating D_Cal1And D_Cal2The difference between the two code values is 3/4 code value plus D_Cal2The code value of is the desired sum D_Cal2The DAC code value of.

Second step of correcting coarse slopeSlope, correction logic corrects the coarse ramp in sequence. Take the ith step as an example, turn on the second switch

Third switch

And a fourth switch

Disconnect the first switch

And a fifth switch

Sampling the ith step voltage value, and disconnecting the second switch after sampling

Then the fourth switch is turned off

First, the ith step value is loaded to the holding capacitor C_HThird switch

And a fourth switch

Closed, first switch

Second switch

And a fifth switch

Disconnecting, after loading the step voltage of the coarse slope, disconnecting the third switch

Then the coarse slope is reset, and the fourth switch is switched off

Close the fifth switch

Carrying out fine quantization to obtain code value

Judgment of

If not, after sampling the ith step voltage value, increasing the coarse slope step code value by one bit and then disconnecting the third switch

Loading the (i + 1) th step value to the holding capacitor C_HRepeating the fine quantization process, and continuously changing the loading step until

If the loading step is the (i + z) th step_iA step, then will be

And a coarse ramp step code value increment number z_iAnd outputting the output to an external FPGA. Due to the coarse slope loading to the holding capacitor C_HThe subsequent voltage decay increases with the coarse ramp step code value, so z_iIncreasing as the coarse ramp step code value increases. After all steps have been performed, the external FPGA will z, as shown in fig. 5_iThe step number i when increasing is stored in the memory DC from small to large₁，DC₂，…DC_nIn z_iThe corresponding i with the same numerical value is stored in the same memory, and one memory stores the maximum i value, and then the corresponding required delay number can be obtained by simple comparison.

And thirdly, correcting the weight value of the coarse slope, and sequentially performing correction operation on the voltages of all steps of the coarse slope except the redundancy bit. Take the i-1 st step as an example, turn on the second switch

Third switch

And a fourth switch

Disconnect the first switch

And a fifth switch

The i-1 th step voltage value is sampled, and the coarse ramp step code value i is input into the "+" terminal of the digital comparator shown in FIG. 5 to be compared with the value in the memory at the same time. When the step value of the rough slope is larger than or equal to the step value stored in the corresponding memory, the output of the digital comparator is 1 to control the corresponding D trigger to be opened, otherwise, the output of the digital comparator is 0 to close the corresponding D trigger, and z is the value_iThe D flip-flops are opened so that the EOL signal to be delayed can be delayed by z after passing through the n cascaded D flip-flops_iA delay period. E.g. as a digital comparator DC₁The output is 0, the NOR gate with the rightmost single-ended input inverted is opened, the delay number is 0, and the digital comparator DC is connected with the output of the inverter₂Output 0, digital comparator DC₁The output is 1, the NOR gate of the rightmost single-ended input inversion is closed, the NOR gate of the second single-ended input inversion of the right number is opened, and the like through the delay of a D flip-flop. Control the third switch

The EOL signal of the switch-off is at the corresponding cycle number z determined by the cascaded D flip-flops_iRear output control third switch

Cut off to load the coarse ramp to the holding capacitor C_HVoltage on has passed a corresponding delay period z_iI.e. applying a voltage of jth_iAnd (4) a step. Then obtaining code value by fine quantization

The result obtained by the refinement at this time is as shown in equation (12):

to be provided with

Is the origin of the fine-slope quantization result, thus

Is a negative value. After each coarse slope is correspondingly operated, code values obtained after each bit is finely quantized are output, and the code values obtained through the second step and the third step of correction in an external FPGA are operated, as shown in the attached figure 6, and the operation result is shown as a formula (13):

since the first step of the coarse slope has no gain error

Thus can be obtained by accumulating

Then obtaining the actual weight of each step of the rough slope, and calculating the actual weight in more than one way, which can be used as the basisThe flexible application is carried out according to the above formula. Because the final quantization result is actually loaded in the holding capacitor C_HThe upper voltage weight and the result of the fine slope quantization are combined, so that the corrected step j of each bit step needs to be obtained_iActually loaded to holding capacitance C_HThe actual weight of (c). The results are shown in equation (14):

the correction stage is finished, the system starts to normally work, when the system is normally quantized, the coarse quantization is finished, after the comparator generates an EOL signal, the current coarse slope step code value is compared with the record value in the memory through the digital comparator, the EOLR signal is output after the EOL signal is delayed by the corresponding period number, and the third switch is controlled by the EOLR signal

Turning off the storage coarse ramp voltage to the holding capacitor C_HThe above. Therefore, nonlinearity caused by factors such as capacitance parasitic factors is compensated, the external FPGA multiplies the coarse ramp code value by the corrected coarse ramp weight after receiving the digital code value, and a final output quantization result is obtained by combining the fine ramp quantization code value.

The data of ENOB and DNL/INL obtained by modeling the 12-bit two-step ADC in the embodiment through MATLAB are shown in figure 7, and the average value of ENOB of the two-step ADC is 4.83bits and the standard deviation is 0.09bit when the correction method provided by the invention is not used for correction by simulating 1000 Monte Carlo results. Compared with the situation of correction by using the correction method provided by the invention, the ENOB average value is improved to 10.85bits, and the standard deviation is 0.33 bits. The average value of the maximum DNL without correction under static simulation was 132.66LSB, the standard deviation was 1.55LSB, the average value of the maximum INL was 134.85LSB, and the standard deviation was 19.27 LSB. The mean of the maximum DNL using the correction is optimized to 0.7LSB, the standard deviation is optimized to 0.12LSB, the mean of the maximum INL is optimized to 1.84LSB, and the standard deviation is optimized to 0.59 LSB.

In summary, the calibration method for the two-step ADC according to the present invention completes the calibration process before the normal quantization, and corrects the offset by sampling the coarse slope start step, thereby eliminating the influence of the offset on the linearity. The coarse slopes are sampled and quantized one by utilizing the fine slopes, and the steps of the coarse slopes loaded on the holding capacitor are modified through delay processing, so that the quantization range of the fine quantization can cover all conditions. A set of data is re-quantized with fine quantization by re-sampling the coarse ramp one by one and adding the loaded coarse ramp voltage by one cycle over the previously stored delay. The external FPGA processes the quantization data twice to obtain a rough slope voltage step weight value actually loaded on the holding capacitor, so that a real weight value of a rough quantization step is obtained. During normal quantization, the algorithm only needs to perform delay processing on the original coarse slope, and no additional analog device is introduced, so that the whole circuit area is not greatly influenced.

Although the invention has been described above based on a two-step ADC calibration method, it is not intended to limit the invention, and those skilled in the art may make insubstantial changes or modifications without departing from the spirit of the invention.

Claims

1. A correction method suitable for a two-step ADC comprises a slope generator, a switched capacitor module, a comparator and a logic module, wherein the slope generator is used for generating a coarse slope step voltage and a fine slope step voltage, the switched capacitor module comprises a sampling capacitor, a holding capacitor, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, one end of the sampling capacitor is connected with one end of the holding capacitor and is respectively connected with an input signal through the first switch and the coarse slope step voltage through the fourth switch, and the other end of the sampling capacitor is connected with a positive input end of the comparator and is connected with a common-mode signal through the second switch; the other end of the holding capacitor is connected with a bias signal through a third switch and the fine slope step voltage through a fifth switch respectively; the negative input end of the comparator is connected with the common-mode signal, and the logic module controls the first switch, the second switch, the third switch, the fourth switch and the fifth switch to be switched on and off according to the output signal of the comparator and generates a coarse quantization code value and a fine quantization code value;

the slope generator is characterized by comprising a coarse slope generating unit and a fine slope generating unit, wherein in the step voltage of the coarse slope generated by the coarse slope generating unit, the step voltage of the 1 st bit coarse slope is used as a fine slope clamping operational amplifier offset correction redundancy bit, and the step voltage of the 2 nd bit coarse slope is used as the step voltage of the 2 nd bit coarse slope to the 2 nd bit coarse slope^M+2 bits coarse slope step voltage as coarse slope quantization step voltage, 2 nd^MThe + 3bit coarse slope step voltage is used as a coarse slope voltage offset redundancy bit until all the remaining coarse slope step voltages are used as coarse slope voltage offset redundancy bits; the 1 st bit fine slope step voltage to the 2 nd bit fine slope step voltage in the fine slope step voltage generated by the fine slope generating unit^LUsing the +1 bit fine slope step voltage as a fine slope quantization step voltage, wherein M + L-1 ═ N, M, L, N are positive integers, and N is the number of bits of the two-step ADC;

a1, dividing the input voltage of the lower end clamp operational amplifier into 2 from the first reference voltage to the second reference voltage^mSub-lower end clamp operational amplifier input voltage, input of the upper end clamp operational amplifierThe voltage is divided into 2 from the second reference voltage to the third reference voltage^mThe sub-upper end clamping operational amplifier input voltage, the phase difference voltage value between the two adjacent sub-lower end clamping operational amplifier input voltages and the two adjacent sub-upper end clamping operational amplifier input voltages is the minimum reference voltage, and m is a positive integer;

A4, judgment C₁-C₂≤2^L-1If the voltage is not satisfied, the input voltage of the upper end clamping operational amplifier is set to be the input voltage of the sub upper end clamping operational amplifier, which is smaller than the current input voltage of the sub upper end clamping operational amplifier by one minimum reference voltage, the step A3 is repeated, and then the judgment C is carried out₁-C₂≤2^L-1If the voltage is not satisfied, the input voltage of the lower end clamp operational amplifier is set to be the input voltage of the sub-lower end clamp operational amplifier which is larger than the current input voltage of the sub-lower end clamp operational amplifier by one minimum reference voltage, the step A3 is repeated, and then the judgment C is carried out₁-C₂≤2^L-1If yes, turning to A5, if not, repeating the step A4;

Judgment of

Judge this moment

Judging the value of the fine quantization code after each update

If it is true, when loading to the i + z th_iQuantizing step electricity by bit the coarse slopePressing on the sampling capacitor, the updated fine quantization code value obtained enables

And a corresponding number of delay periods z_i；

Then

The combination of formula (1) and (2) can be obtained

Are obtained in sequence by accumulation according to equation (3)

Obtaining said 2 according to formula (1) or formula (2)^MActual weight of +1 bit coarse ramp quantization step voltage

To

2. The method as claimed in claim 1, wherein the fine ramp generating unit includes m upper-end input switching transistors connected in parallel and controlled by a first control signal of m-bit binary code, the input voltage of the upper-end input switching transistor controlled corresponding to a code value of 1 in the m-bit binary code of the first control signal is the third reference voltage, the input voltage of the upper-end input switching transistor controlled corresponding to a code value of 0 in the m-bit binary code of the first control signal is the second reference voltage, and the first control signal is controlled from a maximum value

Sequentially transformed to minimum value

the lower end clamping operational amplifier comprises m lower end input switching tubes connected in parallel and respectively controlled by second control signals of m-bit binary codes, the input voltage of the lower end input switching tube correspondingly controlled by a code value of 1 in the m-bit binary codes of the second control signals is the second reference voltage, and the input voltage of the lower end input switching tube correspondingly controlled by a code value of 0 in the m-bit binary codes of the second control signals is the second reference voltageA reference voltage, which is controlled by the second control signal to be minimum

Sequentially transformed into maximum values

3. The calibration method according to claim 1 or 2, wherein the i-th bit of the coarse-ramp quantization step voltage obtained in the second step and the corresponding number z of delay cycles are stored by a delay chain logic circuit_iThe delay chain logic circuit comprises n memories, n digital comparators and n D flip-flops, and z with the same value is compared_iStoring the maximum value of the step number i into a memory according to the number z of delay periods_iIs arranged from small to large, the number n of memories being dependent on the number z of delay periods_iDetermining the numerical condition of (1);

4. The calibration method for two-step ADC according to claim 3, wherein the signal to be delayed inputted by the cascaded n D flip-flops is a signal for controlling the third switch to be turned off.

5. The calibration method for two-step ADC according to claim 1, wherein in the second step and the third step, when sampling the coarse ramp step voltage, the second switch, the third switch and the fourth switch are closed, the first switch and the fifth switch are opened, and the second switch is opened and then the fourth switch is opened after sampling; when the coarse slope step voltage is loaded, the third switch and the fourth switch are closed, the first switch, the second switch and the fifth switch are disconnected, and the third switch is disconnected after the coarse slope step voltage is loaded; and when the fine quantization is performed, the fourth switch is opened, and the fifth switch is closed.