CN113678231A - 用于形成金属间隙填充物的方法 - Google Patents
用于形成金属间隙填充物的方法 Download PDFInfo
- Publication number
- CN113678231A CN113678231A CN202080027926.3A CN202080027926A CN113678231A CN 113678231 A CN113678231 A CN 113678231A CN 202080027926 A CN202080027926 A CN 202080027926A CN 113678231 A CN113678231 A CN 113678231A
- Authority
- CN
- China
- Prior art keywords
- gap filler
- metal
- layer
- metal gap
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 134
- 239000002184 metal Substances 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims abstract description 97
- 239000000945 filler Substances 0.000 title claims abstract description 83
- 238000004544 sputter deposition Methods 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 claims description 27
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 239000010941 cobalt Substances 0.000 claims description 7
- 229910017052 cobalt Inorganic materials 0.000 claims description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 23
- 230000007547 defect Effects 0.000 abstract description 5
- 239000012530 fluid Substances 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 20
- 239000001257 hydrogen Substances 0.000 description 12
- 229910052739 hydrogen Inorganic materials 0.000 description 12
- 229910044991 metal oxide Inorganic materials 0.000 description 11
- 150000004706 metal oxides Chemical class 0.000 description 11
- 239000000356 contaminant Substances 0.000 description 9
- 230000015654 memory Effects 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 6
- 230000006911 nucleation Effects 0.000 description 6
- 238000010899 nucleation Methods 0.000 description 6
- 239000012071 phase Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000002002 slurry Substances 0.000 description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000011534 incubation Methods 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- -1 tungsten Chemical class 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910002451 CoOx Inorganic materials 0.000 description 2
- 229910016553 CuOx Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003599 detergent Substances 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- WIDQNNDDTXUPAN-UHFFFAOYSA-I tungsten(v) chloride Chemical compound Cl[W](Cl)(Cl)(Cl)Cl WIDQNNDDTXUPAN-UHFFFAOYSA-I 0.000 description 2
- 229910021580 Cobalt(II) chloride Inorganic materials 0.000 description 1
- 229910021592 Copper(II) chloride Inorganic materials 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910003074 TiCl4 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910008940 W(CO)6 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/02—Pretreatment of the material to be coated
- C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
- C23C14/025—Metallic sublayers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/04—Coating on selected surface areas, e.g. using masks
- C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
本公开内容一般涉及用于处理基板的方法,且更尤其涉及用于形成金属间隙填充物的方法。在一个实施方式中,该方法包括使用多步骤处理在开口中形成金属间隙填充物。多步骤处理包括:形成金属间隙填充物的第一部分,实行溅射处理以在一个或多个侧壁上形成一个或多个层,和使金属间隙填充物的第二部分生长以用金属间隙填充物来填充开口。通过多步骤处理形成的金属间隙填充物是无缝的,且形成在一个或多个侧壁上的一个或多个层密封在金属间隙填充物与侧壁之间的任何间隙或缺陷。由此,在后续处理中利用的流体不会扩散穿过金属间隙填充物。
Description
背景
领域
本公开内容的多个实施方式一般涉及基板的处理,且尤其涉及用于形成金属间隙填充物的方法。
相关技术说明
在半导体处理中,正在制造具有不断减小的特征尺寸的装置。随着装置尺寸不断缩小,且莫耳定律的二维尺寸限制无法克服,制造商转向三维结构以推进未来的成长。例如鳍式场效晶体管(FinFETs)的装置和例如动态随机存取存储器(DRAM)装置的三维存储器装置通常以堆叠中的不同材料的层为特征。多个装置或单元可彼此堆叠在另一个上面,且数个装置通常形成在一个基板上。这些层常常是不同的材料,所以一个结构可含有绝缘的、半导体的和金属的层的交替层,例如SiO2、SiN、a-Si和聚合Si。通常,这种堆叠由32或64或甚至128层的这些交替层组成。
例如钨这样的某些金属已经在逻辑应用中被用在触点级(contact level)约二十年。在近期先进的互补金属氧化物半导体(CMOS)装置中,已出现例如金属栅极和FinFET这样的新技术,而导致这些金属作为用于p型金属氧化物半导体(PMOS)和n型金属氧化物半导体(NMOS)装置二者的金属栅极填充物的新应用。在3D NAND装置中,这些金属也被用于金属栅极填充物。用于间隙填充物的要求(例如使用钨)由于几个原因而变得越来越具挑战性。例如,对于触点,随着触点的尺寸越来越小且因为钨的共形(conformal)填充物通常会留下缝隙(seam),悬垂(overhang)变得更具挑战性。另外,在化学机械抛光(CMP)期间缝隙将被暴露给浆料(slurry),这将造成整合(integration)问题。此外,对于先进的CMOS和3D NAND两者中的金属栅极沟槽,传统的钨共形生长不可避免地在中间留下缝隙。
因此,对于在先进的逻辑和存储装置中的触点和金属栅极填充物两者,需要一种形成金属间隙填充物的改良的方法。
发明内容
本公开内容的多个实施方式一般涉及用于基板的处理的方法,且尤其涉及用于形成金属间隙填充物的方法。在一个实施方式中,一种用于形成金属间隙填充物的方法包括:在第二层中形成的开口中,在第一层的表面之上形成金属间隙填充物的第一部分;在第一部分上实行溅射处理;和形成金属间隙填充物的第二部分,以用金属间隙填充物来填充开口。
在另一个实施方式中,一种用于形成金属间隙填充物的方法包括:在第二层中形成的开口中,在第一层的表面之上形成金属间隙填充物的第一部分;在第二层的一个或多个侧壁上形成一个或多个层;且形成金属间隙填充物的第二部分,以用金属间隙填充物来填充开口。
在另一个实施方式中,一种处理***包括:传送腔室;多个处理腔室,耦接至传送腔室;和控制器,构造成引发要在处理***中实行的处理,该处理包括:在第二层中形成的开口中,在第一层的表面之上形成金属间隙填充物的第一部分;在第一部分上实行溅射处理;和形成金属间隙填充物的第二部分,以用金属间隙填充物来填充开口。
附图说明
为了能详细理解本公开内容的上述特征,可参照多个实施方式来得到以上简要概述的本公开内容的更具体的说明,一些实施方式绘示在附图中。然而,需要注意,附图仅绘示本公开内容的多个示例性实施方式,而非用作本公开内容范围上的限制,本公开内容可容许其他多个等效实施方式。
图1是根据一个实施方式的用于形成金属间隙填充物的方法的流程图。
图2A-图2F示出根据一个实施方式的图1的方法的不同阶段期间的基板的各种视图。
图3是根据一个实施方式的适合用于实行图1的方法的示例性多腔室处理***的示意性俯视图。
为了便于理解,已尽可能地使用相同的附图标记标识这些图中共有的相同元件。需理解一个实施方式的多个元件和特征可在无进一步详述的情况下,有利地并入其他多个实施方式中。
具体实施方式
本公开内容一般涉及用于基板的处理的方法,且尤其涉及用于形成金属间隙填充物的方法。在能包括或与本文所述的一个或多个实施方式结合的一个实施方式中,这种方法包括使用多步骤处理在开口中形成金属间隙填充物。多步骤处理包括:通过选择性沉积处理使金属间隙填充物的第一部分生长,实行溅射处理以在一个或多个侧壁上形成一个或多个层,和通过选择性沉积处理使金属间隙填充物的第二部分生长,以用金属间隙填充物来填充开口。通过选择性沉积处理形成的金属间隙填充物是无缝的,且形成在一个或多个侧壁上的一个或多个层密封在金属间隙填充物与侧壁之间的任何间隙或缺陷。由此,在后续处理中利用的流体不会扩散穿过金属间隙填充物而与设置在金属间隙填充物下面的层相互作用。
图1是用于形成金属间隙填充物的方法100的流程图。图2A-图2F绘示在图1的方法100的不同阶段期间基板200的各种视图。应注意方法100可被利用以形成未在本文呈现的任何其他半导体结构。本领域技术人员应认识到,用于形成半导体装置和相关联结构的完整处理并未在这些附图中绘示或在本文中说明。尽管在这些附图中绘示各种操作且在本文中说明,但是并未暗示关于这些步骤的顺序或步骤存在或不存在的限制。除非明确说明,否则依序描绘或说明的操作仅是为了解释的目的而做的,不排除各个步骤实际上是以(如果不是整体地,则至少部分地)并发或重叠的方式实行的可能性。
方法100通过在处理腔室中在基板200上实行预清洁处理而在操作102处开始。在一个范例中,处理腔室是蚀刻腔室。如图2A中所示,基板200包括第一层202、在第一层202中形成的至少一个开口204和设置在开口204中的第二层206。第一层202可以是介电层,介电层是由SiO2、SiN、SiCN、Al2O3、AlN或其他适合的介电材料制成。或者,在硬模(hardmask)应用中,第一层202可以是碳层。开口204可以是过孔(via)或沟槽,且开口204被第二层206的表面210和第一层202的一个或多个侧壁212界定。开口204具有高度H1。第二层206可由导电材料制成,导电材料例如是金属、半导体、导电陶瓷或其他适合的导电材料。在一个范例中,第二层206由钴、氮化钛或硅制成。
预清洁处理在第二层206的表面210上实行。实行预清洁处理以移除第二层206的表面210上的污染物,例如金属氧化物、氟化物、碳、聚合物或其他蚀刻处理后残留物。预清洁处理可以是任何适合的清洁方法,例如化学清洁或等离子体清洁。化学清洁利用清洁剂或反应气体,清洁剂例如是氢自由基,反应气体例如是H2、CO、C2H5OH、WF6、WCl5或其他适合的反应气体。某些清洁剂,例如氢自由基、H2或CO,将金属氧化物污染物还原成金属。某些清洁剂,例如WF6或WCl5,通过将污染物挥发成气体来腐蚀污染物。在一个范例中,预清洁处理利用氢自由基以还原诸如CoOx、CuOx和/或WO3这样的金属氧化物。氢自由基可在远程等离子体源中形成,然后与氢气或氩气一起流动至基板200。基板200可维持在从约200摄氏度至约400摄氏度的范围的温度。在另一个范例中,预清洁处理利用H2热浸以还原诸如CoOx、CuOx和/或WO3这样的金属氧化物。热浸处理包括使氢气和氩气流至处理腔室中,腔室压强的范围从约30Torr至约300Torr,且基板200维持在从约300摄氏度至约600摄氏度的范围的温度。在另一个范例中,预清洁处理利用乙醇浸泡以还原金属氧化物,且基板200维持在从约200摄氏度至约400摄氏度的范围的温度。在另一个范例中,预清洁处理利用WF6或WCl5浸泡以与金属氧化物反应,且在高温和低压下将金属氧化物转换成气/液相金属化合物(例如,WOF4、CuCl2、CoCl2),且基板200维持在从约200摄氏度至约500摄氏度的范围的温度。
预清洁处理可以是等离子体清洁处理。等离子体清洁处理利用Ar/He等离子体或H2等离子体。一些等离子体清洁处理物理地将污染物溅射离开,而其他等离子体清洁处理强化反应以清洁表面210。在一个范例中,预清洁处理利用氩等离子体,且氩离子物理地溅射在第二层206的表面210上的污染物。氩等离子体可以被电容耦合、电感耦合或电容耦合与电感耦合的结合。等离子体频率的范围是从约350kHz至约40MHz,等离子体功率的范围是从约0W至约1000W,且腔室压强的范围是从约10mTorr至约100Torr。在另一个范例中,预清洁处理利用氢等离子体,且氢离子与第二层206的表面210上的污染物反应,以形成金属和水。氢等离子体清洁处理具有类似氢热浸的化学作用,但在氢等离子体清洁处理中利用更少的热能。
在一个范例中,使用远程等离子体源在处理腔室中实行预清洁处理。适合用于实行预清洁处理的一个范例处理腔室是可从美国加州圣克拉拉市的应用材料公司获得的AKTIV Pre-CleanTM腔室或清洁腔室。或者,在蚀刻腔室中实行预清洁处理,例如使用电感耦合等离子体(ICP)源的蚀刻腔室。一个范例蚀刻腔室可以是可从美国加州圣克拉拉市的应用材料公司获得的修改的解耦等离子体氮化(DPN)腔室。然而,应考虑来自其他制造商的其他被适当地构造的腔室也可实施以实行预清洁处理。
在操作104处,在第二层206的清洁后的表面210上实行成核处置(nucleationtreatment)。成核处置消除要在表面210上和在开口204中形成金属间隙填充物的孕育期(incubation period),且还消除晶格失配,因为在不同金属上的某种金属生长孕育是非常困难的。如图2B中所示,成核处置可包括在第二层206的表面210上形成金属种晶层(metalseed layer)214。金属种晶层214可由钨、钴、钌或其他适合的金属制成。金属种晶层214通过选择性处理形成,所以金属种晶层214并未形成在一个或多个侧壁212上。在一个范例中,金属种晶层214通过利用例如B2H6、SiH4、Si2H6、WF6、WCl5、TiCl4或其他适合的气体的一种或多种气体的化学浸泡处理来形成。在另一个范例中,金属种晶层214通过选择性金属原子层沉积(ALD)处理而形成。在选择性金属ALD处理中利用的一种或多种前驱物包括B2H6、WF6、H2、SiH4、WCl5、W(CO)6或其他适合的前驱物。在一些实施方式中,利用含有除了钨以外的金属的一种或多种气体。例如,可利用含钴或钌的气体以形成金属种晶层214。在一些实施方式中,省略成核处置且不存在金属种晶层214。
下一步,在操作106处,如图2C中所示,在金属种晶层214上形成金属间隙填充物的第一部分216。在一些实施方式中,金属间隙填充物的第一部分216形成在第二层206的表面210上。金属间隙填充物的第一部分216由金属制成,例如钨、钴、钌或其他适合的金属。第一部分216通过选择性处理形成,且从底部向上生长。换句话说,第一部分216选择性地形成在金属种晶层214或第二层206的表面210上,或从金属种晶层214或第二层206的表面210生长,且并未形成在一个或多个侧壁212上。如图2C中所示,第一部分216与一个或多个侧壁212的一部分接触,但第一部分216并未从一个或多个侧壁212生长。第一部分216具有高度H2,且高度H2是开口204的高度H1的约百分之十至约百分之五十。
用于形成第一部分216的选择性处理可以是化学气相沉积(CVD)处理,且选择性是基于腔室压强和前驱物气体的比例。在一个范例中,选择性处理包括使含金属气体和第二气体流至处理腔室中。含金属气体可以是任何适合的含金属气体,例如WF6。第二气体可以是氢气。第二气体与含金属气体的比例范围从约六比一至约八千比一。腔室压强的范围从约1Torr至约300Torr,且基板维持在从约200摄氏度至约500摄氏度的范围的温度。腔室压强和气体的比例能影响选择性。在一个范例中,在相对高的温度,例如大于约400摄氏度,当第二气体与含金属气体的比例是高的且腔室压强是低的时候,维持选择性。
下一步,在操作108处,如图2D中所示,实行溅射处理以移除金属间隙填充物的第一部分216的一些,且在一个或多个侧壁212上形成一个或多个层218。溅射处理可具有与利用氩等离子体的预清洁处理相同的处理条件。溅射处理将金属间隙填充物的第一部分216的一些溅射至一个或多个侧壁212上。由此,在每个侧壁212上形成层218。层218由与金属间隙填充物的第一部分216相同的材料制成。
下一步,在操作110处,如图2E中所示,在金属间隙填充物的第一部分216上形成金属间隙填充物的第二部分220。第二部分220可通过与用于金属间隙填充物的第一部分216的处理相同的处理形成。第二部分220由与第一部分216相同的材料制成。在开口204中形成的金属间隙填充物包括第一部分216、一个或多个层218和第二部分220。用于形成金属间隙填充物的多步骤是无缝的,且在金属间隙填充物与侧壁212之间不存在间隙或缺陷。由此,在后续处理中利用的流体不会扩散穿过金属间隙填充物而与第二层206作用。
下一步,在操作112处,如图2F中所示,在基板200上实行化学机械抛光(CMP)处理,以形成平坦表面222。在CMP处理期间,浆料不会扩散穿过具有第一部分216、层218和第二部分220的金属间隙填充物,因为侧壁212被层218密封。如此,在CMP处理中第二层206被保护不受浆料影响。
参照回图1,实行操作106、108和110以形成无缝金属间隙填充物,且在金属间隙填充物与侧壁之间不具有间隙或缺陷。在一些实施方式中,用单一操作取代操作106、108和110,而从底部向上形成单相晶体(single phase crystal)金属间隙填充物。单相晶体金属间隙填充物不具有任何形成在金属间隙填充物中的晶界,且金属间隙填充物的阻抗(resistivity)与开口204的尺寸无关。因此,单相晶体金属间隙填充物是无缝的且具有降低的电阻。单相晶体金属间隙填充物可通过CVD处理形成,其中基板200被维持在大于或等于450摄氏度的温度。
根据本文所提供的教示可适当修改的处理***的范例包括可从位于美国加州圣克拉拉市的应用材料公司商业上获得的或集成处理***,或其他适合的处理***。应考虑可应用其他处理***(包括来自其他制造商的处理***)以从本文所述的方面获益。图3示出根据本公开内容的多个实施方式的范例多腔室处理***300的示意性俯视图,范例多腔室处理***300能用于完成图1中绘示的方法100。如图3中所示,多个处理腔室302耦接至第一传送腔室304。第一传送腔室304还耦接至第一对直通腔室(pass-through chamber)306。第一传送腔室304具有中心设置的传送机械手(未图示),用于在直通腔室306和处理腔室302之间传送基板。直通腔室306耦接至第二传送腔室310,第二传送腔室310耦接至构造成实行例如操作102这样的预清洁处理的处理腔室314,和构造成实行例如操作106这样的成核处置操作的处理腔室316。第二传送腔室310具有中心设置的传送机械手(未图示),用于在一组负载锁定腔室312与处理腔室314或处理腔室316之间传送基板。工厂接口(factory interface)320通过负载锁定腔室312连接至第二传送腔室310。工厂接口320在与负载锁定腔室312的相对侧上耦接至一个或多个舱330。舱330通常是可从无尘室进出的前开式标准舱(FOUP)。
在操作期间,基板首先被传送至处理腔室314,在处理腔室314中实行例如操作102这样的预清洁处理,以移除诸如来自开口的底部的金属氧化物污染物之类的污染物。然后,基板被传送至处理腔室316,在处理腔室316中实行操作106。基板然后被传送至一个或多个处理腔室302,在一个或多个处理腔室302中实行操作106、108和110。因为所有的操作102、104、106、108和110都在同一处理***300中实行,所以真空不会随着基板被传送至各个腔室而被破坏,这减少了污染的机会且提高了金属间隙填充物的质量。
***控制器380耦接至处理***300,用于控制处理***300或控制处理***300的部件。例如,***控制器380可使用处理***300的腔室302、304、306、310、312、314、316的直接控制来控制处理***300的操作,或通过控制与腔室302、304、306、310、312、314、316相关联的控制器360来控制处理***300的操作。在操作中,***控制器380使得能够从各个腔室进行数据收集和反馈,以协调处理***300的性能。
***控制器380一般包括中央处理单元(CPU)382、存储器384和支持电路386。CPU382可以是能在工业环境中使用的任何形式的通用处理器的一种。存储器384、非暂时性计算机可读介质或机器可读存储装置,可通过CPU382存取且可以是一个或多个存储器,例如随机存取存储器(RAM)、只读存储器(ROM)、软盘、硬盘或数字储存的任何其他形式,不论是本地或远程。支持电路386耦接至CPU 382,且可包含高速缓冲存储器、时钟电路、输入/输出子***、电源和类似装置。***控制器380被构造成实行存储在存储器384中的方法100。在本公开内容中公开的各种实施方式一般可在CPU 382的控制下通过执行存储在存储器384中(或在特定处理腔室的存储器中)的计算机指令代码(作为例如计算机程序产品或软件程序)来实施。即,计算机程序产品实体地(tangibly)安装在存储器384(或非暂时性计算机可读取介质或机器可读取存储装置)上。当通过CPU 382执行计算机指令代码时,CPU 382控制腔室以实行根据各种实施方式的操作。
综上所述,本公开内容的多个实施方式使得能够形成无缝金属间隙填充物,该无缝金属间隙填充物避免任何流体穿过而扩散。该无缝金属间隙填充物通过多步骤处理形成,该多步骤处理包括:通过选择性沉积处理使金属间隙填充物的第一部分生长;实行溅射处理以在一个或多个侧壁上形成一个或多个层;和通过选择性沉积处理使金属间隙填充物的第二部分生长,以用金属间隙填充物来填充开口。通过选择性沉积处理形成的金属间隙填充物是无缝的,且在一个或多个侧壁上形成的一个或多个层密封在金属间隙填充物与侧壁之间的任何间隙或缺陷。由此,在后续处理中利用的流体不会扩散穿过金属间隙填充物。
尽管上述内容针对本公开内容的实施方式,可在不脱离本公开内容的基本范围的情况下,设计出本公开内容的其他和进一步实施方式,且本公开内容的范围通过随附权利要求来确定。
Claims (15)
1.一种用于形成金属间隙填充物的方法,所述方法包含以下步骤:
在第二层中形成的开口中,在第一层的表面之上形成所述金属间隙填充物的第一部分;
在所述第一部分上实行溅射处理;和
形成所述金属间隙填充物的第二部分,以用所述金属间隙填充物来填充所述开口。
2.如权利要求1所述的方法,其中所述金属间隙填充物的所述第一部分和所述金属间隙填充物的所述第二部分由钴、钨或钌制成。
3.如权利要求1所述的方法,其中
所述第一层包含金属,和
所述第二层包含介电层。
4.如权利要求1所述的方法,进一步包含以下步骤:在形成所述金属间隙填充物的所述第一部分之前,在所述第一层的所述表面上实行预清洁处理。
5.如权利要求4所述的方法,进一步包含以下步骤:在所述第一层的所述表面上形成金属种晶层,其中所述金属间隙填充物的所述第一部分形成在所述金属种晶层上。
6.如权利要求1所述的方法,其中所述溅射处理利用氩等离子体。
7.一种用于形成金属间隙填充物的方法,所述方法包含以下步骤:
在第二层中形成的开口中,在第一层的表面之上形成所述金属间隙填充物的第一部分;
在所述第二层的一个或多个侧壁上形成一个或多个层;和
形成所述金属间隙填充物的第二部分,以用所述金属间隙填充物来填充所述开口。
8.如权利要求7所述的方法,其中所述金属间隙填充物的所述第一部分、所述一个或多个层和所述金属间隙填充物的所述第二部分由钴、钨或钌制成。
9.如权利要求7所述的方法,其中
所述第一层包含金属,并且
所述第二层包含介电层。
10.如权利要求7所述的方法,进一步包含以下步骤:
在形成所述金属间隙填充物的所述第一部分之前,在所述第一层的所述表面上实行预清洁处理;和
在所述第一层的所述表面上形成金属种晶层,其中所述金属间隙填充物的所述第一部分形成在所述金属种晶层上。
11.如权利要求7所述的方法,其中所述一个或多个层通过利用氩等离子体的溅射处理形成。
12.一种处理***,包含:
传送腔室;
多个处理腔室,耦接至所述传送腔室;和
控制器,构造成引发要在所述处理***实行的处理,所述处理包括:
在第二层中形成的开口中,在第一层的表面之上形成金属间隙填充物的第一部分;
在所述第一部分上实行溅射处理;和
形成所述金属间隙填充物的第二部分,以用所述金属间隙填充物来填充所述开口。
13.如权利要求12所述的处理***,其中所述金属间隙填充物的所述第一部分和所述金属间隙填充物的所述第二部分的由钴、钨或钌制成。
14.如权利要求12所述的处理***,其中
所述第一层包含金属,并且
所述第二层包含介电层。
15.如权利要求12所述的处理***,进一步包含
在形成所述金属间隙填充物的所述第一部分之前,在所述第一层的所述表面上实行预清洁处理,和
在所述第一层的所述表面上形成金属种晶层,其中所述金属间隙填充物的所述第一部分形成在所述金属种晶层上。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962819697P | 2019-03-18 | 2019-03-18 | |
US62/819,697 | 2019-03-18 | ||
US16/803,842 | 2020-02-27 | ||
US16/803,842 US11355391B2 (en) | 2019-03-18 | 2020-02-27 | Method for forming a metal gapfill |
PCT/US2020/020696 WO2020190494A1 (en) | 2019-03-18 | 2020-03-02 | Method for forming a metal gapfill |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113678231A true CN113678231A (zh) | 2021-11-19 |
Family
ID=72513728
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202080027926.3A Pending CN113678231A (zh) | 2019-03-18 | 2020-03-02 | 用于形成金属间隙填充物的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11355391B2 (zh) |
JP (1) | JP2022527693A (zh) |
KR (1) | KR20210129243A (zh) |
CN (1) | CN113678231A (zh) |
TW (1) | TW202101547A (zh) |
WO (1) | WO2020190494A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11404313B2 (en) * | 2017-04-26 | 2022-08-02 | Applied Materials, Inc. | Selective tungsten deposition at low temperatures |
JP7182970B2 (ja) * | 2018-09-20 | 2022-12-05 | 東京エレクトロン株式会社 | 埋め込み方法及び処理システム |
US11387112B2 (en) * | 2018-10-04 | 2022-07-12 | Tokyo Electron Limited | Surface processing method and processing system |
JP7278164B2 (ja) * | 2019-07-11 | 2023-05-19 | 東京エレクトロン株式会社 | ルテニウム膜の形成方法及び基板処理システム |
US11515200B2 (en) | 2020-12-03 | 2022-11-29 | Applied Materials, Inc. | Selective tungsten deposition within trench structures |
US20230326744A1 (en) * | 2022-04-06 | 2023-10-12 | Applied Materials, Inc. | Field suppressed metal gapfill |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH065715A (ja) * | 1992-06-18 | 1994-01-14 | Sony Corp | 配線層の形成方法 |
TW374230B (en) * | 1996-03-05 | 1999-11-11 | Tokyo Electron Ltd | Method of forming multilevel-interconnection for a semiconductor device |
US6077768A (en) * | 1996-07-19 | 2000-06-20 | Motorola, Inc. | Process for fabricating a multilevel interconnect |
US5695810A (en) * | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
JP2000106397A (ja) * | 1998-07-31 | 2000-04-11 | Sony Corp | 半導体装置における配線構造及びその形成方法 |
KR100319614B1 (ko) * | 1999-04-08 | 2002-01-05 | 김영환 | 반도체 소자의 배선 형성 방법 |
US7781327B1 (en) * | 2001-03-13 | 2010-08-24 | Novellus Systems, Inc. | Resputtering process for eliminating dielectric damage |
US6528409B1 (en) * | 2002-04-29 | 2003-03-04 | Advanced Micro Devices, Inc. | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration |
US20050151263A1 (en) * | 2004-01-08 | 2005-07-14 | Fujitsu Limited | Wiring structure forming method and semiconductor device |
KR100620161B1 (ko) | 2004-08-19 | 2006-09-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
US7964504B1 (en) | 2008-02-29 | 2011-06-21 | Novellus Systems, Inc. | PVD-based metallization methods for fabrication of interconnections in semiconductor devices |
KR20090121662A (ko) | 2008-05-22 | 2009-11-26 | 주식회사 탑 엔지니어링 | 박막 금속 전도선의 형성 방법 |
US20120228125A1 (en) * | 2010-09-21 | 2012-09-13 | Liqi Wu | Creation of magnetic field (vector potential) well for improved plasma deposition and resputtering uniformity |
US9330939B2 (en) * | 2012-03-28 | 2016-05-03 | Applied Materials, Inc. | Method of enabling seamless cobalt gap-fill |
KR20170095829A (ko) | 2014-12-23 | 2017-08-23 | 인텔 코포레이션 | 분리된 비아 충전 |
US9679850B2 (en) * | 2015-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating semiconductor structure |
US9449921B1 (en) * | 2015-12-15 | 2016-09-20 | International Business Machines Corporation | Voidless contact metal structures |
US10777452B2 (en) * | 2017-09-14 | 2020-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure having top and bottom vias with a barrier layer therebetween and a dielectric spacer at the bottom via |
US10867905B2 (en) * | 2017-11-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
CN112530857A (zh) * | 2019-09-19 | 2021-03-19 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
-
2020
- 2020-02-27 US US16/803,842 patent/US11355391B2/en active Active
- 2020-03-02 CN CN202080027926.3A patent/CN113678231A/zh active Pending
- 2020-03-02 JP JP2021556653A patent/JP2022527693A/ja active Pending
- 2020-03-02 WO PCT/US2020/020696 patent/WO2020190494A1/en active Application Filing
- 2020-03-02 KR KR1020217033190A patent/KR20210129243A/ko unknown
- 2020-03-16 TW TW109108543A patent/TW202101547A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
KR20210129243A (ko) | 2021-10-27 |
TW202101547A (zh) | 2021-01-01 |
US11355391B2 (en) | 2022-06-07 |
WO2020190494A1 (en) | 2020-09-24 |
JP2022527693A (ja) | 2022-06-03 |
US20200303250A1 (en) | 2020-09-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11355391B2 (en) | Method for forming a metal gapfill | |
US9748105B2 (en) | Tungsten deposition with tungsten hexafluoride (WF6) etchback | |
US9685371B2 (en) | Method of enabling seamless cobalt gap-fill | |
US10727119B2 (en) | Process integration approach of selective tungsten via fill | |
US10395916B2 (en) | In-situ pre-clean for selectivity improvement for selective deposition | |
US8586479B2 (en) | Methods for forming a contact metal layer in semiconductor devices | |
TWI830960B (zh) | 低電阻接觸互連的方法與設備 | |
US20240038859A1 (en) | Metal cap for contact resistance reduction | |
US20240014072A1 (en) | Nitrogen plasma treatment for bottom-up growth | |
TWI843858B (zh) | 用於選擇性金屬通孔填充的製程整合方法 | |
US20220165852A1 (en) | Methods and apparatus for metal fill in metal gate stack | |
US20240006236A1 (en) | Plasma enhanced tungsten nucleation for low resistivity | |
TW202407133A (zh) | 整合的清潔及選擇性鉬沉積製程 | |
KR20220113516A (ko) | 선택적 갭 충전을 위한 저온 플라즈마 사전-세정 | |
WO2023229612A1 (en) | Selective metal removal with flowable polymer | |
CN117501429A (zh) | 用于处理基板的方法及设备 | |
CN115004336A (zh) | 沟槽结构内的选择性钨沉积 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |