TW202101547A - 用於形成金屬間隙填充物之方法 - Google Patents
用於形成金屬間隙填充物之方法 Download PDFInfo
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- TW202101547A TW202101547A TW109108543A TW109108543A TW202101547A TW 202101547 A TW202101547 A TW 202101547A TW 109108543 A TW109108543 A TW 109108543A TW 109108543 A TW109108543 A TW 109108543A TW 202101547 A TW202101547 A TW 202101547A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 131
- 239000002184 metal Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims abstract description 89
- 239000000945 filler Substances 0.000 claims description 81
- 238000004140 cleaning Methods 0.000 claims description 31
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 229910017052 cobalt Inorganic materials 0.000 claims description 7
- 239000010941 cobalt Substances 0.000 claims description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 24
- 230000007547 defect Effects 0.000 abstract description 5
- 239000012530 fluid Substances 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 19
- 239000001257 hydrogen Substances 0.000 description 12
- 229910052739 hydrogen Inorganic materials 0.000 description 12
- 229910044991 metal oxide Inorganic materials 0.000 description 11
- 150000004706 metal oxides Chemical class 0.000 description 11
- 150000002739 metals Chemical class 0.000 description 10
- 230000015654 memory Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 239000000356 contaminant Substances 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000006911 nucleation Effects 0.000 description 6
- 238000010899 nucleation Methods 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 5
- 238000002791 soaking Methods 0.000 description 5
- -1 tungsten Chemical class 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910021591 Copper(I) chloride Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- WYEMLYFITZORAB-UHFFFAOYSA-N boscalid Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1NC(=O)C1=CC=CN=C1Cl WYEMLYFITZORAB-UHFFFAOYSA-N 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- OXBLHERUFWYNTN-UHFFFAOYSA-M copper(I) chloride Chemical compound [Cu]Cl OXBLHERUFWYNTN-UHFFFAOYSA-M 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000013515 script Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本揭露案大致關於用於處理基板之方法,且更具體而言,關於用於形成金屬間隙填充物之方法。在一個實例中,方法包括使用多個步驟處理在開口中形成金屬間隙填充物。多個步驟處理包括形成第一部分的金屬間隙填充物,實行濺射處理以在一或更多側壁上形成一或更多層,及成長第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。藉由多個步驟處理形成的金屬間隙填充物為無縫的,且形成於一或更多側壁上的一或更多層密封介於金屬間隙填充物及側壁之間的任何間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物。
Description
本揭露案的實例大致關於基板的處理,且更特定而言,關於用於形成金屬間隙填充物之方法。
在半導體處理中,裝置以持續減少的特徵尺寸來製造。隨著裝置尺寸持續地縮小,及莫耳定律的二維尺寸限制無法跨越,製造商轉向三維結構以推進未來的成長。例如鰭式場效電晶體(FinFETs)的裝置及例如動態隨機存取記憶體(DRAM)裝置的三維記憶體裝置通常具有在堆疊中不同材料層的特徵。多個裝置或單元可彼此堆疊在另一個頂部,且數個裝置通常形成在一個基板上。層常常為不同的材料,所以一個結構可含有絕緣、半導體及金屬層的交替層,例如SiO2
、SiN、a-Si及聚合Si。通常,堆疊以32或64或甚至128層的此等交替層組成。
諸如鎢的某些金屬在邏輯應用中使用於接觸位準處長達約二十年。在近期先進的互補金屬氧化物半導體(CMOS)裝置中,例如金屬閘極及FinFET的新技術浮現,而導致此等金屬新的應用作為對p類型金屬氧化物半導體(PMOS)及n型金屬氧化物半導體(NMOS)裝置兩者的閘極填充物。在3D NAND裝置中,此等金屬亦用於金屬閘極填充物。用於間隙填充物之條件,使用鎢作為範例,因為數個原因變得越來越具挑戰性。舉例而言,對於接觸,隨著接觸的尺寸越來越小且因為鎢的共形填充通常會留下縫隙,懸垂變得更加具挑戰性。再者,於化學機械拋光(CMP)期間縫隙將暴露至研漿,而造成整合問題。此外,對於先進的CMOS及3D NAND兩者中的金屬閘極溝道,傳統鎢共形成長不可避免地在中間留下縫隙。
因此,需要形成金屬間隙填充物的改良的方法,用於在先進的邏輯及半導體裝置中的接觸及金屬閘極填充物兩者。
本揭露案的實例大致關於用於處理基板之方法,且更具體而言,關於用於形成金屬間隙填充物之方法。在一個實例中,一種用於形成金屬間隙填充物之方法,包括在第二層中形成的開口中,於第一層的表面上形成第一部分的金屬間隙填充物;在第一部分上實行濺射處理;及形成第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。
在另一實例中,一種用於形成金屬間隙填充物之方法,包括在第二層中形成的開口中,於第一層的表面上形成第一部分的金屬間隙填充物;在第二層的一或更多側壁上形成一或更多層;及形成第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。
在另一實例中,一種處理系統,包括傳送腔室;複數個處理腔室,耦合至傳送腔室;及控制器,配置成在處理系統中造成處理,以實行在第二層中形成的開口中,於第一層的表面上形成第一部分的金屬間隙填充物;在第一部分上實行濺射處理;及形成第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。
本揭露案大致關於用於大致關於用於處理基板之方法,且更具體而言,關於用於形成金屬間隙填充物之方法。在可包括或與此處所述的一或更多實例結合的一個實例中,方法包括使用多個步驟處理在開口中形成金屬間隙填充物。多個步驟處理包括藉由選擇性沉積處理成長第一部分的金屬間隙填充物,實行濺射處理以在一或更多側壁上形成一或更多層,及藉由選擇性沉積處理成長第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。藉由選擇性沉積處理形成的金屬間隙填充物為無縫的,且形成於一或更多側壁上的一或更多層密封介於金屬間隙填充物及側壁之間的任何間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物,而與佈置在金屬間隙填充物下方的層作用。
第1圖為用於形成金屬間隙填充物之方法100的流程圖。第2A-2F圖圖示在第1圖的方法100的不同階段期間基板200的各種視圖。應理解方法100可利用以形成未在此處呈現的任何其他半導體結構。技藝人士應理解形成半導體裝置及相關聯結構的全部處理並非圖示於圖式中或在此處說明。儘管在圖式中圖示各種操作且在此處說明,並未暗示關於此等步驟的順序或步驟存在與否的限制。依序描繪或說明的操作,除非另外說明,僅為了解釋之目的而完成,若非整體則為至少部分地並未排除同時或重疊方式的可能性。
方法100藉由在處理腔室中於基板200上實行預清潔處理,而於操作102處開始。在一個範例中,處理腔室為蝕刻腔室。如第2A圖中所顯示,基板200包括第一層202,在第一層202中形成的至少一個開口204,及佈置於開口204中的第二層206。第一層202可為介電層,而由SiO2
、SiN、SiCN、Al2
O3
、AlN或其他適合的介電材料製成。或者,在硬遮罩應用中第一層202可為碳層。開口204可為貫孔或溝道,且開口204藉由第二層206的表面210及第一層202的一或更多側壁212界定。開口204具有高度H1
。第二層206可從導電材料製成,例如金屬、半導體、導電陶瓷或其他適合的導電材料。在一個範例中,第二層206由鈷、氮化鈦或矽製成。
預清潔處理在第二層206的表面210上實行。實行預清潔處理以移除第二層206的表面210上的污染物,例如金屬氧化物、氟化物、碳、聚合物或其他蝕刻處理後殘留物。預清潔處理可為任何適合的清潔方法,例如化學清潔或電漿清潔。化學清潔利用諸如氫自由基的清潔劑,或例如H2
、CO、C2
H5
OH、WF6
、WCl5
的反應氣體,或其他適合的反應氣體。某些清潔劑,例如氫自由基、H2
或CO,將金屬氧化物污染物還原成金屬。某些清潔劑,例如WF6
或WCl5
,藉由將污染物揮發成氣體來蝕刻污染物。在一個範例中,預清潔處理利用氫自由基以還原諸如CoOx
、CuOx
及/或WO3
的金屬氧化物。氫自由基可在遠端電漿源中形成,且接著與氫氣或氬氣一起流動至基板200。基板200可維持在從約攝氏200度至約攝氏400度之範圍的溫度下。在另一範例中,預清潔處理利用H2
熱浸泡以還原諸如CoOx
、CuOx
及/或WO3
的金屬氧化物。熱浸泡處理包括將氫氣及氬氣流至處理腔室中,腔室壓力從約30 Torr至約300 Torr的範圍,且基板200維持在從約攝氏300度至約攝氏600度之範圍的溫度下。在另一範例中,預清潔處理利用乙醇浸泡以還原金屬氧化物,且基板200維持在從約攝氏200度至約攝氏400度之範圍的溫度下。在另一範例中,預清潔處理利用WF6
或WCl5
浸泡以與金屬氧化物反應,且在高溫及低壓下將金屬氧化物轉換成氣/液相金屬化合物(例如,WOF4
、CuCl2
、CoCl2
),且基板200維持在從約攝氏200度至約攝氏500度之範圍的溫度下。
預清潔處理可為電漿清潔處理。電漿清潔處理利用Ar/He電漿或H2
電漿。某些電漿清潔處理物理性將污染物濺射離開,而其他電漿清潔處理強化反應以清潔表面210。在一個範例中,預清潔處理利用氬電漿,且氬離子物理性濺射在第二層206的表面210上的污染物。氬電漿可為電容耦合、電感耦合或其結合。電漿頻率為從約350 kHz至約40 MHz的範圍,電漿功率為從約0 W至約1000 W的範圍,且腔室壓力為從約10 mTorr至約100 Torr的範圍。在另一範例中,預清潔處理利用氫電漿,且氫離子與第二層206的表面210上的污染物反應,以形成金屬及水。氫電漿清潔處理具有如氫熱浸泡類似的化學反應,但在氫電漿清潔處理中利用較少的熱能量。
在一個範例中,使用遠端電漿源在處理腔室中實行預清潔處理。適合用於實行預清潔處理的一個範例處理腔室為從美國加州聖克拉拉市的應用材料公司可取得的AKTIV Pre-CleanTM
腔室或SICONI®
清潔腔室。或者,在蝕刻腔室中實行預清潔處理,例如使用電感耦合電漿(ICP)源的蝕刻腔室。一個範例蝕刻腔室可為從美國加州聖克拉拉市的應用材料公司可取得的修改的解耦電漿氮化(DPN)腔室。然而,應考量來自其他製造商的其他適合配置的腔室亦可實施以實行預清潔處理。
在操作104處,於第二層206的清潔的表面210上實行成核處置。成核處置消除在表面210上及在開口204中形成金屬間隙填充物的孕核期,而亦消除晶格失配,因為某些金屬在不同金屬上成長孕育為非常困難的。如第2B圖中所顯示,成核處置可包括在第二層206的表面210上形成金屬種晶層214。金屬種晶層214可從鎢、鈷、釕或其他適合的金屬製成。金屬種晶層214藉由選擇性處理形成,所以金屬種晶層214並未形成於一或更多側壁212上。在一個範例中,金屬種晶層214藉由化學浸泡處理,利用諸如B2
H6
、SiH4
、Si2
H6
、WF6
、WCl5
、TiCl4
或其他適合的氣體的一或更多氣體來形成。在另一範例中,金屬種晶層214藉由選擇性金屬原子層沉積(ALD)處理而形成。在選擇性金屬ALD處理中利用的一或更多前驅物包括B2
H6
、WF6
、H2
、SiH4
、WCl5
、W(CO)6
或其他適合的前驅物。在某些實例中,利用含有除了鎢以外的金屬的一或更多氣體。舉例而言,可利用含鈷或釕的氣體以形成金屬種晶層214。在某些實例中,忽略成核處置且不存在金屬種晶層214。
下一步,於操作106處,如第2C圖中所顯示,在金屬種晶層214上形成第一部分216的金屬間隙填充物。在某些實例中,第一部分216的金屬間隙填充物形成於第二層206的表面210上。第一部分216的金屬間隙填充物以金屬製成,例如鎢、鈷、釕或其他適合的金屬。第一部分216藉由選擇性處理形成,且從底部向上成長。換句話說,第一部分216從金屬種晶層214或第二層206的表面210選擇性形成或成長,且並未形成於一或更多側壁212上。如第2C圖中所顯示,第一部分216與一或更多側壁212的部分接觸,但第一部分216並未從一或更多側壁212成長。第一部分216具有高度H2
,且高度H2
為開口204的高度H1
的約百分之10至約百分之50。
用於形成第一部分216的選擇性處理可為化學氣相沉積(CVD)處理,且選擇性是基於腔室壓力及前驅物氣體的比例。在一個範例中,選擇性處理包括將含金屬氣體及第二氣體流至處理腔室中。含金屬氣體可為任何適合的含金屬氣體,例如WF6
。第二氣體可為氫氣。第二氣體對含金屬氣體的比例從約六比一至約8000比一。腔室壓力從約1 Torr至約300 Torr的範圍,且基板維持在從約攝氏200度至約攝氏500度的溫度下。腔室壓力及氣體的比例可影響選擇性。在一個範例中,於相對高溫下,例如大於約攝氏400度,當第二氣體對含金屬氣體的比例為高的且腔室壓力為低的時,維持選擇性。
下一步,於操作108處,如第2D圖中所顯示,實行濺射處理以移除某些第一部分216的金屬間隙填充物,且在一或更多側壁212上形成一或更多層218。濺射處理可具有與利用氬電漿的預清潔處理相同的處理條件。濺射處理將某些第一部分216的金屬間隙填充物濺射至一或更多側壁212上。結果,在各個側壁212上形成層218。層218以與第一部分216的金屬間隙填充物相同的材料製成。
下一步,在操作110處,如第2E圖中所顯示,在第一部分216的金屬間隙填充物上形成第二部分220的金屬間隙填充物。第二部分220可藉由用於第一部分216的金屬間隙填充物的相同的處理形成。第二部分220以如第一部分216相同的材料製成。在開口204中形成的金屬間隙填充物包括第一部分216、一或更多層218及第二部分220。用以形成金屬間隙填充物的多個步驟為無縫的,且在金屬間隙填充物及側壁212之間不存在間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物,而與第二層206作用。
下一步,在操作112處,如第2F圖中所顯示,於基板200上實行化學機械拋光(CMP)處理,以形成平坦表面222。在CMP處理期間,研漿不會擴散通過具有第一部分216、層218及第二部分220的金屬間隙填充物,因為側壁212藉由層218密封。如此,在CMP處理中第二層206受保護而避免研漿。
參照回第1圖,實行操作106、108及110以形成無縫金屬間隙填充物,且在金屬間隙填充物及側壁之間不具有間隙或缺陷。在某些實例中,以單一操作取代操作106、108及110,而從底部向上形成單一相位結晶的金屬間隙填充物。單一相位結晶的金屬間隙填充物不具有任何晶界形成於其中,且金屬間隙填充物的阻抗獨立於開口204的尺寸。因此,單一相位結晶的金屬間隙填充物為無縫的且具有降低的電阻。單一相位結晶的金屬間隙填充物可藉由CVD處理形成,其中基板200維持於大於或等於攝氏450度的溫度。
根據此處所提供的教示可適合修改的處理系統之範例包括ENDURA®
、PRODUCER®
或CENTURA®
整合的處理系統,或從位於美國加州聖克拉拉市的應用材料公司商業上可取得的其他適合的處理系統。應考量可應用其他處理系統(包括來自其他製造商的)以從此處所述的態樣獲益。第3圖根據本揭露案的實例,圖示範例多重腔室處理系統300的概要頂部視圖,而可用以完成第1圖中圖示的方法100。如第3圖中所顯示,複數個處理腔室302耦合至第一傳送腔室304。第一傳送腔室304亦耦合至第一對直通腔室(pass-through chamber)306。第一傳送腔室304具有中心佈置的傳送機械手臂(未顯示),用於在直通腔室306及處理腔室302之間傳送基板。直通腔室306耦合至第二傳送腔室310,第二傳送腔室310耦合至配置成實行例如操作102的預清潔處理的處理腔室314,及配置成實行例如操作106的成核處置操作的處理腔室316。第二傳送腔室310具有中心佈置的傳送機械手臂(未顯示),用於在一組負載鎖定腔室312及處理腔室314或處理腔室316之間傳送基板。工廠界面320藉由負載鎖定腔室312連接至第二傳送腔室310。工廠界面320在負載鎖定腔室312的相對側上耦合至一或更多吊艙330。吊艙330通常為從無塵室可取得的前開式統一吊艙(FOUP)。
在操作中,基板首先傳送至處理腔室314,其中實行例如操作102的預清潔處理,以移除諸如來自開口的底部的金屬氧化物污染物的污染物。接著,基板傳送至處理腔室316,其中實行操作106。基板接著傳送至一或更多處理腔室302,其中實行操作106、108及110。因為所有的操作102、104、106、108及110在相同的處理系統300之中實行,所以隨著基板傳送至各種腔室不會破壞真空,而降低污染的機會且增強金屬間隙填充物的品質。
系統控制器380耦合至處理系統300,用於控制處理系統300或其部件。舉例而言,系統控制器380可使用直接控制處理系統300的腔室302、304、306、310、312、314、316,或藉由控制與腔室302、304、306、310、312、314、316相關聯的控制器,來控制處理系統300的操作。在操作中,系統控制器380能夠從分別的腔室收集資料及回饋,以協調處理系統300的效能。
系統控制器380大致包括中央處理單元(CPU)382、記憶體384及支援電路386。CPU 382可為任何形式的通用處理器之一者,而可在工業設定中使用。記憶體384、非暫時性電腦可讀取媒體或機器可讀取儲存裝置,可藉由CPU 382存取且可為一或更多記憶體,例如隨機存取記憶體(RAM)、唯讀記憶體(ROM)、軟碟、硬碟或任何其他形式的數位儲存,不論為本端或遠端。支援電路386耦合至CPU 382,且可包含快取、時鐘電路、輸入/輸出子系統、電源供應器及類似者。系統控制器380配置成實行儲存於記憶體384中的方法100。在此揭露案中揭露的各種實例可大致在CPU 382的控制下藉由執行儲存於記憶體384中(或在特定處理腔室的記憶體中)的電腦指令碼來實施,例如作為電腦程式產品或軟體常式。亦即,電腦程式產品實體安裝在記憶體384上(或非暫時性電腦可讀取媒體或機器可讀取儲存裝置)。當藉由CPU 382執行電腦指令碼時,CPU 382控制腔室以實行根據各種實例之操作。
綜上所述,本揭露案的實例能夠形成無縫金屬間隙填充物,而避免任何流體通過而擴散。無縫金屬間隙填充物藉由多個步驟處理形成,包括藉由選擇性沉積處理成長第一部分的金屬間隙填充物;實行濺射處理以在一或更多側壁上形成一或更多層;及藉由選擇性沉積處理成長第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。藉由選擇性沉積處理形成的金屬間隙填充物為無縫的,且在一或更多側壁上形成的一或更多層密封介於金屬間隙填充物及側壁之間的任何間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物。
儘管以上導向本揭露案的實例,可衍生本揭露案的其他及進一步實例,而不會悖離其基本範疇,且其範疇藉由以下申請專利範圍來決定。
100:方法
102~112:操作
200:基板
202:第一層
204:開口
206:第二層
210:表面
212:側壁
214:金屬種晶層
216:第一部分
218:層
220:第二部分
222:平坦表面
300:多重腔室處理系統
304:第一傳送腔室
306:直通腔室
310:第二傳送腔室
312:負載鎖定腔室
314:處理腔室
316:處理腔室
320:工廠界面
330:吊艙
360:控制器
380:系統控制器
382:中央處理單元
384:記憶體
386:支援電路
由此方式可詳細理解本揭露案以上所載之特徵,以上簡要概述的本揭露案的更特定說明可參考實例而獲得,某些實例圖示於隨附圖式中。然而,應理解隨附圖式僅圖示範例實例,且因此不應考量為其範疇之限制,且可認可其他均等效果的實例。
第1圖根據一個實例,為用於形成金屬間隙填充物之方法的流程圖。
第2A-2F圖根據一個實例,圖示第1圖之方法的不同狀態期間,基板的各種視圖。
第3圖根據一個實例,為適合用於實行第1圖之方法的範例多重腔室處理系統的概要頂部視圖。
為了促進理解,已盡可能地使用相同的元件符號代表共通圖式中相同的元件。應考量一個實例的元件及特徵可有益地併入其他實例中而無須進一步說明。
國內寄存資訊(請依寄存機構、日期、號碼順序註記)
無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記)
無
100:方法
102~112:操作
Claims (20)
- 一種用於形成一金屬間隙填充物之方法,該方法包含以下步驟: 在一第二層中形成的一開口中,於一第一層的一表面上形成一第一部分的該金屬間隙填充物; 在該第一部分上實行一濺射處理;及 形成一第二部分的該金屬間隙填充物,以該金屬間隙填充物來填充該開口。
- 如請求項1所述之方法,其中該第一部分的該金屬間隙填充物及該第二部分的該金屬間隙填充物以鈷、鎢或釕製成。
- 如請求項1所述之方法,其中該第一層包含一金屬。
- 如請求項1所述之方法,其中該第二層包含一介電層。
- 如請求項1所述之方法,進一步包含以下步驟:在形成該第一部分的該金屬間隙填充物之前,於該第一層的該表面上實行一預清潔處理。
- 如請求項5所述之方法,進一步包含以下步驟:在該第一層的該表面上形成一金屬種晶層,其中該第一部分的該金屬間隙填充物形成於該金屬種晶層上。
- 如請求項1所述之方法,其中該濺射處理利用氬電漿。
- 一種用於形成一金屬間隙填充物之方法,該方法包含以下步驟: 在一第二層中形成的一開口中,於一第一層的一表面上形成一第一部分的該金屬間隙填充物; 在該第二層的一或更多側壁上形成一或更多層;及 形成一第二部分的該金屬間隙填充物,以該金屬間隙填充物來填充該開口。
- 如請求項8所述之方法,其中該第一部分的該金屬間隙填充物、該一或更多層及該第二部分的該金屬間隙填充物以鈷、鎢或釕製成。
- 如請求項8所述之方法,其中該第一層包含一金屬。
- 如請求項8所述之方法,其中該第二層包含一介電層。
- 如請求項8所述之方法,進一步包含以下步驟:在形成該第一部分的該金屬間隙填充物之前,於該第一層的該表面上實行一預清潔處理。
- 如請求項12所述之方法,進一步包含以下步驟:在該第一層的該表面上形成一金屬種晶層,其中該第一部分的該金屬間隙填充物形成於該金屬種晶層上。
- 如請求項8所述之方法,其中該一或更多層藉由利用氬電漿的一濺射處理形成。
- 一種處理系統,包含: 一傳送腔室; 複數個處理腔室,耦合至該傳送腔室;及 一控制器,配置成在該處理系統中造成一處理,以實行包括以下之動作: 在一第二層中形成的一開口中,於一第一層的一表面上形成一第一部分的一金屬間隙填充物; 在該第一部分上實行一濺射處理;及 形成一第二部分的該金屬間隙填充物,以該金屬間隙填充物來填充該開口。
- 如請求項15所述之處理系統,其中該第一部分的該金屬間隙填充物及該第二部分的該金屬間隙填充物以鈷、鎢或釕製成。
- 如請求項15所述之處理系統,其中該第一層包含一金屬。
- 如請求項15所述之處理系統,其中該第二層包含一介電層。
- 如請求項15所述之處理系統,進一步包含在形成該第一部分的該金屬間隙填充物之前,於該第一層的該表面上實行一預清潔處理。
- 如請求項19所述之處理系統,進一步包含在該第一層的該表面上形成一金屬種晶層,其中該第一部分的該金屬間隙填充物形成於該金屬種晶層上。
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US201962819697P | 2019-03-18 | 2019-03-18 | |
US62/819,697 | 2019-03-18 | ||
US16/803,842 US11355391B2 (en) | 2019-03-18 | 2020-02-27 | Method for forming a metal gapfill |
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KR (1) | KR20210129243A (zh) |
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-
2020
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- 2020-03-02 JP JP2021556653A patent/JP2022527693A/ja active Pending
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