TW202101547A - 用於形成金屬間隙填充物之方法 - Google Patents

用於形成金屬間隙填充物之方法 Download PDF

Info

Publication number
TW202101547A
TW202101547A TW109108543A TW109108543A TW202101547A TW 202101547 A TW202101547 A TW 202101547A TW 109108543 A TW109108543 A TW 109108543A TW 109108543 A TW109108543 A TW 109108543A TW 202101547 A TW202101547 A TW 202101547A
Authority
TW
Taiwan
Prior art keywords
metal
gap filler
layer
metal gap
forming
Prior art date
Application number
TW109108543A
Other languages
English (en)
Inventor
岑羲
馬飛越
凱 吳
雨 雷
大東和也
徐翼
維卡許 班西亞
鎂 張
河 任
海文 洪
姚雅寬
艾夫傑尼諾斯V 傑拉多斯
傳偉 柯
周靜
蹇國強
林齊周
賴一鳴
葉佳
振宇 王
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW202101547A publication Critical patent/TW202101547A/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02Pretreatment of the material to be coated
    • C23C14/024Deposition of sublayers, e.g. to promote adhesion of the coating
    • C23C14/025Metallic sublayers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04Coating on selected surface areas, e.g. using masks
    • C23C14/046Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

本揭露案大致關於用於處理基板之方法,且更具體而言,關於用於形成金屬間隙填充物之方法。在一個實例中,方法包括使用多個步驟處理在開口中形成金屬間隙填充物。多個步驟處理包括形成第一部分的金屬間隙填充物,實行濺射處理以在一或更多側壁上形成一或更多層,及成長第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。藉由多個步驟處理形成的金屬間隙填充物為無縫的,且形成於一或更多側壁上的一或更多層密封介於金屬間隙填充物及側壁之間的任何間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物。

Description

用於形成金屬間隙填充物之方法
本揭露案的實例大致關於基板的處理,且更特定而言,關於用於形成金屬間隙填充物之方法。
在半導體處理中,裝置以持續減少的特徵尺寸來製造。隨著裝置尺寸持續地縮小,及莫耳定律的二維尺寸限制無法跨越,製造商轉向三維結構以推進未來的成長。例如鰭式場效電晶體(FinFETs)的裝置及例如動態隨機存取記憶體(DRAM)裝置的三維記憶體裝置通常具有在堆疊中不同材料層的特徵。多個裝置或單元可彼此堆疊在另一個頂部,且數個裝置通常形成在一個基板上。層常常為不同的材料,所以一個結構可含有絕緣、半導體及金屬層的交替層,例如SiO2 、SiN、a-Si及聚合Si。通常,堆疊以32或64或甚至128層的此等交替層組成。
諸如鎢的某些金屬在邏輯應用中使用於接觸位準處長達約二十年。在近期先進的互補金屬氧化物半導體(CMOS)裝置中,例如金屬閘極及FinFET的新技術浮現,而導致此等金屬新的應用作為對p類型金屬氧化物半導體(PMOS)及n型金屬氧化物半導體(NMOS)裝置兩者的閘極填充物。在3D NAND裝置中,此等金屬亦用於金屬閘極填充物。用於間隙填充物之條件,使用鎢作為範例,因為數個原因變得越來越具挑戰性。舉例而言,對於接觸,隨著接觸的尺寸越來越小且因為鎢的共形填充通常會留下縫隙,懸垂變得更加具挑戰性。再者,於化學機械拋光(CMP)期間縫隙將暴露至研漿,而造成整合問題。此外,對於先進的CMOS及3D NAND兩者中的金屬閘極溝道,傳統鎢共形成長不可避免地在中間留下縫隙。
因此,需要形成金屬間隙填充物的改良的方法,用於在先進的邏輯及半導體裝置中的接觸及金屬閘極填充物兩者。
本揭露案的實例大致關於用於處理基板之方法,且更具體而言,關於用於形成金屬間隙填充物之方法。在一個實例中,一種用於形成金屬間隙填充物之方法,包括在第二層中形成的開口中,於第一層的表面上形成第一部分的金屬間隙填充物;在第一部分上實行濺射處理;及形成第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。
在另一實例中,一種用於形成金屬間隙填充物之方法,包括在第二層中形成的開口中,於第一層的表面上形成第一部分的金屬間隙填充物;在第二層的一或更多側壁上形成一或更多層;及形成第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。
在另一實例中,一種處理系統,包括傳送腔室;複數個處理腔室,耦合至傳送腔室;及控制器,配置成在處理系統中造成處理,以實行在第二層中形成的開口中,於第一層的表面上形成第一部分的金屬間隙填充物;在第一部分上實行濺射處理;及形成第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。
本揭露案大致關於用於大致關於用於處理基板之方法,且更具體而言,關於用於形成金屬間隙填充物之方法。在可包括或與此處所述的一或更多實例結合的一個實例中,方法包括使用多個步驟處理在開口中形成金屬間隙填充物。多個步驟處理包括藉由選擇性沉積處理成長第一部分的金屬間隙填充物,實行濺射處理以在一或更多側壁上形成一或更多層,及藉由選擇性沉積處理成長第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。藉由選擇性沉積處理形成的金屬間隙填充物為無縫的,且形成於一或更多側壁上的一或更多層密封介於金屬間隙填充物及側壁之間的任何間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物,而與佈置在金屬間隙填充物下方的層作用。
第1圖為用於形成金屬間隙填充物之方法100的流程圖。第2A-2F圖圖示在第1圖的方法100的不同階段期間基板200的各種視圖。應理解方法100可利用以形成未在此處呈現的任何其他半導體結構。技藝人士應理解形成半導體裝置及相關聯結構的全部處理並非圖示於圖式中或在此處說明。儘管在圖式中圖示各種操作且在此處說明,並未暗示關於此等步驟的順序或步驟存在與否的限制。依序描繪或說明的操作,除非另外說明,僅為了解釋之目的而完成,若非整體則為至少部分地並未排除同時或重疊方式的可能性。
方法100藉由在處理腔室中於基板200上實行預清潔處理,而於操作102處開始。在一個範例中,處理腔室為蝕刻腔室。如第2A圖中所顯示,基板200包括第一層202,在第一層202中形成的至少一個開口204,及佈置於開口204中的第二層206。第一層202可為介電層,而由SiO2 、SiN、SiCN、Al2 O3 、AlN或其他適合的介電材料製成。或者,在硬遮罩應用中第一層202可為碳層。開口204可為貫孔或溝道,且開口204藉由第二層206的表面210及第一層202的一或更多側壁212界定。開口204具有高度H1 。第二層206可從導電材料製成,例如金屬、半導體、導電陶瓷或其他適合的導電材料。在一個範例中,第二層206由鈷、氮化鈦或矽製成。
預清潔處理在第二層206的表面210上實行。實行預清潔處理以移除第二層206的表面210上的污染物,例如金屬氧化物、氟化物、碳、聚合物或其他蝕刻處理後殘留物。預清潔處理可為任何適合的清潔方法,例如化學清潔或電漿清潔。化學清潔利用諸如氫自由基的清潔劑,或例如H2 、CO、C2 H5 OH、WF6 、WCl5 的反應氣體,或其他適合的反應氣體。某些清潔劑,例如氫自由基、H2 或CO,將金屬氧化物污染物還原成金屬。某些清潔劑,例如WF6 或WCl5 ,藉由將污染物揮發成氣體來蝕刻污染物。在一個範例中,預清潔處理利用氫自由基以還原諸如CoOx 、CuOx 及/或WO3 的金屬氧化物。氫自由基可在遠端電漿源中形成,且接著與氫氣或氬氣一起流動至基板200。基板200可維持在從約攝氏200度至約攝氏400度之範圍的溫度下。在另一範例中,預清潔處理利用H2 熱浸泡以還原諸如CoOx 、CuOx 及/或WO3 的金屬氧化物。熱浸泡處理包括將氫氣及氬氣流至處理腔室中,腔室壓力從約30 Torr至約300 Torr的範圍,且基板200維持在從約攝氏300度至約攝氏600度之範圍的溫度下。在另一範例中,預清潔處理利用乙醇浸泡以還原金屬氧化物,且基板200維持在從約攝氏200度至約攝氏400度之範圍的溫度下。在另一範例中,預清潔處理利用WF6 或WCl5 浸泡以與金屬氧化物反應,且在高溫及低壓下將金屬氧化物轉換成氣/液相金屬化合物(例如,WOF4 、CuCl2 、CoCl2 ),且基板200維持在從約攝氏200度至約攝氏500度之範圍的溫度下。
預清潔處理可為電漿清潔處理。電漿清潔處理利用Ar/He電漿或H2 電漿。某些電漿清潔處理物理性將污染物濺射離開,而其他電漿清潔處理強化反應以清潔表面210。在一個範例中,預清潔處理利用氬電漿,且氬離子物理性濺射在第二層206的表面210上的污染物。氬電漿可為電容耦合、電感耦合或其結合。電漿頻率為從約350 kHz至約40 MHz的範圍,電漿功率為從約0 W至約1000 W的範圍,且腔室壓力為從約10 mTorr至約100 Torr的範圍。在另一範例中,預清潔處理利用氫電漿,且氫離子與第二層206的表面210上的污染物反應,以形成金屬及水。氫電漿清潔處理具有如氫熱浸泡類似的化學反應,但在氫電漿清潔處理中利用較少的熱能量。
在一個範例中,使用遠端電漿源在處理腔室中實行預清潔處理。適合用於實行預清潔處理的一個範例處理腔室為從美國加州聖克拉拉市的應用材料公司可取得的AKTIV Pre-CleanTM 腔室或SICONI® 清潔腔室。或者,在蝕刻腔室中實行預清潔處理,例如使用電感耦合電漿(ICP)源的蝕刻腔室。一個範例蝕刻腔室可為從美國加州聖克拉拉市的應用材料公司可取得的修改的解耦電漿氮化(DPN)腔室。然而,應考量來自其他製造商的其他適合配置的腔室亦可實施以實行預清潔處理。
在操作104處,於第二層206的清潔的表面210上實行成核處置。成核處置消除在表面210上及在開口204中形成金屬間隙填充物的孕核期,而亦消除晶格失配,因為某些金屬在不同金屬上成長孕育為非常困難的。如第2B圖中所顯示,成核處置可包括在第二層206的表面210上形成金屬種晶層214。金屬種晶層214可從鎢、鈷、釕或其他適合的金屬製成。金屬種晶層214藉由選擇性處理形成,所以金屬種晶層214並未形成於一或更多側壁212上。在一個範例中,金屬種晶層214藉由化學浸泡處理,利用諸如B2 H6 、SiH4 、Si2 H6 、WF6 、WCl5 、TiCl4 或其他適合的氣體的一或更多氣體來形成。在另一範例中,金屬種晶層214藉由選擇性金屬原子層沉積(ALD)處理而形成。在選擇性金屬ALD處理中利用的一或更多前驅物包括B2 H6 、WF6 、H2 、SiH4 、WCl5 、W(CO)6 或其他適合的前驅物。在某些實例中,利用含有除了鎢以外的金屬的一或更多氣體。舉例而言,可利用含鈷或釕的氣體以形成金屬種晶層214。在某些實例中,忽略成核處置且不存在金屬種晶層214。
下一步,於操作106處,如第2C圖中所顯示,在金屬種晶層214上形成第一部分216的金屬間隙填充物。在某些實例中,第一部分216的金屬間隙填充物形成於第二層206的表面210上。第一部分216的金屬間隙填充物以金屬製成,例如鎢、鈷、釕或其他適合的金屬。第一部分216藉由選擇性處理形成,且從底部向上成長。換句話說,第一部分216從金屬種晶層214或第二層206的表面210選擇性形成或成長,且並未形成於一或更多側壁212上。如第2C圖中所顯示,第一部分216與一或更多側壁212的部分接觸,但第一部分216並未從一或更多側壁212成長。第一部分216具有高度H2 ,且高度H2 為開口204的高度H1 的約百分之10至約百分之50。
用於形成第一部分216的選擇性處理可為化學氣相沉積(CVD)處理,且選擇性是基於腔室壓力及前驅物氣體的比例。在一個範例中,選擇性處理包括將含金屬氣體及第二氣體流至處理腔室中。含金屬氣體可為任何適合的含金屬氣體,例如WF6 。第二氣體可為氫氣。第二氣體對含金屬氣體的比例從約六比一至約8000比一。腔室壓力從約1 Torr至約300 Torr的範圍,且基板維持在從約攝氏200度至約攝氏500度的溫度下。腔室壓力及氣體的比例可影響選擇性。在一個範例中,於相對高溫下,例如大於約攝氏400度,當第二氣體對含金屬氣體的比例為高的且腔室壓力為低的時,維持選擇性。
下一步,於操作108處,如第2D圖中所顯示,實行濺射處理以移除某些第一部分216的金屬間隙填充物,且在一或更多側壁212上形成一或更多層218。濺射處理可具有與利用氬電漿的預清潔處理相同的處理條件。濺射處理將某些第一部分216的金屬間隙填充物濺射至一或更多側壁212上。結果,在各個側壁212上形成層218。層218以與第一部分216的金屬間隙填充物相同的材料製成。
下一步,在操作110處,如第2E圖中所顯示,在第一部分216的金屬間隙填充物上形成第二部分220的金屬間隙填充物。第二部分220可藉由用於第一部分216的金屬間隙填充物的相同的處理形成。第二部分220以如第一部分216相同的材料製成。在開口204中形成的金屬間隙填充物包括第一部分216、一或更多層218及第二部分220。用以形成金屬間隙填充物的多個步驟為無縫的,且在金屬間隙填充物及側壁212之間不存在間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物,而與第二層206作用。
下一步,在操作112處,如第2F圖中所顯示,於基板200上實行化學機械拋光(CMP)處理,以形成平坦表面222。在CMP處理期間,研漿不會擴散通過具有第一部分216、層218及第二部分220的金屬間隙填充物,因為側壁212藉由層218密封。如此,在CMP處理中第二層206受保護而避免研漿。
參照回第1圖,實行操作106、108及110以形成無縫金屬間隙填充物,且在金屬間隙填充物及側壁之間不具有間隙或缺陷。在某些實例中,以單一操作取代操作106、108及110,而從底部向上形成單一相位結晶的金屬間隙填充物。單一相位結晶的金屬間隙填充物不具有任何晶界形成於其中,且金屬間隙填充物的阻抗獨立於開口204的尺寸。因此,單一相位結晶的金屬間隙填充物為無縫的且具有降低的電阻。單一相位結晶的金屬間隙填充物可藉由CVD處理形成,其中基板200維持於大於或等於攝氏450度的溫度。
根據此處所提供的教示可適合修改的處理系統之範例包括ENDURA® 、PRODUCER® 或CENTURA® 整合的處理系統,或從位於美國加州聖克拉拉市的應用材料公司商業上可取得的其他適合的處理系統。應考量可應用其他處理系統(包括來自其他製造商的)以從此處所述的態樣獲益。第3圖根據本揭露案的實例,圖示範例多重腔室處理系統300的概要頂部視圖,而可用以完成第1圖中圖示的方法100。如第3圖中所顯示,複數個處理腔室302耦合至第一傳送腔室304。第一傳送腔室304亦耦合至第一對直通腔室(pass-through chamber)306。第一傳送腔室304具有中心佈置的傳送機械手臂(未顯示),用於在直通腔室306及處理腔室302之間傳送基板。直通腔室306耦合至第二傳送腔室310,第二傳送腔室310耦合至配置成實行例如操作102的預清潔處理的處理腔室314,及配置成實行例如操作106的成核處置操作的處理腔室316。第二傳送腔室310具有中心佈置的傳送機械手臂(未顯示),用於在一組負載鎖定腔室312及處理腔室314或處理腔室316之間傳送基板。工廠界面320藉由負載鎖定腔室312連接至第二傳送腔室310。工廠界面320在負載鎖定腔室312的相對側上耦合至一或更多吊艙330。吊艙330通常為從無塵室可取得的前開式統一吊艙(FOUP)。
在操作中,基板首先傳送至處理腔室314,其中實行例如操作102的預清潔處理,以移除諸如來自開口的底部的金屬氧化物污染物的污染物。接著,基板傳送至處理腔室316,其中實行操作106。基板接著傳送至一或更多處理腔室302,其中實行操作106、108及110。因為所有的操作102、104、106、108及110在相同的處理系統300之中實行,所以隨著基板傳送至各種腔室不會破壞真空,而降低污染的機會且增強金屬間隙填充物的品質。
系統控制器380耦合至處理系統300,用於控制處理系統300或其部件。舉例而言,系統控制器380可使用直接控制處理系統300的腔室302、304、306、310、312、314、316,或藉由控制與腔室302、304、306、310、312、314、316相關聯的控制器,來控制處理系統300的操作。在操作中,系統控制器380能夠從分別的腔室收集資料及回饋,以協調處理系統300的效能。
系統控制器380大致包括中央處理單元(CPU)382、記憶體384及支援電路386。CPU 382可為任何形式的通用處理器之一者,而可在工業設定中使用。記憶體384、非暫時性電腦可讀取媒體或機器可讀取儲存裝置,可藉由CPU 382存取且可為一或更多記憶體,例如隨機存取記憶體(RAM)、唯讀記憶體(ROM)、軟碟、硬碟或任何其他形式的數位儲存,不論為本端或遠端。支援電路386耦合至CPU 382,且可包含快取、時鐘電路、輸入/輸出子系統、電源供應器及類似者。系統控制器380配置成實行儲存於記憶體384中的方法100。在此揭露案中揭露的各種實例可大致在CPU 382的控制下藉由執行儲存於記憶體384中(或在特定處理腔室的記憶體中)的電腦指令碼來實施,例如作為電腦程式產品或軟體常式。亦即,電腦程式產品實體安裝在記憶體384上(或非暫時性電腦可讀取媒體或機器可讀取儲存裝置)。當藉由CPU 382執行電腦指令碼時,CPU 382控制腔室以實行根據各種實例之操作。
綜上所述,本揭露案的實例能夠形成無縫金屬間隙填充物,而避免任何流體通過而擴散。無縫金屬間隙填充物藉由多個步驟處理形成,包括藉由選擇性沉積處理成長第一部分的金屬間隙填充物;實行濺射處理以在一或更多側壁上形成一或更多層;及藉由選擇性沉積處理成長第二部分的金屬間隙填充物,以金屬間隙填充物來填充開口。藉由選擇性沉積處理形成的金屬間隙填充物為無縫的,且在一或更多側壁上形成的一或更多層密封介於金屬間隙填充物及側壁之間的任何間隙或缺陷。結果,在後續處理中利用的流體不會擴散通過金屬間隙填充物。
儘管以上導向本揭露案的實例,可衍生本揭露案的其他及進一步實例,而不會悖離其基本範疇,且其範疇藉由以下申請專利範圍來決定。
100:方法 102~112:操作 200:基板 202:第一層 204:開口 206:第二層 210:表面 212:側壁 214:金屬種晶層 216:第一部分 218:層 220:第二部分 222:平坦表面 300:多重腔室處理系統 304:第一傳送腔室 306:直通腔室 310:第二傳送腔室 312:負載鎖定腔室 314:處理腔室 316:處理腔室 320:工廠界面 330:吊艙 360:控制器 380:系統控制器 382:中央處理單元 384:記憶體 386:支援電路
由此方式可詳細理解本揭露案以上所載之特徵,以上簡要概述的本揭露案的更特定說明可參考實例而獲得,某些實例圖示於隨附圖式中。然而,應理解隨附圖式僅圖示範例實例,且因此不應考量為其範疇之限制,且可認可其他均等效果的實例。
第1圖根據一個實例,為用於形成金屬間隙填充物之方法的流程圖。
第2A-2F圖根據一個實例,圖示第1圖之方法的不同狀態期間,基板的各種視圖。
第3圖根據一個實例,為適合用於實行第1圖之方法的範例多重腔室處理系統的概要頂部視圖。
為了促進理解,已盡可能地使用相同的元件符號代表共通圖式中相同的元件。應考量一個實例的元件及特徵可有益地併入其他實例中而無須進一步說明。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:方法
102~112:操作

Claims (20)

  1. 一種用於形成一金屬間隙填充物之方法,該方法包含以下步驟: 在一第二層中形成的一開口中,於一第一層的一表面上形成一第一部分的該金屬間隙填充物; 在該第一部分上實行一濺射處理;及 形成一第二部分的該金屬間隙填充物,以該金屬間隙填充物來填充該開口。
  2. 如請求項1所述之方法,其中該第一部分的該金屬間隙填充物及該第二部分的該金屬間隙填充物以鈷、鎢或釕製成。
  3. 如請求項1所述之方法,其中該第一層包含一金屬。
  4. 如請求項1所述之方法,其中該第二層包含一介電層。
  5. 如請求項1所述之方法,進一步包含以下步驟:在形成該第一部分的該金屬間隙填充物之前,於該第一層的該表面上實行一預清潔處理。
  6. 如請求項5所述之方法,進一步包含以下步驟:在該第一層的該表面上形成一金屬種晶層,其中該第一部分的該金屬間隙填充物形成於該金屬種晶層上。
  7. 如請求項1所述之方法,其中該濺射處理利用氬電漿。
  8. 一種用於形成一金屬間隙填充物之方法,該方法包含以下步驟: 在一第二層中形成的一開口中,於一第一層的一表面上形成一第一部分的該金屬間隙填充物; 在該第二層的一或更多側壁上形成一或更多層;及 形成一第二部分的該金屬間隙填充物,以該金屬間隙填充物來填充該開口。
  9. 如請求項8所述之方法,其中該第一部分的該金屬間隙填充物、該一或更多層及該第二部分的該金屬間隙填充物以鈷、鎢或釕製成。
  10. 如請求項8所述之方法,其中該第一層包含一金屬。
  11. 如請求項8所述之方法,其中該第二層包含一介電層。
  12. 如請求項8所述之方法,進一步包含以下步驟:在形成該第一部分的該金屬間隙填充物之前,於該第一層的該表面上實行一預清潔處理。
  13. 如請求項12所述之方法,進一步包含以下步驟:在該第一層的該表面上形成一金屬種晶層,其中該第一部分的該金屬間隙填充物形成於該金屬種晶層上。
  14. 如請求項8所述之方法,其中該一或更多層藉由利用氬電漿的一濺射處理形成。
  15. 一種處理系統,包含: 一傳送腔室; 複數個處理腔室,耦合至該傳送腔室;及 一控制器,配置成在該處理系統中造成一處理,以實行包括以下之動作: 在一第二層中形成的一開口中,於一第一層的一表面上形成一第一部分的一金屬間隙填充物; 在該第一部分上實行一濺射處理;及 形成一第二部分的該金屬間隙填充物,以該金屬間隙填充物來填充該開口。
  16. 如請求項15所述之處理系統,其中該第一部分的該金屬間隙填充物及該第二部分的該金屬間隙填充物以鈷、鎢或釕製成。
  17. 如請求項15所述之處理系統,其中該第一層包含一金屬。
  18. 如請求項15所述之處理系統,其中該第二層包含一介電層。
  19. 如請求項15所述之處理系統,進一步包含在形成該第一部分的該金屬間隙填充物之前,於該第一層的該表面上實行一預清潔處理。
  20. 如請求項19所述之處理系統,進一步包含在該第一層的該表面上形成一金屬種晶層,其中該第一部分的該金屬間隙填充物形成於該金屬種晶層上。
TW109108543A 2019-03-18 2020-03-16 用於形成金屬間隙填充物之方法 TW202101547A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962819697P 2019-03-18 2019-03-18
US62/819,697 2019-03-18
US16/803,842 US11355391B2 (en) 2019-03-18 2020-02-27 Method for forming a metal gapfill
US16/803,842 2020-02-27

Publications (1)

Publication Number Publication Date
TW202101547A true TW202101547A (zh) 2021-01-01

Family

ID=72513728

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109108543A TW202101547A (zh) 2019-03-18 2020-03-16 用於形成金屬間隙填充物之方法

Country Status (6)

Country Link
US (1) US11355391B2 (zh)
JP (1) JP2022527693A (zh)
KR (1) KR20210129243A (zh)
CN (1) CN113678231A (zh)
TW (1) TW202101547A (zh)
WO (1) WO2020190494A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404313B2 (en) * 2017-04-26 2022-08-02 Applied Materials, Inc. Selective tungsten deposition at low temperatures
JP7182970B2 (ja) * 2018-09-20 2022-12-05 東京エレクトロン株式会社 埋め込み方法及び処理システム
US11387112B2 (en) * 2018-10-04 2022-07-12 Tokyo Electron Limited Surface processing method and processing system
JP7278164B2 (ja) * 2019-07-11 2023-05-19 東京エレクトロン株式会社 ルテニウム膜の形成方法及び基板処理システム
US11515200B2 (en) 2020-12-03 2022-11-29 Applied Materials, Inc. Selective tungsten deposition within trench structures
US20230326744A1 (en) * 2022-04-06 2023-10-12 Applied Materials, Inc. Field suppressed metal gapfill

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065715A (ja) * 1992-06-18 1994-01-14 Sony Corp 配線層の形成方法
US6066558A (en) * 1996-03-05 2000-05-23 Tokyo Electron Limited Multilevel interconnection forming method for forming a semiconductor device
US6077768A (en) * 1996-07-19 2000-06-20 Motorola, Inc. Process for fabricating a multilevel interconnect
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
JP2000106397A (ja) * 1998-07-31 2000-04-11 Sony Corp 半導体装置における配線構造及びその形成方法
KR100319614B1 (ko) * 1999-04-08 2002-01-05 김영환 반도체 소자의 배선 형성 방법
US7781327B1 (en) * 2001-03-13 2010-08-24 Novellus Systems, Inc. Resputtering process for eliminating dielectric damage
US6528409B1 (en) * 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US20050151263A1 (en) * 2004-01-08 2005-07-14 Fujitsu Limited Wiring structure forming method and semiconductor device
KR100620161B1 (ko) 2004-08-19 2006-09-04 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US7964504B1 (en) 2008-02-29 2011-06-21 Novellus Systems, Inc. PVD-based metallization methods for fabrication of interconnections in semiconductor devices
KR20090121662A (ko) 2008-05-22 2009-11-26 주식회사 탑 엔지니어링 박막 금속 전도선의 형성 방법
US20120228125A1 (en) * 2010-09-21 2012-09-13 Liqi Wu Creation of magnetic field (vector potential) well for improved plasma deposition and resputtering uniformity
US9330939B2 (en) * 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US10026649B2 (en) 2014-12-23 2018-07-17 Intel Corporation Decoupled via fill
US9679850B2 (en) * 2015-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of fabricating semiconductor structure
US9449921B1 (en) * 2015-12-15 2016-09-20 International Business Machines Corporation Voidless contact metal structures
US10777452B2 (en) * 2017-09-14 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure having top and bottom vias with a barrier layer therebetween and a dielectric spacer at the bottom via
US10867905B2 (en) * 2017-11-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming the same
CN112530857A (zh) * 2019-09-19 2021-03-19 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
CN113678231A (zh) 2021-11-19
KR20210129243A (ko) 2021-10-27
US11355391B2 (en) 2022-06-07
JP2022527693A (ja) 2022-06-03
US20200303250A1 (en) 2020-09-24
WO2020190494A1 (en) 2020-09-24

Similar Documents

Publication Publication Date Title
TW202101547A (zh) 用於形成金屬間隙填充物之方法
TWI629373B (zh) 以六氟化鎢(wf6)回蝕進行鎢沉積
US10096516B1 (en) Method of forming a barrier layer for through via applications
EP2831907B1 (en) Method of enabling seamless cobalt gap-fill
US8222133B2 (en) Manufacturing method of semiconductor device
US10727119B2 (en) Process integration approach of selective tungsten via fill
US20150093891A1 (en) Method of enabling seamless cobalt gap-fill
US11967525B2 (en) Selective tungsten deposition at low temperatures
TWI830960B (zh) 低電阻接觸互連的方法與設備
JP2022535444A (ja) 充填による選択的金属用のプロセス統合アプローチ
KR102118580B1 (ko) 루테늄 필름들의 화학 기상 증착 (cvd) 및 그 용도들
US20240175120A1 (en) Low resistivity gapfill
US20230326744A1 (en) Field suppressed metal gapfill
TW202225445A (zh) 用於金屬閘極堆疊中之金屬填充之方法及設備
WO2022006225A1 (en) Selective tungsten deposition at low temperatures
TW202346466A (zh) 使用流動性聚合物的選擇性金屬移除
TW202407133A (zh) 整合的清潔及選擇性鉬沉積製程
WO2024064285A1 (en) Middle of line dielectric layer engineering for via void prevention
TW202230805A (zh) 用於降低接觸電阻之金屬蓋
JP2023516866A (ja) トレンチ構造内の選択的タングステン堆積