CN113496963A - 半导体装置及其制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 109
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims description 74
- 230000001681 protective effect Effects 0.000 description 7
- 229910018503 SF6 Inorganic materials 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 3
- 241000237503 Pectinidae Species 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 235000020637 scallop Nutrition 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000012733 comparative method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
实施方式提供可靠性较高的半导体装置及其制造方法。实施方式的半导体装置具备:基板;设于基板之上的电极层;半导体芯片,设于电极层之上,具有相对于基板的基板面形成第一角度的第一侧面部和设于第一侧面部之下且相对于基板面形成比第一角度小的第二角度的第二侧面部;以及树脂,设于电极层以及半导体芯片的周围,与第一侧面部以及第二侧面部相接。
Description
相关申请
本申请享受以日本专利申请2020-50007号(申请日:2020年3月19日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的所有内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
具有MOSFET(Metal Oxide Semiconductor Field Effect Transistor,金属氧化物半导体场效应管)等半导体芯片的半导体装置被使用于电力转换等用途。这种半导体芯片通过树脂密封来使用。优选的是,树脂的密封状态良好。
发明内容
本发明的实施方式提供可靠性较高的半导体装置及其制造方法。
实施方式的半导体装置具备:基板;设于基板之上的电极层;半导体芯片,设于电极层之上,具有相对于基板的基板面形成第一角度的第一侧面部和设于第一侧面部之下且相对于基板面形成比第一角度小的第二角度的第二侧面部;以及树脂,设于电极层以及半导体芯片的周围,与第一侧面部以及第二侧面部相接。
附图说明
图1是实施方式的半导体装置的示意剖面图。
图2是实施方式的半导体装置的主要部分的示意剖面图。
图3的(a)~(c)是表示实施方式的半导体装置的制造工序的示意剖面图。
图4的(a)~(c)是表示实施方式的半导体装置的主要部分的制造工序的示意剖面图。
图5的(a)~(c)是表示实施方式的半导体装置的主要部分的制造工序的示意剖面图。
图6的(a)~(c)是表示成为比较方式的半导体装置的制造工序的示意剖面图。
具体实施方式
以下,参照附图对本发明的实施方式进行说明。另外,在以下的说明中,对相同的部件等标注相同的附图标记,对于说明过一次的部件等适当省略其说明。
在本说明书中,为了表示部件等的位置关系,将附图的上方向记述为“上”,将附图的下方向记述为“下”。在本说明书中,“上”、“下”的概念并不一定是表示与重力的朝向的关系的词语。
(实施方式)
实施方式的半导体装置具备:基板;设于基板之上的电极层;半导体芯片,设于电极层之上,具有相对于基板的基板面形成第一角度的第一侧面部和设于第一侧面部之下且相对于基板面形成比第一角度小的第二角度的第二侧面部;以及树脂,设于电极层以及半导体芯片的周围,与第一侧面部以及第二侧面部相接。
图1是实施方式的半导体装置100的示意剖面图。实施方式的半导体装置100例如是MOSFET。
半导体装置100具备基板2、电极层6、半导体芯片10、以及树脂20。
基板2具有基板面4。基板2例如包含金属材料、半导体材料。这里,金属材料例如是Cu(铜)、Al(铝)、Ni(镍)、Ag(银)或者Au(金)等。另外,半导体材料例如是Si(硅)、SiC(碳化硅)、GaAs(砷化镓)、或者GaN(氮化镓)等。但是,基板2例如也可以是包含树脂材料的树脂基板。
电极层6设于基板2的基板面4之上。电极层6例如与基板面4接合。电极层6例如作为MOSFET的漏极电极发挥功能。电极层6包含金属材料。这里,金属材料例如是Cu(铜)、Al(铝)、Ni(镍)、Ag(银)或者Au(金)等,但并不限定于此。另外,电极层6也可以成为半导体芯片10的一部分。
半导体芯片10设于电极层6之上。例如电极层6是半导体芯片10的背面电极。例如半导体芯片10的底面与电极层6电连接。半导体芯片10在侧面具有第一侧面部12和第二侧面部16。第一侧面部12相对于基板面4形成第一角度θ1。第一角度θ1例如是90度。在图1中,将第一角度θ1图示为90度,但第一角度θ1并不限定于90度。第二侧面部16设于第一侧面部12之下。第二侧面部16相对于基板面4形成比第一角度θ1小的第二角度θ2。另外,在图1中,将第一角度θ1以及第二角度θ2都设为从基板面4逆时针旋转而得的角度。在后述的图2中也相同。
树脂20设于电极层6以及半导体芯片10的周围。树脂20与基板面4、电极层6、半导体芯片10的上表面、第一侧面部12以及第二侧面部16相接,将电极层6以及半导体芯片10密封。树脂20例如是环氧树脂等密封树脂。另外,树脂20也可以还含有二氧化硅(SiO2)等填料。但是,树脂20的种类并不限定于此。
图2是实施方式的半导体装置100的主要部分的示意剖面图。另外,在图2中,省略了树脂20的图示。
第一侧面部12具有以第一间距d1形成的多个第一扇形边(scallop)14。在图2中图示了作为多个第一扇形边14的第一扇形边14a、14b、14c、14d、14e、14f、14g、14h、14i以及14j。第二侧面部16具有以第二间距d2形成的多个第二扇形边18。在图2中图示了作为多个第二扇形边18的第二扇形边18a、18b、18c以及18d。第一间距d1以及第二间距d2优选的是10μm以下。而且,树脂20与多个第一扇形边14以及多个第二扇形边18相接。优选的是第二间距d2大于第一间距d1,即d2>d1。
多个第一扇形边14以及多个第二扇形边18例如在通过等离子体蚀刻将包含Si的基板2切断时形成。这里,这种等离子体蚀刻如后述那样,例如通过重复使用了F(氟)类自由基的各向同性蚀刻、包含CF4(四氟化碳)类自由基的保护膜的形成以及使用了F类离子的各向异性蚀刻来进行。通过这种等离子体蚀刻,形成了具有贝壳状的形状的扇形边。具体而言,多个第一扇形边14形成于第一侧面部12,多个第二扇形边18形成于第二侧面部16。
另外,第一角度θ1为设于各个第一扇形边14之间的多个顶点15连结而成的线段与基板面4所成的角。在图2中,作为顶点15,示出了顶点15a、15b、15c、15d、15e、15f、15g、15h以及15i。另外,第二角度θ2为设于各个第二扇形边18之间的多个顶点19连结而成的线段与基板面4所成的角。在图2中,作为顶点19,示出了顶点19a、19b以及19c。
图3是表示实施方式的半导体装置100的制造工序的示意剖面图。
实施方式的半导体装置的制造方法使用设于在下方具有电极层6的半导体基板70之上且具有第一宽度L1的第一开口部62的掩模,进行设于第一开口部62之下的所述半导体基板的第一部分72的第一蚀刻,从而形成具有第一侧面部12的第一间隙74,并进行第一间隙74下方的半导体基板70的第二部分76的第二蚀刻,从而形成具有第二侧面部16的倒锥形状的第二间隙78,通过形成第二间隙78,将半导体基板70断开而形成半导体芯片10,将电极层6以及半导体芯片10配置于基板2之上,并在基板2之上的半导体芯片10的周围形成树脂20。
半导体基板70是形成半导体芯片10的基板。在半导体基板的上表面70a之上设有例如作为光掩模的掩模60。掩模60具有第一宽度L1的第一开口部62。在半导体基板的下表面70b之下设有电极层6。电极层6具有比第一宽度L1长的第二宽度L2的第二开口部8。第二开口部8设于第一开口部62之下。第一开口部62以及第二开口部8分别为切割用的刻痕线。半导体芯片10所具有的MOSFET例如形成于半导体基板的上表面70a。电极层6固定于公知的切割带90之上(图3的(a))。
这里,进行设于第一开口部62之下的半导体基板70的第一部分72的蚀刻(第一蚀刻的一个例子)。由此,在第一开口部62之下形成第一间隙74(图3的(b))。第一间隙74例如与半导体基板的上表面70a或者下表面70b平行地形成为条状。半导体基板70的第一间隙74的侧面成为作为第一侧面部12的第一侧面部12a以及第二侧面部12b。
接下来,进行设于第一间隙74之下的半导体基板70的第二部分76的蚀刻(第二蚀刻的一个例子)。由此,形成具有倒锥形状的第二间隙78。第二间隙78将第二开口部8与第一间隙74连接。另外,第二间隙78例如与半导体基板的上表面70a或者下表面70b平行地形成为条状。由此,半导体基板70被断开,形成半导体芯片10a以及半导体芯片10b。第二间隙78的侧面成为作为第二侧面部16的第二侧面部16a以及第二侧面部16b(图3的(c))。
接下来,将切割带90从电极层6剥离。接下来,将电极层6以及半导体芯片10配置于图3中未图示的基板2之上。接下来,在基板2之上的电极层6以及半导体芯片的周围形成图3中未图示的树脂20。由此,获得实施方式的半导体装置100。
图4是表示实施方式的半导体装置100的主要部分的制造工序的示意剖面图。图4是表示第一间隙74的制造工序的示意剖面图。
在半导体基板70之上设有具有第一宽度L1的第一开口部62的掩模60。在第一开口部62之下形成有间隙80a。在间隙80a的侧面形成有第一扇形边14a。这里,在间隙80a的侧面以及底面,使用CF4(四氟化碳)类自由基形成保护膜82a(图4的(a))。
接下来,例如使用由SF6(六氟化硫)构成的F类离子,通过各向异性蚀刻将形成于间隙80a的底面的保护膜82a的一部分去除(图4的(b))。另外,使用图4的(b)说明的各向异性蚀刻是第三蚀刻的一个例子。
接下来,在间隙80a的底面之下,例如通过使用了由SF6构成的F(氟)类自由基的各向同性蚀刻,形成间隙80b。在间隙80b的侧面形成第一扇形边14b。接下来,在间隙80b的侧面以及底面使用CF4(四氟化碳)类自由基形成保护膜82b(图4的(c)),另外,使用图4的(c)说明的各向同性蚀刻是第四蚀刻的一个例子。
通过重复进行以上的工序,形成第一间隙74。即,第一蚀刻是第三蚀刻和第四蚀刻的重复。
图5是表示实施方式的半导体装置100的主要部分的制造工序的示意剖面图。图5是表示第二间隙78的制造工序的示意剖面图。
在间隙84a的侧面形成有第二扇形边18a。这里,在间隙84a的侧面以及底面,使用CF4(四氟化碳)类自由基形成保护膜86a(图5的(a))。
接下来,例如使用由SF6(六氟化硫)构成的F类离子,通过各向异性蚀刻,将形成于间隙84a的底面的保护膜86a的一部分去除(图5的(b))。另外,使用图5的(b)说明的各向异性蚀刻是第五蚀刻的一个例子。
接下来,在间隙84a的底面之下,通过例如使用了由SF6构成的F(氟)类自由基的各向同性蚀刻,形成间隙84b。在间隙84b的侧面形成第二扇形边18b。这里,例如相比于形成间隙80b时的各向同性蚀刻的时间,延长形成间隙84b时的各向同性蚀刻的时间。由此,如使用图2说明那样,第二间距d2变得比第一间距d1大(图2)。另外,第二间隙78的形状成为倒锥形状。接下来,在间隙84b的侧面以及底面使用CF4(四氟化碳)类自由基形成保护膜86b(图5的(c))。另外,使用图5的(c)说明的各向同性蚀刻是第六蚀刻的一个例子。
通过重复进行以上的工序,形成第二间隙78。即,第二蚀刻是第五蚀刻和第六蚀刻的重复。而且,第六蚀刻的时间每当重复时就变长。由此,形成上述的倒锥形状。另外,第六蚀刻的时间例如也可以以每当重复时就追加规定时间的形式变长。另外,第六蚀刻的时间也可以以其他方式在每次重复时变长,不被特别限定。
接下来,记载实施方式的作用效果。
图6是表示成为比较方式的半导体装置800的制造工序的示意剖面图。
在下方具有电极层6的半导体基板70的切割中,考虑在将电极层6的一部分去除而形成第二开口部8之后,将具有第一开口部62的掩模60形成于半导体基板70之上。这里,第一开口部62以及第二开口部8被用作刻痕线,因此第一开口部62形成为配置于第二开口部8之上。
在形成掩模60然后进行切割的情况下,优选的是使第二开口部8的第二宽度L2比第一开口部62的第一宽度L1长。这是因为,难以从半导体基板70的上方观察第二开口部8的位置,因此通过预先加长第二宽度L2,可靠地在第二开口部8之上形成第一开口部62。换言之,是因为考虑电极层6相对于第二开口部8的对准余量(位置偏移余量)的缘故(图6的(a))。
但是,如图6的(b)所示,在形成与半导体基板70的基板面垂直的间隙92而进行了切割的情况下,在半导体芯片10a以及半导体芯片10b的下表面(底面)形成未形成有电极层6的部分。因此,在利用树脂20密封的情况下,树脂20不能进入未形成有电极层6的部分的周围,将会形成空隙V。因此,有树脂20中出现裂纹等、半导体装置100的可靠性降低的问题。
因此,实施方式的半导体装置100具备半导体芯片10,该半导体芯片10设于电极层6之上,具有:第一侧面部12,相对于基板2的基板面4形成第一角度θ1;以及第二侧面部16,设于第一侧面部12之下,相对于基板面4形成比第一角度θ1小的第二角度θ2。由于具有这种第二侧面部16,树脂20良好地进入第二侧面部16,因此可抑制空隙V的形成。因此,能够提供可靠性高的半导体装置。
另外,在进行实施方式那样的等离子体蚀刻的情况下,在第一侧面部12形成多个第一扇形边14,而且在第二侧面部16形成多个第二扇形边18。多个第一扇形边14的第一间距d1以及多个第二扇形边18的第二间距d2设为10μm以下这样小,因此在树脂20进入第一扇形边14以及第二扇形边18的情况下,树脂与第一侧面部12或者第二侧面部16的接触性提高,可获得更高的可靠性。另一方面,即使树脂20未进入,形成的空隙的大小也极小,因此不会对可靠性带来影响。另外,在多个第一扇形边14的第一间距P1以及多个第二扇形边18的第二间距P2比10μm大的情况下,存在形成空隙而可靠性降低的可能性。
在实施方式的制造方法中,使用设于在下方具有电极层6的半导体基板70之上且具有第一宽度L1的第一开口部62的掩模,进行设于第一开口部62之下的所述半导体基板的第一部分72的第一蚀刻,从而形成具有第一侧面部12的第一间隙74,通过进行第一间隙74下方的半导体基板70的第二部分76的第二蚀刻,从而形成具有第二侧面部16的倒锥形状的第二间隙78,通过形成第二间隙78,将半导体基板70断开而形成半导体芯片10,将电极层6以及半导体芯片10配置于基板2之上,在基板2之上的半导体芯片10的周围形成树脂20。然后,通过进行第一蚀刻,在与第一侧面部12平行的方向上将以第一间距形成的多个第一扇形边14形成于第一侧面部12,通过进行第二蚀刻,在与第二侧面部16平行的方向上将以第二间距形成的多个第二扇形边18形成于第二侧面部16。由此,可抑制半导体芯片10的侧面以及未形成有电极层6的半导体芯片10的下表面(底面)形成空隙V,并形成可靠性较高的半导体装置。
另外,第一蚀刻是作为各向异性蚀刻的第三蚀刻和在所述第三蚀刻之后进行的作为各向同性蚀刻的第四蚀刻的重复。而且,第二蚀刻是作为各向异性蚀刻的第五蚀刻和在所述第五蚀刻之后进行的作为各向同性蚀刻的第六蚀刻的重复。而且,第六蚀刻的时间比所述第四蚀刻的时间长。而且,第六蚀刻的时间每当重复时就变长。由此,形成具有倒锥形状的第二间隙,可抑制空隙V的形成。另外,若使第六蚀刻的时间比第四蚀刻的时间长,则第二间距d2比第一间距d1大(d2>d1)。
虽然说明了本发明的几个实施方式以及实施例,但这些实施方式以及实施例是作为例子而提出的,并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施,在不脱离发明的主旨的范围内,能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围及主旨中,并且包含在权利要求书所记载的发明及其等效的范围内。
Claims (9)
1.一种半导体装置,具备:
基板;
电极层,设于所述基板之上;
半导体芯片,设于所述电极层之上,具有第一侧面部和第二侧面部,该第一侧面部相对于所述基板的基板面形成第一角度,该第二侧面部设于所述第一侧面部之下,相对于所述基板面形成比所述第一角度小的第二角度;以及
树脂,设于所述电极层以及所述半导体芯片的周围,与所述第一侧面部以及所述第二侧面部相接。
2.根据权利要求1所述的半导体装置,
所述第一侧面部在与所述第一侧面部平行的方向上具有以第一间距形成的多个第一扇形边,
所述第二侧面部在与所述第二侧面部平行的方向上具有以第二间距形成的多个第二扇形边。
3.根据权利要求2所述的半导体装置,
所述第二间距比所述第一间距大。
4.根据权利要求2或3所述的半导体装置,
所述第一间距为10μm以下,所述第二间距为10μm以下。
5.一种半导体装置的制造方法,具备如下步骤:
使用掩模来进行设于第一开口部之下的所述半导体基板的第一部分的第一蚀刻,从而形成具有第一侧面部的第一间隙,所述掩模设于在下方具有电极层的所述半导体基板之上,并具有第一宽度的所述第一开口部,
进行所述第一间隙之下的所述半导体基板的第二部分的第二蚀刻,从而形成具有第二侧面部的倒锥形状的第二间隙,
通过形成所述第二间隙,将所述半导体基板断开而形成半导体芯片,
将所述电极层以及所述半导体芯片配置于基板之上,
在所述基板之上的所述半导体芯片的周围形成树脂。
6.根据权利要求5所述的半导体装置的制造方法,
通过进行所述第一蚀刻,在与所述第一侧面部平行的方向上将以第一间距形成的多个第一扇形边形成于所述第一侧面部,
通过进行所述第二蚀刻,在与所述第二侧面部平行的方向上将以第二间距形成的多个第二扇形边形成于所述第二侧面部。
7.根据权利要求6所述的半导体装置的制造方法,
所述第二间距比所述第一间距大。
8.根据权利要求6所述的半导体装置的制造方法,
所述多个第一扇形边的第一间距为10μm以下,所述多个第二扇形边的第二间距为10μm以下。
9.根据权利要求5至8中任一项所述的半导体装置的制造方法,
所述第一蚀刻是作为各向异性蚀刻的第三蚀刻和在所述第三蚀刻之后进行的作为各向同性蚀刻的第四蚀刻的重复,
所述第二蚀刻是作为各向异性蚀刻的第五蚀刻和在所述第五蚀刻之后进行的作为各向同性蚀刻的第六蚀刻的重复,
所述第六蚀刻的时间比所述第四蚀刻的时间长,
所述第六蚀刻的时间在每当进行所述重复时就追加规定时间而变长。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010019852A1 (en) * | 1996-10-17 | 2001-09-06 | Nobuaki Hashimoto | Semiconductor device, method of making the same, circuit board, flexible substrate, and method of making substrate |
US20110175209A1 (en) * | 2010-01-18 | 2011-07-21 | Seddon Michael J | Method of forming an em protected semiconductor die |
CN104637877A (zh) * | 2013-11-13 | 2015-05-20 | 株式会社东芝 | 半导体芯片的制造方法、半导体芯片及半导体装置 |
CN105990432A (zh) * | 2014-09-16 | 2016-10-05 | 株式会社东芝 | 半导体装置及其制造方法 |
US20180096944A1 (en) * | 2016-09-21 | 2018-04-05 | Kabushiki Kaisha Toshiba | Semiconductor device |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177178A (ja) * | 1992-12-01 | 1994-06-24 | Nissan Motor Co Ltd | 半導体チップの構造 |
JP2003163313A (ja) * | 2001-09-13 | 2003-06-06 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
US6759745B2 (en) | 2001-09-13 | 2004-07-06 | Texas Instruments Incorporated | Semiconductor device and manufacturing method thereof |
JP2003124431A (ja) * | 2001-10-17 | 2003-04-25 | Sony Corp | ウェーハ状シート、チップ状電子部品、およびそれらの製造方法 |
US7675153B2 (en) | 2005-02-02 | 2010-03-09 | Kabushiki Kaisha Toshiba | Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof |
JP4434977B2 (ja) | 2005-02-02 | 2010-03-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2006294688A (ja) * | 2005-04-06 | 2006-10-26 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2006351950A (ja) * | 2005-06-17 | 2006-12-28 | Rohm Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP2012182382A (ja) * | 2011-03-02 | 2012-09-20 | Sekisui Chem Co Ltd | 半導体チップ、半導体パッケージおよび半導体パッケージの製造方法 |
JP2013207279A (ja) | 2012-03-29 | 2013-10-07 | Toshiba Corp | 半導体装置の製造方法 |
JP2017120800A (ja) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | 半導体素子、半導体素子の製造方法及び電子機器 |
JP6476418B2 (ja) | 2016-02-04 | 2019-03-06 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法および電子部品実装構造体の製造方法 |
JP6524562B2 (ja) * | 2017-02-23 | 2019-06-05 | パナソニックIpマネジメント株式会社 | 素子チップおよびその製造方法 |
KR20200034503A (ko) * | 2018-09-21 | 2020-03-31 | 삼성전자주식회사 | 기판 쏘잉 방법 및 반도체 칩의 싱귤레이션 방법 |
-
2020
- 2020-03-19 JP JP2020050007A patent/JP7282710B2/ja active Active
- 2020-08-07 CN CN202010787426.1A patent/CN113496963A/zh active Pending
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010019852A1 (en) * | 1996-10-17 | 2001-09-06 | Nobuaki Hashimoto | Semiconductor device, method of making the same, circuit board, flexible substrate, and method of making substrate |
US20110175209A1 (en) * | 2010-01-18 | 2011-07-21 | Seddon Michael J | Method of forming an em protected semiconductor die |
CN104637877A (zh) * | 2013-11-13 | 2015-05-20 | 株式会社东芝 | 半导体芯片的制造方法、半导体芯片及半导体装置 |
CN105990432A (zh) * | 2014-09-16 | 2016-10-05 | 株式会社东芝 | 半导体装置及其制造方法 |
US20180096944A1 (en) * | 2016-09-21 | 2018-04-05 | Kabushiki Kaisha Toshiba | Semiconductor device |
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