JP7476991B2 - 半導体装置と半導体装置の製造方法 - Google Patents
半導体装置と半導体装置の製造方法 Download PDFInfo
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- JP7476991B2 JP7476991B2 JP2023007003A JP2023007003A JP7476991B2 JP 7476991 B2 JP7476991 B2 JP 7476991B2 JP 2023007003 A JP2023007003 A JP 2023007003A JP 2023007003 A JP2023007003 A JP 2023007003A JP 7476991 B2 JP7476991 B2 JP 7476991B2
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- Prior art keywords
- semiconductor
- semiconductor wafer
- dicing
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 213
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 description 56
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 229920005989 resin Polymers 0.000 description 14
- 239000011347 resin Substances 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 229910052759 nickel Inorganic materials 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Dicing (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図面を参照して、実施例1の半導体装置10について説明する。図1に示すように、半導体装置10は、半導体素子12と、金属ブロック20と、上部リードフレーム22と、下部リードフレーム24と、モールド樹脂26と、を有している。
図面を参照して、実施例2の半導体装置110の製造方法について説明する。なお、以下では、主たる工程のみを説明する。したがって、半導体装置110の製造方法には、必要に応じて以下の説明に含まれない一又は複数の工程が含まれ得る。
12:半導体素子
14:半導体基板
14a:上面
14b:下面
14c:端面
15a:第1端面
15b:第2端面
16:上部電極
16a:主電極
16b:信号用配線
18:下部電極
20:金属ブロック
22:上部リードフレーム
24:下部リードフレーム
26:モールド樹脂
28、30、32:はんだ層
34:ニッケル膜
36:ポリイミド膜
40:凸部
42:角部
44:角部
60:半導体ウェハ
60a:上面
60b:下面
61:溝部
62:ダイシング領域
64:素子領域
110:半導体装置
114:半導体ウェハ
116:上部電極
118:下部電極
160:半導体ウェハ
160a:上面
160b:下面
162:ダイシング領域
164:素子領域
166:脆弱層
Claims (1)
- 半導体装置の製造方法であって、
ダイシング領域によって区画されている複数の素子領域を有する半導体ウェハを準備する工程と、
前記半導体ウェハを機械的に薄板化することによって、前記半導体ウェハの一方の主面に脆弱層を形成する工程と、
前記複数の素子領域の各々の前記脆弱層を消失させることにより、前記ダイシング領域の前記脆弱層を選択的に残存させる工程と、
前記半導体ウェハの平面方向に引張応力を加えることによって、前記半導体ウェハを前記複数の素子領域に分割して複数の半導体装置を得る工程と、
を備える、製造方法。
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JP2023007003A JP7476991B2 (ja) | 2019-08-27 | 2023-01-20 | 半導体装置と半導体装置の製造方法 |
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JP2019154913A JP7255424B2 (ja) | 2019-08-27 | 2019-08-27 | 半導体装置と半導体装置の製造方法 |
JP2023007003A JP7476991B2 (ja) | 2019-08-27 | 2023-01-20 | 半導体装置と半導体装置の製造方法 |
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JP2019154913A Division JP7255424B2 (ja) | 2019-08-27 | 2019-08-27 | 半導体装置と半導体装置の製造方法 |
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JP2023052535A JP2023052535A (ja) | 2023-04-11 |
JP7476991B2 true JP7476991B2 (ja) | 2024-05-01 |
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JP2023007003A Active JP7476991B2 (ja) | 2019-08-27 | 2023-01-20 | 半導体装置と半導体装置の製造方法 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003133260A (ja) | 2001-10-19 | 2003-05-09 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2004214431A (ja) | 2003-01-06 | 2004-07-29 | Toshiba Corp | 半導体装置の製造方法 |
JP2006032418A (ja) | 2004-07-12 | 2006-02-02 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2014207382A (ja) | 2013-04-15 | 2014-10-30 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法及び半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207796A (ja) | 2006-01-31 | 2007-08-16 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2008140894A (ja) | 2006-11-30 | 2008-06-19 | Toyota Motor Corp | 半導体装置とその製造方法 |
JP2015138843A (ja) | 2014-01-21 | 2015-07-30 | 株式会社デンソー | 半導体装置及びその製造方法 |
-
2019
- 2019-08-27 JP JP2019154913A patent/JP7255424B2/ja active Active
-
2023
- 2023-01-20 JP JP2023007003A patent/JP7476991B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003133260A (ja) | 2001-10-19 | 2003-05-09 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2004214431A (ja) | 2003-01-06 | 2004-07-29 | Toshiba Corp | 半導体装置の製造方法 |
JP2006032418A (ja) | 2004-07-12 | 2006-02-02 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2014207382A (ja) | 2013-04-15 | 2014-10-30 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法及び半導体装置 |
Also Published As
Publication number | Publication date |
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JP2023052535A (ja) | 2023-04-11 |
JP2021034622A (ja) | 2021-03-01 |
JP7255424B2 (ja) | 2023-04-11 |
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