CN113488532A - Electrode of p-type gallium nitride-based device and preparation method and application thereof - Google Patents
Electrode of p-type gallium nitride-based device and preparation method and application thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 17
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention provides an electrode of a p-type gallium nitride-based device and a preparation method and application thereof. The electrode comprises a nickel layer, a platinum layer and a gold layer which are sequentially stacked, wherein the platinum layer is positioned between the nickel layer and the gold layer, and the nickel layer is an ohmic contact layer of a p-type gallium nitride-based device. The electrode of the p-type gallium nitride-based device solves the problem that ohmic contact resistance is increased due to the fact that Schottky barrier height is increased due to diffusion of metal electrode materials, meanwhile, a GaO thin layer of a semiconductor interface is converted into a NiO semiconductor layer, Ga vacancy at a metal/p-type GaN interface is improved, source and drain ohmic contact resistance is further reduced, the problem that ohmic contact resistance of a source electrode and a drain electrode of the p-type gallium nitride-based device is high is finally solved, the performance of a p-type gallium nitride transistor is improved, and the p-type gallium nitride-based device can play a greater role in a CMOS circuit.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and relates to an electrode of a p-type gallium nitride-based device, a preparation method and application thereof.
Background
Wide Bandgap (WBG) semiconductors, such as silicon carbide SiC and gallium nitride GaN, are considered to be the most potential materials in next generation power electronics devices. They can be used for manufacturing devices that can operate at higher voltages, higher temperatures and higher frequencies than silicon materials by virtue of extraordinary physical properties such as band gap >3eV, high critical electric field (2-4MV/cm) and low intrinsic carrier concentration (-10 [ (cm) [ [ 10 ]) ] (-3) ]. GaN material is the mainstream material of wide bandgap semiconductor material, and a special aspect of the GaN material is that an AlGaN/GaN heterostructure can be grown, and a two-dimensional electron gas (2DEG) is generated at an interface through piezoelectric polarization gradient, and the existence of the 2DEG enables a GaN-based High Electron Mobility Transistor (HEMT) to have lower channel resistance compared with Si and SiC devices. HEMTs have attracted considerable attention in high power and high temperature applications due to their many advantages, such as high electron mobility, saturation velocity, high carrier concentration at the heterojunction interface, high breakdown field, and low thermal resistance. With the development of high integration, the GaN HEMT has a lower channel resistance, so that the GaN HEMT is used as a channel material of a cmos transistor, and the efficiency of a high-power gate drive circuit is effectively improved.
However, the performance of p-type GaN transistors is still significantly lower than that of n-type GaN devices, which greatly weakens the pull-up network of CMOS circuits. One important factor contributing to poor performance of p-type GaN transistors is poor quality of ohmic contacts of source/drain electrodes of p-type GaN devices due to low density of ionization acceptors due to large activation energy of p-type dopants. The ohmic contact is a substrate of a GaN transistor, which is a bridge for connecting a device to an external circuit, and is used for transmission of an electric signal, and it is desirable that the ohmic contact resistance is as small as possible. The lower the ohmic resistance, the lower the loss and the higher the device efficiency. Ohmic contact is related to the metal/semiconductor schottky barrier height phi _ B, which is related to the work function phi _ m of the metal, and ohmic resistance can be reduced by selecting a suitable value of phi _ m for the metal material. Finding an effective contact metal scheme for p-type GaN is therefore a great challenge.
A great deal of research is carried out on the aspect of selecting a proper metal material scheme for p-type GaN, and the existing ohmic metal combination schemes comprise Cr/Au, Pt/Au, Pd/Au, Pt/Ni/Au, Pd/Ni/Au, Ta/Ti, Pt/Ni/Au, Ni/Pd/Au, Ti/Pt/Au, Ni/ITO, Ru and Ir, Ru/Ni, Ir/Ni, Au/Ni/Au, Ni/AlZnO, Ni/Ag, Pd/Ni/Au, Ag, Ni/Au/TaN/Ti/Au, Ni/Au/TiN/Ti/Au, Ni/Au/ZrN/Ti/Au, Ni/Ag/Ni, Ni/Ag/Au or Pd/Pt/Au. Rhoc(specific contact resistance, used to describe the ohmic contact resistance) ranges from ^ 10 to ^ (-10) & spiral (-5) omega ^ cm 2, which is about 1-2 orders of magnitude higher than that of n-type GaN, and the existing metal material scheme still can not meet the development requirement, so there is a great space for forming a stable and reliable metal material scheme with small ohmic resistance for p-type GaN.
CN111599865A discloses a GaN-based P-channel MOSFET and a preparation method thereof, belonging to the technical field of electronic materials. The invention utilizes the principle that two-dimensional hole gas (2DHG) formed after fluorine positive ions are injected into gallium nitride (GaN) can form a conductive channel below a GaN surface layer, and fluorine ions are injected into the GaN to prepare the GaN-based P-channel MOSFET. In the literature, an ion implantation method is adopted to perform N-type implantation doping on a source-drain electrode region, so that the doping concentration of a contact layer is increased, and the tunneling probability is improved, thereby reducing the ohmic contact resistance.
CN104409344A discloses a method for reducing specific contact resistivity of Ni/Au and p-GaN ohmic contact, which comprises the following steps: step 1: growing a heavily doped p-GaN thin layer on the p-GaN layer; step 2: carrying out Mg activation annealing on the p-GaN layer and the p-GaN thin layer; and step 3: growing a heavily doped p-InGaN thin layer on the p-GaN thin layer; and 4, step 4: carrying out Mg activation annealing on the p-InGaN thin layer to form a sample; and 5: processing the surface of the sample, and photoetching the surface of the sample to form a pattern; step 6: evaporating the Ni/Au metal layer on the surface of the sample by electron beam evaporation; and 7: stripping the redundant Ni/Au metal layer; and 8: and annealing to form Ni/Au alloy to form ohmic contact, thereby completing the preparation. The Ni/Au combination in this document has some drawbacks, mainly due to the inward diffusion of Au, the Au-Ni solid solution formed by the outward diffusion and the inward diffusion of Ni, and the formation of NiO on the metal surface by the outward diffusion of Ni. So that the ohmic contact resistance of gallium nitride becomes high.
How to reduce the ohmic contact resistance of a p-type gallium nitride device, solve the problems of Schottky barrier height increase caused by metal electrode material diffusion and Ga vacancy concentration at a metal/p-type GaN interface, and is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide an electrode of a p-type gallium nitride-based device, and a preparation method and application thereof. The electrode of the p-type gallium nitride-based device solves the problem of Schottky barrier height increase caused by mutual diffusion of metal electrode materials, eliminates oxide or pollutants on a semiconductor interface by forming a NiO semiconductor on the metal and semiconductor interface, increases the Ga vacancy concentration at the metal/p-type GaN interface, finally improves the problem of high ohmic contact resistance of a source electrode and a drain electrode of the p-type gallium nitride-based device, improves the performance of the p-type gallium nitride transistor, and enables the p-type gallium nitride-based device to play a greater role in a CMOS circuit.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the invention provides an electrode of a p-type gallium nitride-based device, which comprises a nickel layer, a platinum layer and a gold layer which are sequentially stacked, wherein the platinum layer is positioned between the nickel layer and the gold layer, and the nickel layer is an ohmic contact layer of the p-type gallium nitride-based device.
In the invention, Ni is used as an ohmic contact layer to form ohmic contact with p-type gallium nitride, Au has excellent stability and is used as a protective layer to protect a source and drain metal stacking structure of a device from being oxidized and polluted, and Pt is used as a diffusion barrier layer to have high metal melting point, high conductivity, good thermal stability and chemical stability, so that Au is prevented from diffusing inwards to increase the Schottky barrier height at a metal semiconductor interface; meanwhile, the outward diffusion of Ni is prevented, the probability of forming a NiO semiconductor on the surface of p-GaN by Ni is improved, more oxides or pollutants on the interface of the semiconductor are dissociated, the Ga vacancy concentration at the metal/p-type GaN interface is increased, and finally, the electrode can form stable ohmic contact with small resistance, so that the problem of high ohmic contact resistance of the electrode of the p-type gallium nitride-based device is solved, the performance of the p-type gallium nitride transistor is improved, and the p-type gallium nitride-based device can play a greater role in a CMOS circuit.
Although the Ni/Au combination is a better metal combination scheme in the metal combination of the existing electrode (source and drain) ohmic contact, the Ni/Au combination also has some defects, which are mainly reflected in Au inward diffusion, Au-Ni solid solution formed by Ni outward diffusion and Au inward diffusion and NiO formed by Ni outward diffusion on the metal surface. On the one hand, the electronegativity values of Au, Ni and Ga are 2.4, 1.91 and 1.6 respectively, and the electronegativity difference of Au and Ga is larger than that of Ni and Ga, which means that Au atoms can reach the surface of p-type gallium nitride more easily. However, the Schottky barrier height of the Au/p-type GaN interface is greater than that of Ni/p-type GaN, i.e., the inward diffusion of Au degrades the ohmic contact characteristics of the Ni/Au combination. On the other hand, Ni outdiffusion and Au like outdiffusion to form Au-Ni solid solution, which outdiffusion reduces the dissociation of oxides or contaminants on the semiconductor surface that can increase the schottky barrier height, while not contributing to the separation of the O element in the Ga-O oxide to create more Ga vacancy concentration at the metal/p-type GaN interface. On the last hand, Ni diffuses out on the surface of Au and combines with oxygen element in the environment to form NiO semiconductor, thereby reducing the conductivity of the source and drain metal electrodes. It is therefore necessary to interpose a diffusion barrier layer between the Ni/Au layers to prevent the inward diffusion of Au and the outward diffusion of Ni/Au. The above problems can be solved when a Pt diffusion barrier layer having a higher metal melting point, high electrical conductivity, good thermal stability and chemical stability is added.
Preferably, the thickness of the electrode is 20 to 200nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80n, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, or 200nm, and the like.
Preferably, the thickness of the platinum layer is greater than or equal to the thickness of the nickel layer and less than the thickness of the gold layer.
In the invention, the thickness of the electrode cannot be too thick, which can cause that the metal in the non-source drain region can not completely fall off in the stripping process, and meanwhile, the thickness of the electrode cannot be too thin, which can cause poor thermal stability of the electrode.
Preferably, the thickness of the nickel layer is 5-50 nm, such as 5nm, 8nm, 10nm, 13nm, 15nm, 18nm, 25nm, 30nm, 40nm or 50 nm.
Preferably, the thickness of the platinum layer is 5 to 50nm, such as 5nm, 8nm, 10nm, 13nm, 15nm, 18nm, 25nm, 30nm, 40nm or 50 nm.
Preferably, the gold layer has a thickness of 10 to 100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, or 100 nm.
In the invention, the thicknesses of the nickel layer, the platinum layer and the gold layer cannot be too thin or too thick, the adhesion between the Ni layer and a semiconductor is poor due to too small Ni thickness, the barrier cannot be caused due to too small Pt thickness, the mutual diffusion of Ni and Au occurs, the oxygen can diffuse into an electrode layer due to too small Au thickness, so that the oxidation prevention effect cannot be realized, and the incomplete metal stripping can be caused in the electrode preparation process if each layer of metal is too thick.
In a second aspect, the present invention provides a method for producing an electrode of a p-type gallium nitride-based device according to the first aspect, the method comprising the steps of:
(1) carrying out regionalization treatment on the p-type gallium nitride epitaxial structure to expose an electrode region of the p-type gallium nitride-based device;
(2) and sequentially depositing a nickel layer, a platinum layer and a gold layer on the electrode area of the p-type gallium nitride-based device, and then carrying out metal stripping to obtain the electrode of the p-type gallium nitride-based device.
In the present invention, the p-type gallium nitride epitaxial structure includes p-type gallium nitride grown along the epitaxial structure, all of which are part of the epitaxial structure.
The preparation method provided by the invention is simple to operate, and can uniformly obtain the electrode with good performance and low ohmic contact resistance.
Preferably, the regionalization process of step (1) includes:
and spin-coating photoresist on the p-type gallium nitride epitaxial structure, and then carrying out exposure development.
Preferably, the electrode region of the p-type gallium nitride-based device obtained in the step (1) is subjected to etching treatment.
In the invention, the electrode area is further etched, which is beneficial to removing the oxide on the surface, thereby eliminating the problem of Schottky barrier rising caused by the oxide on the surface.
Preferably, the etching process comprises a dry etching process.
In the invention, the purpose of dry etching is to remove the p-type gallium nitride in the electrode region along the vertical direction, the electrode region of the p-type gallium nitride-based device can be etched completely, and the electrode region of the p-type gallium nitride-based device can also be patterned, wherein the pattern includes, but is not limited to, a circle, a rectangle, a pentagon, a hexagon, and the like.
Preferably, after the electrode region of the p-type gallium nitride-based device obtained in the step (1) is etched, the operation of removing the photoresist is continued, and then the double-layer photoresist for the liftoff process is spin-coated again.
Preferably, the deposition method in step (2) is vacuum magnetron sputtering and/or electron beam evaporation.
As a preferred technical scheme of the invention, the preparation method of the electrode of the p-type gallium nitride-based device comprises the following steps:
(1) spin-coating photoresist on the p-type gallium nitride epitaxial structure, and then performing exposure and development to expose an electrode region of the p-type gallium nitride-based device;
(2) carrying out dry etching treatment on the electrode area of the p-type gallium nitride-based device obtained in the step (1) to obtain a treated sample;
(3) removing the photoresist from the processed sample obtained in the step (2), and spin-coating the double-layer photoresist for lift-off process again
(4) And (4) sequentially depositing a nickel layer, a platinum layer and a gold layer in the electrode area of the p-type gallium nitride-based device treated in the step (3) by using a vacuum magnetron sputtering method, and then carrying out metal stripping to obtain the electrode of the p-type gallium nitride-based device.
In a third aspect, the present invention further provides a p-type gallium nitride-based device, where the p-type gallium nitride-based device includes a substrate, a p-type gallium nitride epitaxial structure, and an electrode of the p-type gallium nitride-based device according to the first aspect, where the p-type gallium nitride epitaxial structure is located on a surface of the substrate, and the electrode is located on the p-type gallium nitride epitaxial structure;
the electrodes of the p-type gallium nitride-based device according to the first aspect serve as a source and a drain in the p-type gallium nitride-based device.
In the invention, the manufacturing processes of the source electrode and the drain electrode need to be kept consistent, namely the total thickness is consistent, and the thickness of each metal layer is also consistent.
Preferably, the substrate comprises any one of sapphire, silicon or silicon carbide or a combination of at least two thereof.
Compared with the prior art, the invention has the following beneficial effects:
the p-type gallium nitride-based device provided by the invention has the advantages that the Ni/Pt/Au is arranged in a laminated mode, the barrier layer Pt with the advantages of high melting point, high conductivity, good thermal stability, good chemical stability and the like is added, the Au can be prevented from diffusing inwards and the Ni can be prevented from diffusing outwards, the problems of increase of Schottky barrier height caused by diffusion of metal electrode materials and increase of generation of Ni and oxide on the surface of a semiconductor are solvedReaction is carried out, so that the Ga vacancy concentration at the metal/p-type GaN interface is improved, the problem of high ohmic contact resistance of a source electrode and a drain electrode of the p-type gallium nitride-based device is finally solved, the performance of the p-type gallium nitride transistor is improved, the p-type gallium nitride-based device can play a greater role in a CMOS circuit, and the specific contact resistance of the p-type gallium nitride-based device can be reduced to 10-5～10-7Ω·mm2。
Drawings
Fig. 1 is a schematic structural view of a p-type gallium nitride-based device provided in example 1.
1-substrate, 2-p type gallium nitride epitaxial structure, 3-p type gallium nitride, 4-electrode, 41-nickel layer, 42-platinum layer and 43-gold layer.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments. It should be understood by those skilled in the art that the examples are only for the understanding of the present invention and should not be construed as the specific limitations of the present invention.
Example 1
As shown in fig. 1: the embodiment provides an electrode of a p-type gallium nitride-based device, wherein the electrode 4 comprises a nickel layer 41, a platinum layer 42 and a gold layer 43 which are sequentially stacked, wherein the platinum layer 42 is located between the nickel layer 41 and the gold layer 43, and the nickel layer 41 is an ohmic contact layer of the p-type gallium nitride-based device; the electrode 4 includes a source electrode and a drain electrode.
The thickness of the source electrode is 125nm, wherein the thickness of the nickel layer is 15nm, the thickness of the platinum layer is 30nm, and the thickness of the gold layer is 80 nm.
The thickness of the drain electrode is 125nm, wherein the thickness of the nickel layer is 15nm, the thickness of the platinum layer is 30nm, and the thickness of the gold layer is 80 nm.
The preparation method of the electrode comprises the following steps:
(1) a layer of photoresist is spin-coated on the P-type gallium nitride 3 included in the P-type gallium nitride epitaxial structure 2, and then after exposure and development, the source electrode and the drain electrode area of the P-type gallium nitride-based device are exposed;
(2) within 10min before metal deposition, HCl: H2O ═ 1: 4, soaking the sample in the step (1) for 60s, removing oxides on the surfaces of the gallium nitride in the source electrode area and the drain electrode area, washing with deionized water for 3min after soaking, and drying moisture with nitrogen;
(3) placing the sample treated in the step (2) into a sample injection chamber of a vacuum magnetron sputtering device of a Cotelicaceae type Lab18 at 10 DEG-7Under Pa, sequentially depositing a nickel layer 41, a platinum layer 42 and a gold layer 43 on the source electrode and drain electrode regions of the p-type gallium nitride-based device;
(4) and (4) after the deposition in the step (3) is finished, performing metal stripping on the deposited metal layer by using a DMSO (dimethyl ethyl maple) solution in a water bath at 90 ℃ to obtain the electrode 4 of the p-type gallium nitride-based device.
The embodiment also provides a p-type gallium nitride-based device, the device comprises a substrate 1, a p-type gallium nitride epitaxial structure 2 and the electrode 4 (source and drain) prepared in the above way, which are sequentially stacked, wherein the substrate 1 is a sapphire substrate.
Example 2
This example is different from example 1 in that, unlike the method of preparing the electrode, the electrode is etched to form a pit in the electrode region, and then metal is deposited on the pit.
The preparation method comprises the following specific steps:
(1) depositing a layer of silicon nitride with the thickness of 100nm on the p-type gallium nitride epitaxial structure to be used as a hard mask, then spin-coating a layer of photoresist, and exposing a source electrode area and a drain electrode area of the p-type gallium nitride-based device after exposure and development;
(2) removing the silicon nitride covering the source electrode region and the drain electrode region in the step (1) by ICP dry etching; simultaneously cleaning the photoresist, washing the sample wafer for 3min by deionized water, and finally drying by nitrogen;
(3) after the step (2), etching the source electrode area and the drain electrode area which are not covered by the silicon nitride by ICP (inductively coupled plasma), wherein the etching depth is 5 nm;
(4) soaking the sample treated in the step (3) in BOE for 3min, then washing with deionized water for 3min, and drying with nitrogen;
(5) within 10min before metal deposition, HCl: h2O is 1: 4 solution ofSoaking the sample treated in the step (4) for 60s, washing with deionized water for 3min after soaking, and drying moisture with nitrogen;
(6) placing the sample treated in the step (5) into a sample injection chamber of a vacuum magnetron sputtering device of a Coteliki Lab18 model at 10-7Under Pa, sequentially depositing a nickel layer, a platinum layer and a gold layer on the source electrode and the drain electrode area of the p-type gallium nitride-based device;
(7) and (4) after the deposition in the step (6) is finished, performing metal stripping on the deposited metal layer by using a DMSO (dimethyl ethyl maple) solution in a water bath at 90 ℃ to obtain the electrode of the p-type gallium nitride-based device.
Example 3
The difference between the electrode provided in this embodiment and embodiment 2 is that the electrode is patterned to present etching holes distributed in a matrix at intervals in the electrode region.
The difference between this embodiment and embodiment 2 further includes that, between step (2) and step (3), a step is added, and the added step is:
after the cleaning in the step (2), spin-coating a layer of photoresist on the source electrode area and the drain electrode area, and then exposing and developing to enable the source electrode area and the drain electrode area to be provided with a plurality of rectangles;
the remaining preparation methods and parameters were in accordance with example 2.
Example 4
The embodiment provides an electrode of a p-type gallium nitride-based device, which comprises a nickel layer, a platinum layer and a gold layer which are sequentially stacked, wherein the platinum layer is positioned between the nickel layer and the gold layer, and the nickel layer is an ohmic contact layer of the p-type gallium nitride-based device; the electrodes include a source electrode and a drain electrode.
The thickness of the source electrode is 20nm, wherein the thickness of the nickel layer is 5nm, the thickness of the platinum layer is 5nm, and the thickness of the gold layer is 10 nm.
The thickness of the drain electrode is 20nm, wherein the thickness of the nickel layer is 5nm, the thickness of the platinum layer is 5nm, and the thickness of the gold layer is 10 nm.
The preparation method of the electrode in this example was identical to that of example 1.
The embodiment also provides a p-type gallium nitride-based device, which comprises a silicon substrate, a p-type gallium nitride epitaxial structure, and the source electrode and the drain electrode which are sequentially stacked.
Example 5
The embodiment provides an electrode of a p-type gallium nitride-based device, which comprises a nickel layer, a platinum layer and a gold layer which are sequentially stacked, wherein the platinum layer is positioned between the nickel layer and the gold layer, and the nickel layer is an ohmic contact layer of the p-type gallium nitride-based device; the electrodes include a source electrode and a drain electrode.
The thickness of the source electrode is 200nm, wherein the thickness of the nickel layer is 50nm, the thickness of the platinum layer is 50nm, and the thickness of the gold layer is 100 nm.
The thickness of the drain electrode is 200nm, wherein the thickness of the nickel layer is 50nm, the thickness of the platinum layer is 50nm, and the thickness of the gold layer is 100 nm.
The preparation method of the electrode in this example was identical to that of example 1.
The embodiment also provides a p-type gallium nitride-based device, which comprises a silicon carbide substrate, a p-type gallium nitride epitaxial structure, and the source electrode and the drain electrode which are sequentially stacked.
Comparative example 1
The comparison example provides an electrode of a p-type gallium nitride-based device, and the electrode comprises a nickel layer and a gold layer which are sequentially stacked, wherein the nickel layer is an ohmic contact layer of the p-type gallium nitride-based device; the electrodes include a source electrode and a drain electrode.
The thickness of the source electrode is 70nm, wherein the thickness of the nickel layer is 20nm, and the thickness of the gold layer is 50 nm.
The thickness of the drain electrode is 70nm, wherein the thickness of the nickel layer is 20nm, and the thickness of the gold layer is 50 nm.
The preparation method of the electrode comprises the following steps:
(1) spin-coating a layer of photoresist on the P-type gallium nitride included in the P-type gallium nitride epitaxial structure, and exposing the source electrode and the drain electrode area of the P-type gallium nitride-based device after exposure and development;
(2) placing the sample into a sample chamber 10 of a vacuum magnetron sputtering device of a Coteliki Lab18 model-7Under Pa, sequentially depositing a nickel layer and a gold layer in a source electrode area and a drain electrode area of the p-type gallium nitride-based device;
(3) and (3) after the deposition in the step (2) is finished, carrying out metal stripping on the deposited metal layer by using a DMSO (dimethyl ethyl maple) solution in a water bath at 90 ℃ to obtain the electrode of the p-type gallium nitride-based device.
The present comparative example also provides a p-type gallium nitride-based device comprising a sapphire substrate, a p-type gallium nitride epitaxial structure, and the source and drain fabricated as described above, stacked in sequence.
Comparative example 2
The comparison example provides an electrode of a p-type gallium nitride-based device, and the electrode comprises a platinum layer, a nickel layer and a gold layer which are sequentially stacked, wherein the nickel layer is positioned between the platinum layer and the gold layer, and the platinum layer is an ohmic contact layer of the p-type gallium nitride-based device; the electrodes include a source electrode and a drain electrode.
The thickness of the source electrode is 125nm, wherein the thickness of the platinum layer is 30nm, the thickness of the nickel layer is 15nm, and the thickness of the gold layer is 80 nm.
The thickness of the drain electrode is 125nm, the thickness of the platinum layer is 30nm, the thickness of the nickel layer is 15nm, and the thickness of the gold layer is 80 nm.
The preparation method of the electrode comprises the following steps:
(1) spin-coating a layer of photoresist on the P-type gallium nitride included in the P-type gallium nitride epitaxial structure, and exposing the source electrode and the drain electrode area of the P-type gallium nitride-based device after exposure and development;
(2) within 10min before metal deposition, HCl: H2O ═ 1: 4, soaking the sample in the step (1) for 60s, removing oxides on the surfaces of the gallium nitride in the source electrode area and the drain electrode area, washing with deionized water for 3min after soaking, and drying moisture with nitrogen;
(3) putting the sample processed in the step (2) into a Coteleiseke with the model number Lab18 in a sample introduction chamber of a vacuum magnetron sputtering device of the vacuum magnetron sputtering device, 10-7Under Pa, sequentially depositing a platinum layer, a nickel layer and a gold layer in the source electrode and drain electrode areas of the p-type gallium nitride-based device;
(4) and (4) after the deposition in the step (3) is finished, carrying out metal stripping on the deposited metal layer by using a DMSO (dimethyl ethyl maple) solution in a water bath at 90 ℃ to obtain the electrode of the p-type gallium nitride-based device.
The present comparative example also provides a p-type gallium nitride-based device comprising a sapphire substrate, a p-type gallium nitride epitaxial structure, and the source and drain fabricated as described above, stacked in sequence.
Specific contact resistance ρ of the p-type gallium nitride-based devices provided in examples 1 to 5 and comparative examples 1 to 2 was testedcThe results are shown in Table 1.
And (3) testing conditions are as follows: I-V curves were measured using a circular transmission line model and a Keithley 4200-SCS analyzer to derive the specific contact resistance ρc。
TABLE 1
From the data results of example 1 and examples 2 and 3, it is known that further etching is performed on the region of the electrode where the source and drain are exposed, which is beneficial to removing the surface oxide and reducing the specific contact resistance.
As is apparent from the data results of example 1 and comparative example 1, when no platinum layer is added to the electrode, metal diffusion is caused, thereby increasing the specific contact resistance.
As can be seen from the data results of example 1 and comparative example 2, when the ohmic contact layer was changed to a platinum layer, thermal stability was deteriorated and the ohmic contact was unstable.
To sum up, when Ni is used as an ohmic contact layer to form ohmic contact with p-type gallium nitride, Au is used as a protective layer, and Pt is used as a diffusion barrier layer at the middle, the ohmic contact resistance of the p-type gallium nitride-based device can be significantly reduced, and finally, the performance of the p-type gallium nitride transistor is improved, so that the p-type gallium nitride-based device can play a greater role in a CMOS circuit.
The applicant declares that the above description is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and it should be understood by those skilled in the art that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are within the scope and disclosure of the present invention.
Claims (10)
1. The electrode of the p-type gallium nitride-based device is characterized by comprising a nickel layer, a platinum layer and a gold layer which are sequentially stacked, wherein the platinum layer is positioned between the nickel layer and the gold layer, and the nickel layer is an ohmic contact layer of the p-type gallium nitride-based device.
2. The electrode of the p-type gallium nitride-based device according to claim 1, wherein the thickness of the electrode is 20 to 200 nm;
preferably, the thickness of the platinum layer is greater than or equal to the thickness of the nickel layer and less than the thickness of the gold layer.
3. The electrode of the p-type gallium nitride-based device according to claim 1 or 2, wherein the nickel layer has a thickness of 5 to 50 nm.
4. The electrode of a p-type gallium nitride-based device according to any one of claims 1 to 3, wherein the thickness of the platinum layer is 5 to 50 nm.
5. The electrode of the p-type gallium nitride-based device according to any one of claims 1 to 4, wherein the gold layer has a thickness of 10 to 100 nm.
6. The method for fabricating an electrode of a p-type gallium nitride-based device according to any one of claims 1 to 5, comprising the steps of:
(1) carrying out regionalization treatment on the p-type gallium nitride epitaxial structure to expose an electrode region of the p-type gallium nitride-based device;
(2) and sequentially depositing a nickel layer, a platinum layer and a gold layer on the electrode area of the p-type gallium nitride-based device, and then carrying out metal stripping to obtain the electrode of the p-type gallium nitride-based device.
7. The method for preparing an electrode of a p-type gallium nitride-based device according to claim 6, wherein the regionalization process of step (1) comprises:
spin-coating photoresist on the p-type gallium nitride epitaxial structure, and then performing exposure development;
preferably, the electrode area of the p-type gallium nitride-based device obtained in the step (1) is etched;
preferably, the etching treatment comprises a dry etching treatment;
preferably, after etching the electrode region of the p-type gallium nitride-based device obtained in the step (1), continuously removing the photoresist, and then spin-coating the double-layer photoresist for the liftoff process again;
preferably, the deposition method in step (2) is vacuum magnetron sputtering and/or electron beam evaporation.
8. The method for fabricating an electrode of a p-type gallium nitride-based device according to claim 6 or 7, comprising the steps of:
(1) spin-coating photoresist on the p-type gallium nitride epitaxial structure, and then performing exposure and development to expose an electrode region of the p-type gallium nitride-based device;
(2) carrying out dry etching treatment on the electrode area of the p-type gallium nitride-based device obtained in the step (1) to obtain a treated sample;
(3) removing photoresist from the processed sample obtained in the step (2), and spin-coating double-layer photoresist for lift-off process again;
(4) and (4) sequentially depositing a nickel layer, a platinum layer and a gold layer in the electrode area of the p-type gallium nitride-based device treated in the step (3) by using a vacuum magnetron sputtering method, and then carrying out metal stripping to obtain the electrode of the p-type gallium nitride-based device.
9. A p-type gallium nitride-based device, comprising a substrate, a p-type gallium nitride epitaxial structure and an electrode of the p-type gallium nitride-based device according to any one of claims 1 to 5, wherein the substrate, the p-type gallium nitride epitaxial structure and the electrode are sequentially stacked, and the p-type gallium nitride epitaxial structure is positioned on the surface of the substrate;
the electrodes of a p-type gallium nitride-based device according to any one of claims 1-5 are used as source and drain electrodes in the p-type gallium nitride-based device.
10. The p-type gallium nitride-based device of claim 9, wherein the substrate comprises any one of sapphire, silicon, or silicon carbide, or a combination of at least two thereof.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1140846A (en) * | 1997-07-15 | 1999-02-12 | Nec Corp | P-type electrode of gallium nitride semiconductor and manufacture thereof |
| CN1291793A (en) * | 1999-04-22 | 2001-04-18 | 索尼株式会社 | Method of making semi conductor device |
| JP2004040061A (en) * | 2002-07-08 | 2004-02-05 | Sumitomo Chem Co Ltd | Electrode for group iii-v compound semiconductor, manufacturing method thereof, and semiconductor light emitting element using the same |
| CN1484327A (en) * | 1993-04-28 | 2004-03-24 | ���ǻ�ѧ��ҵ��ʽ���� | Gallium nitride-based III-V group compound semiconductor |
| CN101636820A (en) * | 2007-03-28 | 2010-01-27 | 松下电器产业株式会社 | Ohmic electrode structure and semiconductor element |
-
2021
- 2021-07-14 CN CN202110796382.3A patent/CN113488532A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1484327A (en) * | 1993-04-28 | 2004-03-24 | ���ǻ�ѧ��ҵ��ʽ���� | Gallium nitride-based III-V group compound semiconductor |
| JPH1140846A (en) * | 1997-07-15 | 1999-02-12 | Nec Corp | P-type electrode of gallium nitride semiconductor and manufacture thereof |
| CN1291793A (en) * | 1999-04-22 | 2001-04-18 | 索尼株式会社 | Method of making semi conductor device |
| JP2004040061A (en) * | 2002-07-08 | 2004-02-05 | Sumitomo Chem Co Ltd | Electrode for group iii-v compound semiconductor, manufacturing method thereof, and semiconductor light emitting element using the same |
| CN101636820A (en) * | 2007-03-28 | 2010-01-27 | 松下电器产业株式会社 | Ohmic electrode structure and semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023115710A1 (en) * | 2021-12-21 | 2023-06-29 | 南方科技大学 | P-gan ohmic contact electrode and preparation method therefor, and electronic element |
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