TWI641133B - Semiconductor cell - Google Patents
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Abstract
一種半導體單元，包括基板、通道層、第一阻障層、疊層、第一電極和第二電極。通道層具有第一能隙，且位於基板上方；第一阻障層位於該通道層上方，具有第二能隙，且第二能隙大於第一能隙；疊層位於第一阻障層上方，包含非三五族半導體磊晶層或氮化矽層，和p型半導體層；第一電極位於第一阻障層上方；以及第二電極，位於該第一阻障層上方，且與該第一電極分離。A semiconductor unit includes a substrate, a channel layer, a first barrier layer, a laminate, a first electrode, and a second electrode. The channel layer has a first energy gap and is located above the substrate; the first barrier layer is above the channel layer, has a second energy gap, and the second energy gap is larger than the first energy gap; the stack is above the first barrier layer a non-three-five semiconductor epitaxial layer or a tantalum nitride layer, and a p-type semiconductor layer; the first electrode is located above the first barrier layer; and the second electrode is located above the first barrier layer, and The first electrode is separated.
Description
本發明是關於一種半導體單元，更具體而言，關於一種具有保護層的半導體單元。The present invention relates to a semiconductor unit, and more particularly to a semiconductor unit having a protective layer.
氮化鋁鎵/氮化鎵高電子遷移率電晶體為一具有發展潛力的下一代高功率元件。由於它們優越的材料特性，可以在高溫高壓下維持穩固的元件特性。The aluminum gallium nitride/gallium nitride high electron mobility transistor is a next generation high power component with potential for development. Due to their superior material properties, stable component characteristics can be maintained at high temperatures and pressures.
本發明提出一種半導體單元，包括基板、緩衝層、通道層、第一阻障層、疊層、源極、汲極和閘極。緩衝層位於基板的上方；通道層具有第一能隙，且位於緩衝層上方；第一阻障層位於該通道層上方，具有第二能隙，且第二能隙大於第一能隙；疊層位於第一阻障層上方，包含一氮化矽層以及一第一導電型化合物半導體層；源極位於第一阻障層上方；汲極位於第一阻障層上方，且與源極相互分隔；閘極位於源極與汲極之間。The invention provides a semiconductor unit comprising a substrate, a buffer layer, a channel layer, a first barrier layer, a stack, a source, a drain and a gate. The buffer layer is located above the substrate; the channel layer has a first energy gap and is located above the buffer layer; the first barrier layer is located above the channel layer, has a second energy gap, and the second energy gap is larger than the first energy gap; The layer is located above the first barrier layer and comprises a tantalum nitride layer and a first conductivity type compound semiconductor layer; the source is located above the first barrier layer; the drain is located above the first barrier layer and is opposite to the source Separate; the gate is located between the source and the drain.
本發明提出一種半導體單元，包括基板、通道層、第一阻障層、疊層、第一電極和第二電極。通道層具有第一能隙，且位於基板上方；第一阻障層位於該通道層上方，具有第二能隙，且第二能隙大於第一能隙；疊層位於第一阻障層上方，包含非三五族半導體磊晶層或氮化矽層，和p型半導體層；第一電極位於第一阻障層上方；以及第二電極，位於該第一阻障層上方，且與該第一電極分離。The invention provides a semiconductor unit comprising a substrate, a channel layer, a first barrier layer, a laminate, a first electrode and a second electrode. The channel layer has a first energy gap and is located above the substrate; the first barrier layer is above the channel layer, has a second energy gap, and the second energy gap is larger than the first energy gap; the stack is above the first barrier layer a non-three-five semiconductor epitaxial layer or a tantalum nitride layer, and a p-type semiconductor layer; the first electrode is located above the first barrier layer; and the second electrode is located above the first barrier layer, and The first electrode is separated.
本發明之實施例如說明與圖式所示，相同或類似之部分係以相同編號標示於圖式或說明書之中。The implementation of the present invention is, for example, the same or similar parts as those shown in the drawings.
請參閱第1圖，第1圖為本發明第一實施例之半導體元件S的上視圖。半導體元件S例如為三端點的元件。於本實施例中，半導體元件S包含源極墊S70、汲極墊S80、閘極墊S90和多個半導體單元1。半導體單元1例如是場效電晶體，具體來說可以是高電子遷移率電晶體(HEMT)。另外，以作動的方式來區別時，半導體單元1為可以是常開型電晶體也可以是常關電晶體。於第一實施例中，半導體單元1包括與源極墊S70電連接之源極70、與汲極墊S80電連接之汲極、與閘極墊S90電連接之閘極90，以及半導體疊層(未標示)，疊層的材料、位置與外觀設計可依實際的需求而做調整。此外，半導體元件S所包含的多個半導體單元1適用於其他實施例中的半導體單元，舉例來說可將第二實施例至第六實施例中的半導體單元2、3、4、5、6取代第一實施例之半導體單元1。為了清楚說明不同實施例中半導體單元2、3、4、5、6的細部結構，另將半導體單元2、3、4、5、6局部放大，詳請參閱第2A圖、第3A圖、第4A圖、第5A圖，以及第6A圖。半導體單元2、3、4、5、6被放大的部位相對於半導體S之位置，標示於第1圖中區域E。Please refer to FIG. 1, which is a top view of a semiconductor device S according to a first embodiment of the present invention. The semiconductor element S is, for example, a three-terminal element. In the present embodiment, the semiconductor element S includes a source pad S70, a drain pad S80, a gate pad S90, and a plurality of semiconductor units 1. The semiconductor unit 1 is, for example, a field effect transistor, and in particular may be a high electron mobility transistor (HEMT). Further, when distinguished by an operation, the semiconductor unit 1 may be a normally-on transistor or a normally-off transistor. In the first embodiment, the semiconductor unit 1 includes a source 70 electrically connected to the source pad S70, a drain electrically connected to the drain pad S80, a gate 90 electrically connected to the gate pad S90, and a semiconductor stack. (Unlabeled), the material, location and design of the laminate can be adjusted according to actual needs. Further, the plurality of semiconductor units 1 included in the semiconductor element S are applicable to the semiconductor unit in other embodiments, for example, the semiconductor units 2, 3, 4, 5, 6 in the second to sixth embodiments can be used. The semiconductor unit 1 of the first embodiment is replaced. In order to clearly explain the detailed structure of the semiconductor units 2, 3, 4, 5, and 6 in the different embodiments, the semiconductor units 2, 3, 4, 5, and 6 are partially enlarged. For details, please refer to FIG. 2A, FIG. 3A, and FIG. 4A, 5A, and 6A. The position of the enlarged portion of the semiconductor cells 2, 3, 4, 5, 6 with respect to the semiconductor S is indicated in the region E in Fig. 1.
請參閱2A圖至第2B圖所示本發明第二實施例之半導體單元2。第2A圖為半導體單元2的局部上視示意圖，相當於區域E的位置；第2B圖為半導體單元2之剖面示意圖。於第二實施例中，半導體單元2為可以是常開型電晶體也可以是常關電晶體。半導體單元2包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、疊層260、源極70、汲極80、閘極90。其中，成核層20與緩衝層30依序位於基板10的上方；通道層40具有第一能隙，且位於緩衝層30上方；第一阻障層50位於通道層40上方，具有第二能隙，且第二能隙大於第一能隙；疊層260位於第一阻障層50上方，包含第一保護層261以及第一導電型化合物半導體層263；源極70位於第一阻障層50之一部份的上方；汲極80位於第一阻障層50之另一部分的上方，與源極70相互分隔；閘極90位於源極70與汲極80之間。Please refer to the semiconductor unit 2 of the second embodiment of the present invention shown in FIGS. 2A to 2B. 2A is a partial top view of the semiconductor unit 2, corresponding to the position of the region E; and FIG. 2B is a schematic cross-sectional view of the semiconductor unit 2. In the second embodiment, the semiconductor unit 2 may be a normally-on transistor or a normally-off transistor. The semiconductor unit 2 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a laminate 260, a source 70, a drain 80, and a gate 90. The nucleation layer 20 and the buffer layer 30 are sequentially located above the substrate 10; the channel layer 40 has a first energy gap and is located above the buffer layer 30; the first barrier layer 50 is located above the channel layer 40, and has a second energy. And a second energy gap is larger than the first energy gap; the layer 260 is located above the first barrier layer 50, and includes a first protective layer 261 and a first conductive type compound semiconductor layer 263; the source 70 is located at the first barrier layer Above one of the portions 50; the drain 80 is located above the other portion of the first barrier layer 50 and is separated from the source 70; the gate 90 is located between the source 70 and the drain 80.
於本實施例中，基板10例如為矽基板，厚度約為1000~1200um，上述的成核層20、緩衝層30、通道層40、第一阻障層50、疊層260以磊晶方式成長於基板10的(111)面上，並沿[0001]方向成長。磊晶方式例如為金屬有機物化學氣相磊晶法(metal-organic chemical vapor deposition, MOCVD)或分子束磊晶法(molecular-beam epitaxy, MBE)。基板10可為導電基板或者絕緣基板，且基板10的材料可以是矽(Si)、碳化矽(SiC)、氮化鎵(GaN)或藍寶石(sapphire)。在其他實施例中，還可以移除部分的基板10，以減少漏電路徑，達到減少漏電的效果。In this embodiment, the substrate 10 is, for example, a germanium substrate having a thickness of about 1000 to 1200 um, and the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the layer 260 are grown by epitaxy. On the (111) plane of the substrate 10, it grows in the [0001] direction. The epitaxial method is, for example, metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). The substrate 10 may be a conductive substrate or an insulating substrate, and the material of the substrate 10 may be germanium (Si), tantalum carbide (SiC), gallium nitride (GaN) or sapphire. In other embodiments, part of the substrate 10 can also be removed to reduce the leakage path to achieve the effect of reducing leakage.
成核層20位於基板10的上方，厚度約為數十奈米或數百奈米，用以減少基板10和第一阻障層40之間的晶格差異。成核層20例如是三五族材料，包括氮化鋁(AlN)、氮化鎵(GaN)、或氮化鋁鎵(AlGaN)等材料。緩衝層30位於成核層20的上方，厚度約為數微米或數十微米，其材料可為三五族材料，同樣是用以減少基板10和第一阻障層40之間的晶格差異，降低晶格缺陷。於本實施例中，緩衝層30可包括超晶格疊層(super lattice multilayer)，包括氮化鋁(AlN)、氮化鎵(GaN)、或氮化鋁鎵(AlGaN)等材料，其中超晶格疊層由兩種不同材料的疊層組成，亦可兩兩交互堆疊，其材料可為三五族材料，例如是由氮化鋁層(AlN)與氮化鎵鋁層(AlGaN)所構成，緩衝層30之材料也可由碳摻雜之氮化鎵層組成，而碳摻雜之氮化鎵層(GaN)其碳摻雜濃度為漸變或固定。The nucleation layer 20 is located above the substrate 10 and has a thickness of about several tens of nanometers or hundreds of nanometers to reduce the lattice difference between the substrate 10 and the first barrier layer 40. The nucleation layer 20 is, for example, a tri-five material including materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The buffer layer 30 is located above the nucleation layer 20 and has a thickness of about several micrometers or tens of micrometers. The material of the buffer layer 30 can be a tri-five material, which is also used to reduce the lattice difference between the substrate 10 and the first barrier layer 40. Reduce lattice defects. In this embodiment, the buffer layer 30 may include a super lattice multilayer including materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The lattice stack is composed of a laminate of two different materials, and may be stacked alternately in two or two. The material may be a group of three or five materials, for example, an aluminum nitride layer (AlN) and a gallium nitride aluminum layer (AlGaN). The material of the buffer layer 30 can also be composed of a carbon-doped gallium nitride layer, and the carbon-doped gallium nitride layer (GaN) has a carbon doping concentration which is gradual or fixed.
通道層40厚度範圍在50~300nm，形成於緩衝層30上，並具有一第一能隙。第一阻障層50厚度範圍在20~50nm，形成在通道層40上，並具有一第二能隙，第二能隙較第一能隙高，第一阻障層50之晶格常數比通道層40小。在本實施例中，通道層40包含氮化銦鎵(Inx Ga(1-x) N)，0≦x＜1，第一阻障層50包含氮化鋁銦鎵(Aly Inz Ga(1-z) N)，0＜y＜1，0≦z＜1。通道層40以及第一阻障層50自身形成自發性極化(spontaneous polarization)，且因其不同晶格常數形成壓電極化(piezoelectric polarization)，進而在通道層40及第一阻障層50間的異質接面產生二維電子氣(以虛線表示於圖中)。於本實施例中，通道層40及第一阻障層50可為本質半導體。The channel layer 40 has a thickness ranging from 50 to 300 nm and is formed on the buffer layer 30 and has a first energy gap. The first barrier layer 50 has a thickness ranging from 20 to 50 nm, is formed on the channel layer 40, and has a second energy gap. The second energy gap is higher than the first energy gap, and the lattice constant ratio of the first barrier layer 50 is lower. The channel layer 40 is small. In the present embodiment, the channel layer 40 comprises indium gallium nitride (In x Ga (1-x) N), 0 ≦ x < 1, and the first barrier layer 50 comprises aluminum indium gallium nitride (Al y In z Ga (1-z) N), 0 < y < 1, 0 ≦ z < 1. The channel layer 40 and the first barrier layer 50 themselves form spontaneous polarization, and piezoelectric polarization is formed due to different lattice constants thereof, and further between the channel layer 40 and the first barrier layer 50. The heterojunction produces a two-dimensional electron gas (shown in phantom in the figure). In this embodiment, the channel layer 40 and the first barrier layer 50 may be intrinsic semiconductors.
疊層260以磊晶成長的方式成長於第一阻障層50上方，包含一第一保護層261以及第一導電型化合物半導體層263。第一保護層261與第一導電型化合物半導體層263的形成順序不拘，可以如第2B圖所示，先形成第一保護層261之後再形成第一導電型化合物半導體層263，也可以如另一實施例之半導體單元2之剖面示意第2C圖所示的先形成第一導電型化合物半導體層263再形成第一保護層261。The laminate 260 is grown on the first barrier layer 50 in an epitaxial growth manner, and includes a first protective layer 261 and a first conductive type compound semiconductor layer 263. The first protective layer 261 and the first conductive type compound semiconductor layer 263 are formed in the same order, and as shown in FIG. 2B, the first conductive type compound semiconductor layer 263 may be formed after the first protective layer 261 is formed, or may be another The cross section of the semiconductor unit 2 of one embodiment is shown in FIG. 2C, and the first conductive type compound semiconductor layer 263 is formed first to form the first protective layer 261.
第一保護層261用來保護位於其下方的第一阻障層50之表面，以改善此表面的漏電流以及避免水氣滲入。一般而言，在製作第一保護層261時可以利用沉積等方式將第一保護層261成長於第一阻障層50之上，於本實施例中，為了避免汙染或損害半導體單元1，以及為了使第一保護層261的品質與緻密性較好，可以以磊晶的方式成長第一保護層261，第一保護層261例如是利用金屬有機物化學氣相磊晶法(metal-organic chemical vapor deposition, MOCVD)或分子束磊晶法(molecular-beam epitaxy, MBE)等方式磊晶成長的氮化矽層(insitu SiNx)，然而本發明並不以此為限，第一保護層261亦可以利用不同於上述的方式磊晶成長於第一阻障層50上方。第一保護層261也可以是氧化物，如二氧化矽。第一導電型化合物半導體層263材料包含p型或n型半導體材料，n型半導體材料包含n型雜質摻雜或未摻雜的本質半導體，可以是n型三五族化合物半導體，例如是n型氮化鋁鎵n-AlGaN。於本實施例中，第一導電型化合物半導體層263材料例如為p型的三五族半導體，如p型氮化鎵層(p-GaN)，其作用為降低閘極90下方的二維電子氣濃度進而提高導通電阻，使得本半導體單元2在閘極未施加偏壓的狀態下處於未導通的狀態(normally off)。換句話說，於第二實施例中，半導體單元2為常關型高電子遷移率電晶體(normally off transistor)。The first protective layer 261 serves to protect the surface of the first barrier layer 50 underneath to improve leakage current of the surface and to prevent moisture from penetrating. In general, the first protective layer 261 may be grown on the first barrier layer 50 by deposition or the like when the first protective layer 261 is formed. In this embodiment, in order to avoid contamination or damage to the semiconductor unit 1, In order to improve the quality and compactness of the first protective layer 261, the first protective layer 261 may be grown in an epitaxial manner. The first protective layer 261 is, for example, a metal-organic chemical vapor deposition method. Depositing, MOCVD) or molecular-beam epitaxy (MBE) or the like, the epitaxially grown tantalum nitride layer (insitu SiNx), but the invention is not limited thereto, and the first protective layer 261 can also Epitaxial growth is performed over the first barrier layer 50 in a manner different from that described above. The first protective layer 261 may also be an oxide such as hafnium oxide. The first conductive type compound semiconductor layer 263 material comprises a p-type or n-type semiconductor material, and the n-type semiconductor material comprises an n-type impurity doped or undoped intrinsic semiconductor, which may be an n-type tri-five compound semiconductor, for example, an n-type Aluminum gallium nitride n-AlGaN. In the present embodiment, the material of the first conductive type compound semiconductor layer 263 is, for example, a p-type tri-five semiconductor such as a p-type gallium nitride layer (p-GaN), which functions to reduce two-dimensional electrons under the gate 90. The gas concentration further increases the on-resistance such that the semiconductor unit 2 is normally off in a state where the gate is not biased. In other words, in the second embodiment, the semiconductor unit 2 is a normally off type high electron turnover transistor.
在形成疊層260之後，於第一阻障層50上方分別形成源極70、汲極80與閘極90以作為與外部電性連接的端點。其中源極70、汲極80分別置於第一阻障層50的兩側，而閘極90則位於疊層260的上方並位於源極70與汲極80之間。換句話說疊層260位於閘極90的下方且介於源極70與汲極80之間。在本實施例中，可以藉由選擇適當的源極與汲極的材料，以及/或者藉由製程(如，熱退火)以使汲極80與源極70和第一阻障層50之間形成歐姆接觸。類似地，也可藉由選擇適當的閘極的材料，使得閘極90與第一導電型化合物半導體層263則形成蕭特基接觸。源極70、汲極80的材料可以選自鈦(Ti)、鋁(Al)，閘極90的材料可以選自鎳(Ni)、金(Au)、鎢(W)、氮化鈦(TiN)。After the stack 260 is formed, the source 70, the drain 80, and the gate 90 are respectively formed over the first barrier layer 50 as an end point electrically connected to the outside. The source 70 and the drain 80 are respectively disposed on both sides of the first barrier layer 50, and the gate 90 is located above the stack 260 and between the source 70 and the drain 80. In other words, the stack 260 is located below the gate 90 and between the source 70 and the drain 80. In this embodiment, the drain electrode 80 and the source 70 and the first barrier layer 50 can be separated by selecting an appropriate source and drain material and/or by a process such as thermal annealing. An ohmic contact is formed. Similarly, the gate 90 and the first conductive type compound semiconductor layer 263 may form a Schottky contact by selecting an appropriate material of the gate. The material of the source 70 and the drain 80 may be selected from titanium (Ti) and aluminum (Al), and the material of the gate 90 may be selected from nickel (Ni), gold (Au), tungsten (W), and titanium nitride (TiN). ).
於本實施例中，在形成源極70、汲極80與閘極90之前，還可以形成如另一實施例之半導體單元2之剖面示意第2D圖所示之介電層100於疊層260與部分之第一阻障層50的上表面之上。部分之介電層100位於閘極90的下方，並位於閘極90與疊層260之間，能進一步降低表面漏電流，更可提高閘極90操作偏壓範圍，提升元件可靠度。介電層100可以是氧化物或者氮化物，例如是氧化矽或氧化鋁等氧化物，也可以是氮化矽或氮化鎵等氮化物。然而本發明不以此為限，於其他實施例中亦可不形成介電層100。此外，在形成上述的源極70、汲極80與閘極90之後，還可以進一步形成第二保護層(未繪示)以覆蓋介電層100、疊層260、源極70、汲極80與閘極90之表面，以防止通道層40的電性受到影響。而在本實施例中，第二保護層可以是氧化物或者氮化物，如氧化矽或氧化鋁等氧化物，也可以是氮化矽或氮化鎵等氮化物。接著再蝕刻第二保護層，以露出部分源極70、汲極80與閘極90與外界電性連接，源極70、汲極80與閘極90可以有一部份表面未被第二保護層所覆蓋，以增加與外界電性連接的方便性。In the present embodiment, before the source 70, the drain 80 and the gate 90 are formed, the dielectric layer 100 shown in FIG. 2D of the semiconductor unit 2 of another embodiment may be formed on the laminate 260. And a portion of the upper surface of the first barrier layer 50. A portion of the dielectric layer 100 is located below the gate 90 and between the gate 90 and the stack 260, which can further reduce surface leakage current, improve the operating bias range of the gate 90, and improve component reliability. The dielectric layer 100 may be an oxide or a nitride, for example, an oxide such as ruthenium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride. However, the present invention is not limited thereto, and the dielectric layer 100 may not be formed in other embodiments. In addition, after forming the source 70, the drain 80 and the gate 90 described above, a second protective layer (not shown) may be further formed to cover the dielectric layer 100, the laminate 260, the source 70, and the drain 80. The surface of the gate 90 is used to prevent the electrical properties of the channel layer 40 from being affected. In this embodiment, the second protective layer may be an oxide or a nitride, such as an oxide such as yttrium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride. Then, the second protective layer is further etched to expose a portion of the source 70, the drain 80 and the gate 90 to be electrically connected to the outside. The source 70, the drain 80 and the gate 90 may have a portion of the surface not being protected by the second protective layer. Covered to increase the convenience of electrical connection with the outside world.
第二實施例的半導體單元2，包含由第一保護層261及第一導電型化合物半導體層263所組成之疊層260。第一保護層261可以是磊晶成長的氮化矽層，藉此可以達到改善表面漏電流以及保護磊晶表面之功效，而第一導電型化合物半導體層263例如為p型氮化鎵，可以達到降低二維電子氣濃度，進而達到提高閘極90下方之導通電阻的功效。The semiconductor unit 2 of the second embodiment includes a laminate 260 composed of a first protective layer 261 and a first conductive type compound semiconductor layer 263. The first protective layer 261 may be an epitaxially grown tantalum nitride layer, thereby improving the surface leakage current and protecting the epitaxial surface, and the first conductive type compound semiconductor layer 263 is, for example, p-type gallium nitride. The effect of reducing the two-dimensional electron gas concentration to improve the on-resistance under the gate 90 is achieved.
請參閱第3A圖與第3B圖，第3A圖為本發明第三實施例之半導體單元3的局部上視示意圖；第3B圖為本發明第三實施例之半導體單元3之剖面示意圖。如前所述，半導體元件S除了包含多個半導體單元1或2，也可以包含多個第3A至第3B圖所示之半導體單元3。半導體單元3包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、疊層360、源極70、汲極80和閘極90。3A and 3B, FIG. 3A is a partial top view of the semiconductor unit 3 according to the third embodiment of the present invention; FIG. 3B is a schematic cross-sectional view of the semiconductor unit 3 according to the third embodiment of the present invention. As described above, the semiconductor element S may include a plurality of semiconductor units 3 shown in FIGS. 3A to 3B in addition to the plurality of semiconductor units 1 or 2. The semiconductor unit 3 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a second barrier layer 52, a laminate 360, a source 70, a drain 80, and a gate 90.
第三實施例之半導體單元3例如為場效電晶體，可以是常開型高電子遷移率電晶體(normally on transistor)，在未施加偏壓於閘極的狀況下為導通。於第三實施例之製造方法中，首先將成核層20、緩衝層30、通道層40、第一阻障層50依序形成在基板10之上。在形成第一阻障層50之後，形成第二阻障層52於其上。接著，再形成疊層360於第二阻障層52之上，其中疊層360包含第一保護層361以及第一導電型化合物半導體層363，而第一保護層361可以為磊晶成長的氮化矽層。The semiconductor unit 3 of the third embodiment is, for example, a field effect transistor, and may be a normally-on high-electron mobility transistor, which is turned on without applying a bias voltage to the gate. In the manufacturing method of the third embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, and the first barrier layer 50 are first formed on the substrate 10 in this order. After the first barrier layer 50 is formed, a second barrier layer 52 is formed thereon. Next, a laminate 360 is formed over the second barrier layer 52, wherein the laminate 360 includes a first protective layer 361 and a first conductive type compound semiconductor layer 363, and the first protective layer 361 may be epitaxially grown nitrogen.矽 layer.
於形成疊層360之後，利用黃光顯影製程定義圖形，接著蝕刻部分之疊層360以裸露部分之第二阻障層52，之後在裸露之第二阻障層52上形成源極70、汲極80，然後進行熱退火使得源極70、汲極80與第二阻障層52形成歐姆接觸。於形成源極70、汲極80之後，利用黃光顯影製程定義圖形，接著蝕刻部分之疊層360以裸露部分之第二阻障層52，然後在裸露之第二阻障層52上形成閘極90，其中閘極90與第二阻障層52為蕭特基接觸。After forming the layer 360, the pattern is defined by a yellow light developing process, and then the portion of the layer 360 is etched to expose a portion of the second barrier layer 52, and then the source 70 is formed on the exposed second barrier layer 52. The pole 80 is then thermally annealed such that the source 70 and the drain 80 form an ohmic contact with the second barrier layer 52. After the source 70 and the drain 80 are formed, the pattern is defined by a yellow light developing process, and then the portion of the layer 360 is etched to expose the second barrier layer 52, and then the gate is formed on the exposed second barrier layer 52. The pole 90, wherein the gate 90 and the second barrier layer 52 are in Schottky contact.
於本實施例中，第二阻障層52位於疊層360與第一阻障層50之間，可作為蝕刻停止層。此外，本實施例是利用乾式蝕刻的方式來蝕刻疊層360。當利用蝕刻氣體蝕刻部分之疊層360時，由於第二阻障層52的被蝕刻速率低於第一阻障層50的被蝕刻速率，因此蝕刻的深度會大致停止於第二阻障層52的上表面。第二阻障層52的材料例如為三五族半導體層，可以是氮化鋁，或是高鋁組成的氮化鋁鎵層，其鋁組成大於第一阻障層50 之鋁組成，且第二阻障層52的能隙大於通道層40之第一能隙與第一阻障層50之第二能隙。疊層360位於源極70與閘極90之間以及位於汲極80與閘極90之間，而疊層360之第一導電型化合物半導體層363位於第一保護層361與第二阻障層52之間，並且第一導電型化合物半導體層363與閘極90不相連接，兩者間存在有一間隙。於本實施例中，為了提高源極70與閘極90或是汲極80與閘極90下方的二維電子氣濃度，第一導電型化合物半導體層363可以是n型三五族化合物半導體層，例如為n型的氮化鋁鎵，然而本申請不以上述為限。在其他實施例中，為了改變自發性極化與壓電極化效果，通道層40以及第一阻障層50可以是具有摻雜的半導體層，而摻雜的原料可為矽烷(SiH4 )，用以將矽摻雜其中。基板10、成核層20、緩衝層30、通道層40、第一阻障層50、源極70、汲極80和閘極90的材料、厚度範圍、功用請參閱第二實施例之描述。In the present embodiment, the second barrier layer 52 is located between the laminate 360 and the first barrier layer 50 and serves as an etch stop layer. In addition, this embodiment etches the laminate 360 by dry etching. When the portion of the stack 360 is etched using the etching gas, since the etch rate of the second barrier layer 52 is lower than the etch rate of the first barrier layer 50, the depth of the etch may substantially stop at the second barrier layer 52. Upper surface. The material of the second barrier layer 52 is, for example, a three-five-semiconductor layer, which may be aluminum nitride or an aluminum-aluminum gallium layer composed of high aluminum, the aluminum composition of which is larger than the aluminum composition of the first barrier layer 50, and The energy gap of the second barrier layer 52 is greater than the first energy gap of the channel layer 40 and the second energy gap of the first barrier layer 50. The laminate 360 is located between the source 70 and the gate 90 and between the gate 80 and the gate 90, and the first conductive type compound semiconductor layer 363 of the laminate 360 is located at the first protective layer 361 and the second barrier layer Between 52, and the first conductive type compound semiconductor layer 363 and the gate 90 are not connected, there is a gap therebetween. In the present embodiment, in order to increase the two-dimensional electron gas concentration under the source 70 and the gate 90 or the drain 80 and the gate 90, the first conductive type compound semiconductor layer 363 may be an n-type tri-five compound semiconductor layer. For example, it is an n-type aluminum gallium nitride, but the present application is not limited to the above. In other embodiments, in order to change the spontaneous polarization and the piezoelectric polarization effect, the channel layer 40 and the first barrier layer 50 may be a doped semiconductor layer, and the doped material may be decane (SiH 4 ). Used to dope the ruthenium. The material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80 and the gate 90 are described in the second embodiment.
請參閱第4A圖至第4B圖，第4A圖為本發明第四實施例之半導體單元的局部上視示意圖。第4B圖為本發明第四實施例之半導體單元之剖面示意圖。半導體元件S除了可由多個半導體單元1或2或3電連接而成，也可以由多個第4A至第4B圖所示之半導體單元4電連接而成。半導體單元4包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、疊層460、源極70、汲極80和閘極90。Please refer to FIG. 4A to FIG. 4B. FIG. 4A is a partial top view of the semiconductor unit according to the fourth embodiment of the present invention. 4B is a schematic cross-sectional view showing a semiconductor unit according to a fourth embodiment of the present invention. The semiconductor element S may be electrically connected by a plurality of semiconductor units 1 or 2 or 3, or may be electrically connected by a plurality of semiconductor units 4 shown in FIGS. 4A to 4B. The semiconductor unit 4 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a second barrier layer 52, a laminate 460, a source 70, a drain 80, and a gate 90.
第4A至第4B圖所示之半導體單元4類似於第3A圖至第3B圖的半導體單元3，皆是屬於常開型高電子遷移率電晶體，其差異在於疊層460之第一保護層461(如氮化矽層)以及第一導電型化合物半導體層463的形成順序。於第三實施例中，先形成第一導電型化合物半導體層363，然後才形成第一保護層361 (如氮化矽層)。於第四實施例中之製造方法中，首先將成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52依序形成在基板10之上，接著則是先形成第一保護層461於第二阻障層52上，然後才形成第一導電型化合物半導體層463於第一保護層461上。於形成疊層460之後，利用黃光顯影製程定義圖形，接著蝕刻部分之疊層460以裸露部分之第二阻障層52，之後在裸露之第二阻障層52上形成源極70、汲極80，然後進行熱退火使得源極70、汲極80與第二阻障層52形成歐姆接觸。於形成源極70、汲極80之後，再形成閘極90。The semiconductor unit 4 shown in FIGS. 4A to 4B is similar to the semiconductor unit 3 of FIGS. 3A to 3B, and is a normally open type high electron mobility transistor, which differs in the first protective layer of the laminate 460. The order of formation of 461 (such as a tantalum nitride layer) and the first conductive type compound semiconductor layer 463. In the third embodiment, the first conductive type compound semiconductor layer 363 is formed first, and then the first protective layer 361 (such as a tantalum nitride layer) is formed. In the manufacturing method of the fourth embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the second barrier layer 52 are sequentially formed on the substrate 10, and then The first protective layer 461 is formed on the second barrier layer 52, and then the first conductive type compound semiconductor layer 463 is formed on the first protective layer 461. After forming the layer 460, the pattern is defined by a yellow light developing process, and then the portion of the layer 460 is etched to expose a portion of the second barrier layer 52, and then the source 70 is formed on the exposed second barrier layer 52. The pole 80 is then thermally annealed such that the source 70 and the drain 80 form an ohmic contact with the second barrier layer 52. After the source 70 and the drain 80 are formed, the gate 90 is formed again.
在形成第四實施例的閘極90時，會先以利用黃光顯影製程定義圖形，接著蝕刻部分之第一導電型化合物半導體層463與第一保護層461以裸露部分之第二阻障層52，接著於裸露之第二阻障層52上形成閘極90，其中閘極90會連接第一保護層461。於本實施例中，由於蝕刻氣體對於第一保護層461以及第一導電型化合物半導體層463的蝕刻率並不相同，因此較多的第一導電型化合物半導體層463被蝕刻，而裸露出部分第一保護層461。此外，由於第一保護層461連接閘極90，所以第一保護層461和閘極90、源極70、汲極80大致上是覆蓋了整個第二阻障層52的上表面，如此一來可以有效防止水氣進入亦可避免表面漏電流。再者，如圖所示，第一保護層461連接閘極90，對閘極90而言，氮化矽層461提供了側向支撐力，可以避免閘極90坍塌。基板10、成核層20、緩衝層30、通道層40、第一阻障層50、源極70、汲極80和閘極90的材料、厚度範圍以及功用請參閱第二實施例之相關描述。第二阻障層52、疊層460的材料選用請參閱第三實施例中對於第二阻障層52以及疊層360的描述。When the gate electrode 90 of the fourth embodiment is formed, a pattern is defined by using a yellow light developing process, and then a portion of the first conductive type compound semiconductor layer 463 and the first protective layer 461 are exposed to expose a second barrier layer. 52. A gate 90 is then formed on the exposed second barrier layer 52, wherein the gate 90 is connected to the first protective layer 461. In the present embodiment, since the etching rate of the etching gas to the first protective layer 461 and the first conductive type compound semiconductor layer 463 is not the same, more of the first conductive type compound semiconductor layer 463 is etched, and the bare portion is exposed. The first protective layer 461. In addition, since the first protective layer 461 is connected to the gate 90, the first protective layer 461 and the gate 90, the source 70, and the drain 80 substantially cover the upper surface of the entire second barrier layer 52, thus It can effectively prevent moisture from entering and avoid surface leakage current. Moreover, as shown, the first protective layer 461 is connected to the gate 90. For the gate 90, the tantalum nitride layer 461 provides a lateral supporting force to prevent the gate 90 from collapsing. For the material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80 and the gate 90, please refer to the related description of the second embodiment. . For the material selection of the second barrier layer 52 and the laminate 460, please refer to the description of the second barrier layer 52 and the laminate 360 in the third embodiment.
請參閱第5A圖至第5B圖，第5A圖為本發明第五實施例之半導體單元的局部上視示意圖。第5B圖為本發明第五實施例之半導體單元之剖面示意圖。半導體元件S除了可由多個半導體單元1至4電連接而成，也可以由多個第5A至第5B圖所示之半導體單元5電連接而成。於本實施例中，半導體單元5，包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、疊層560、源極70、汲極80和閘極90’。Referring to FIGS. 5A to 5B, FIG. 5A is a partial top plan view showing a semiconductor unit according to a fifth embodiment of the present invention. Fig. 5B is a schematic cross-sectional view showing a semiconductor unit according to a fifth embodiment of the present invention. The semiconductor element S may be electrically connected by a plurality of semiconductor units 1 to 4, or may be electrically connected by a plurality of semiconductor units 5 shown in FIGS. 5A to 5B. In the present embodiment, the semiconductor unit 5 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a stack 560, a source 70, a drain 80, and a gate 90'. .
第5A至第5B圖所示之半導體單元5類似於第3A圖至第3B圖的半導體單元3，同樣屬於常開型高電子遷移率電晶體，兩者的主要差異在於閘極的形狀。於第五實施例中之製造方法中，首先將成核層20、緩衝層30、通道層40、第一阻障層50、疊層560依序形成在基板10之上，於形成疊層560之後，利用黃光顯影製程定義圖形，接著蝕刻部分之疊層560以裸露部分之第二阻障層52，之後在裸露之第二阻障層52上形成源極70、汲極80，然後進行熱退火使得源極70、汲極80與第二阻障層52形成歐姆接觸。於形成源極70、汲極80之後，再形成閘極90’。The semiconductor unit 5 shown in FIGS. 5A to 5B is similar to the semiconductor unit 3 of FIGS. 3A to 3B, and is also a normally-open type high electron mobility transistor, and the main difference between the two is the shape of the gate. In the manufacturing method of the fifth embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the layer stack 560 are sequentially formed on the substrate 10 to form the layer stack 560. Thereafter, a pattern is defined by a yellow light developing process, and then a portion of the stack 560 is etched to expose a portion of the second barrier layer 52, and then a source 70, a drain 80 is formed on the exposed second barrier layer 52, and then The thermal annealing causes the source 70 and the drain 80 to form an ohmic contact with the second barrier layer 52. After the source 70 and the drain 80 are formed, the gate 90' is formed again.
在形成第五實施例的閘極90’時，會先以利用黃光顯影製程定義圖形，接著蝕刻部分之第一保護層561及第一導電型化合物半導體層563以裸露部分之第一阻障層50，接著將閘極90’製作於裸露之第一阻障層50上。When the gate electrode 90' of the fifth embodiment is formed, the pattern is defined by the yellow light developing process, and then the first protective layer 561 and the first conductive type compound semiconductor layer 563 are etched to expose the first barrier of the exposed portion. Layer 50, followed by gate 90' is formed on exposed first barrier layer 50.
於本實施例中，利用乾式蝕刻的方式來對第一保護層561及第一導電型化合物半導體層563的進行蝕刻。一般而言，乾式蝕刻的蝕刻氣體對不同的物質會對應不同的蝕刻速率。於本實施例中，由於蝕刻氣體對第一保護層561的被蝕刻速率會低於對第一導電型化合物半導體層563的被蝕刻速率，因此較多的第一導電型化合物半導體層563被蝕刻。換句話說，第一保護層561因蝕刻而形成的缺口直徑d1會小於第一導電型化合物半導體層563因蝕刻而形成的缺口直徑d2。當形成閘極90’時，部分用於製作閘極90’的材料會通過第一保護層561的缺口與第一導電型化合物半導體層563的缺口而沉積在被裸露的第一阻障層50上，而另一部分用於製作閘極90’的材料則直接沉積於第一保護層561的缺口附近，進而形成了T型閘極90’。於本實施例中，疊層560之第一保護層561 (如氮化矽層)位於第一導電型化合物半體層563之上方且連接T形閘極90’，對閘極90’而言，第一保護層561提供了側向支撐力，可以避免閘極90’坍塌。此外，由於第一保護層561會連接閘極90’，因此第一阻障層50的上表面大致上是被第一保護層561與閘極90’、源極70、汲極80所覆蓋，如此一來可以有效防止水氣進入亦可避免表面漏電流。基板10、成核層20、緩衝層30、通道層40、第一阻障層50、源極70、汲極80和閘極90’的材料、厚度範圍以及功用請參閱第二實施例之相關描述。疊層560的材料選用請參閱第三實施例中對於疊層360的描述。In the present embodiment, the first protective layer 561 and the first conductive type compound semiconductor layer 563 are etched by dry etching. In general, dry etched etch gases will correspond to different etch rates for different materials. In the present embodiment, since the etching rate of the etching gas to the first protective layer 561 is lower than the etching rate of the first conductive type compound semiconductor layer 563, more of the first conductive type compound semiconductor layer 563 is etched. . In other words, the notch diameter d1 formed by the etching of the first protective layer 561 is smaller than the notch diameter d2 formed by the etching of the first conductive type compound semiconductor layer 563. When the gate 90' is formed, a portion of the material for forming the gate 90' is deposited on the exposed first barrier layer 50 through the gap of the first protective layer 561 and the gap of the first conductive type compound semiconductor layer 563. The other portion of the material used to form the gate 90' is deposited directly adjacent the gap of the first protective layer 561, thereby forming a T-type gate 90'. In the present embodiment, the first protective layer 561 of the stack 560 (such as a tantalum nitride layer) is located above the first conductive type compound half layer 563 and connected to the T-shaped gate 90'. For the gate 90', The first protective layer 561 provides lateral support to avoid collapse of the gate 90'. In addition, since the first protective layer 561 is connected to the gate 90 ′, the upper surface of the first barrier layer 50 is substantially covered by the first protective layer 561 and the gate 90 ′, the source 70 , and the drain 80 . In this way, water vapor can be effectively prevented from entering and surface leakage current can be avoided. The material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80 and the gate 90' are referred to in the second embodiment. description. For the material selection of the laminate 560, please refer to the description of the laminate 360 in the third embodiment.
第三實施例至第五實施例的半導體單元3、4、5，分別包含由第一保護層361、461、561及第一導電型化合物半導體層363、463、563所組成之疊層360、460、560。第一保護層361、461、561可以是磊晶成長的氮化矽層，藉此可以達到改善表面漏電流以及保護磊晶表面之功效。第一導電型化合物半導體層363、463、563例如為n型的氮化鋁鎵可以達到提高二維電子氣濃度，進而達到降低導通電阻的功效。The semiconductor units 3, 4, and 5 of the third embodiment to the fifth embodiment respectively include a stack 360 composed of the first protective layers 361, 461, and 561 and the first conductive type compound semiconductor layers 363, 463, and 563. 460, 560. The first protective layer 361, 461, 561 may be an epitaxially grown tantalum nitride layer, whereby the effect of improving surface leakage current and protecting the epitaxial surface can be achieved. The first conductive type compound semiconductor layers 363, 463, and 563 are, for example, n-type aluminum gallium nitride, which can improve the two-dimensional electron gas concentration and further reduce the on-resistance.
請參閱第6A圖和第6B圖，第6A圖為本發明第六實施例之半導體單元的局部上視示意圖。第6B圖為本發明第六實施例之半導體單元之剖面示意圖。半導體元件S除了可由多個半導體單元1至5電連接而成，也可以由多個第6A至第6B圖所示之半導體單元6電連接而成。半導體單元6，包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、第三阻障層54、疊層660、源極70、汲極80和閘極90。Referring to FIGS. 6A and 6B, FIG. 6A is a partial top plan view of a semiconductor unit according to a sixth embodiment of the present invention. 6B is a cross-sectional view showing a semiconductor unit according to a sixth embodiment of the present invention. The semiconductor element S may be electrically connected by a plurality of semiconductor units 1 to 5, or may be electrically connected by a plurality of semiconductor units 6 shown in FIGS. 6A to 6B. The semiconductor unit 6 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a first barrier layer 50, a second barrier layer 52, a third barrier layer 54, a stack 660, a source 70, Bungee 80 and gate 90.
第6A至第6B圖所示之半導體單元6類似於第2A圖至第2D圖的半導體單元2，同樣屬於常關型高電子遷移率電晶體(normally off transistor)，兩者的主要差異在於第六實施例更包含第三阻障層54。在第六實施例中之製造方法中，首先將成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52依序形成於基板10上，接著形成第三阻障層54於第二阻障層52之上，然後形成疊層660於第三阻障層54之上。第三阻障層54的材料或組成可與第一阻障層50相同或不同，於本實施例中第三阻障層54與第一阻障層50的材料皆為氮化鎵鋁，但第三阻障層54之鋁組成高於第一阻障層50之鋁組成。The semiconductor unit 6 shown in FIGS. 6A to 6B is similar to the semiconductor unit 2 of FIGS. 2A to 2D, and is also a normally off type high electron mobility transistor. The main difference between the two is that The sixth embodiment further includes a third barrier layer 54. In the manufacturing method of the sixth embodiment, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the second barrier layer 52 are sequentially formed on the substrate 10, and then the first layer is formed. A triple barrier layer 54 is over the second barrier layer 52 and then a stack 660 is formed over the third barrier layer 54. The material or composition of the third barrier layer 54 may be the same as or different from that of the first barrier layer 50. In the embodiment, the materials of the third barrier layer 54 and the first barrier layer 50 are all aluminum gallium nitride, but The aluminum composition of the third barrier layer 54 is higher than the aluminum composition of the first barrier layer 50.
疊層660包括第一保護層661及第一導電型化合物半導體層663，第一保護層661與第一導電型化合物半導體層663以依序或反序的方式置於第三阻障層54的上方，如此一來第三阻障層54位於疊層660與第二阻障層52之間，且第二阻障層52可作為後續蝕刻製程中的停止層。於形成疊層660之後，進行蝕刻步驟，首先利用黃光微影製程定義圖形，接著蝕刻去除部分之疊層660以裸露部分之第三阻障層54，然後形成源極70與汲極80於被裸露之第三阻障層54上，並經過熱退火步驟使得源極70與汲極80和第三阻障層54形成歐姆接觸。接著，同樣利用黃光微影製程定義圖形，然後蝕刻先去除部分之疊層660與部分之第三阻障層54，並透過使用適當的蝕刻氣體與蝕刻條件(如溫度、蝕刻持續時間等)，以使蝕刻的深度會大致停止於第二阻障層52的上表面，並且裸露部分之第二阻障層52，閘極9 0則形成於裸露之第二阻障層52的上表面。如圖所示，源極70和汲極80分開設置且位於第二阻障層52的兩端，閘極90則位於源極70和汲極80之間。於本實施例中，部分的疊層660位於閘極90與源極70/汲極80之間。然而本發明不以上述為限。基板10、成核層20、緩衝層30、通道層40、第一阻障層50、源極70、汲極80、閘極90’、疊層660的材料、厚度範圍以及功用請參閱第二實施例之相關描述，第二阻障層52的材料選用請參閱第三實施例中的相關描述。The laminate 660 includes a first protective layer 661 and a first conductive type compound semiconductor layer 663. The first protective layer 661 and the first conductive type compound semiconductor layer 663 are disposed in the third barrier layer 54 in a sequential or reverse order. Above, the third barrier layer 54 is located between the stack 660 and the second barrier layer 52, and the second barrier layer 52 can serve as a stop layer in a subsequent etching process. After forming the stack 660, an etching step is performed, first defining a pattern using a yellow lithography process, then etching away portions of the stack 660 to expose portions of the third barrier layer 54, and then forming the source 70 and the drain 80 to be exposed The third barrier layer 54 is subjected to a thermal annealing step such that the source 70 is in ohmic contact with the drain 80 and the third barrier layer 54. Next, the yellow light lithography process is also used to define the pattern, and then the portion of the layer 660 and the portion of the third barrier layer 54 are etched first, and the appropriate etching gas and etching conditions (such as temperature, etching duration, etc.) are used. The etching depth is substantially stopped at the upper surface of the second barrier layer 52, and the exposed portion of the second barrier layer 52, the gate 90 is formed on the upper surface of the exposed second barrier layer 52. As shown, the source 70 and the drain 80 are disposed separately and are located at both ends of the second barrier layer 52, and the gate 90 is located between the source 70 and the drain 80. In this embodiment, a portion of the stack 660 is between the gate 90 and the source 70/drain 80. However, the invention is not limited to the above. The material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the source 70, the drain 80, the gate 90', and the laminate 660 are referred to the second. For a description of the material of the second barrier layer 52, please refer to the related description in the third embodiment.
第六實施例的半導體單元6，包含由第一保護層661及第一導電型化合物半導體層663所組成之疊層660。第一保護層661可以是磊晶成長的氮化矽層，藉此可以達到改善表面漏電流以及保護磊晶表面之功效。第一導電型化合物半導體層663例如為p型氮化鎵可以達到降低二維電子氣濃度，進而達到提高閘極90下方之導通電阻的功效。The semiconductor unit 6 of the sixth embodiment includes a laminate 660 composed of a first protective layer 661 and a first conductive type compound semiconductor layer 663. The first protective layer 661 may be an epitaxially grown tantalum nitride layer, whereby the effect of improving surface leakage current and protecting the epitaxial surface can be achieved. The first conductive type compound semiconductor layer 663 is, for example, p-type gallium nitride, which can reduce the two-dimensional electron gas concentration and further improve the on-resistance under the gate 90.
於本申請中，半導體元件S除了可為第1圖中的三端點的元件，如功率元件，亦可為兩端點的元件，如蕭特基二極體元件。當半導體元件S為兩端點元件時，則會包含陽極墊、陰極墊以及多個分別與陽極墊和陰極墊電連接的兩端點半導體單元。請參閱第7A圖和第7B圖，第7A圖為本發明第七實施例之半導體單元7的局部上視示意圖。第7B圖為本發明第七實施例之半導體單元7剖面示意圖。於本實施例中，半導體單元7為兩端點元件，如蕭特基二極體，半導體單元7包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、疊層760、陽極A和陰極C。In the present application, the semiconductor element S may be an element of a three-terminal end in FIG. 1, such as a power element, and may also be an element at both ends, such as a Schottky diode element. When the semiconductor element S is a two-point element, it includes an anode pad, a cathode pad, and a plurality of terminal semiconductor units electrically connected to the anode pad and the cathode pad, respectively. Referring to FIGS. 7A and 7B, FIG. 7A is a partial top view of the semiconductor unit 7 of the seventh embodiment of the present invention. Fig. 7B is a cross-sectional view showing the semiconductor unit 7 of the seventh embodiment of the present invention. In this embodiment, the semiconductor unit 7 is a two-point element, such as a Schottky diode. The semiconductor unit 7 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, and a first barrier layer 50. Second barrier layer 52, laminate 760, anode A and cathode C.
製作半導體單元7的方式與先前製作半導體單元3的方式類似，首先提供基板10，接著依序於基板10上形成成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52，然後形成疊層760於第二阻障層52之上，其中第二阻障層52可作為後續蝕刻製程中的停止層。疊層760包括第一保護層761(如，磊晶成長的氮化矽層)及第一導電型化合物半導體層763，第一導電型化合物半導體層763與第一保護層761依序置於第二阻障層52的上方，且於形成疊層760之後，進行蝕刻步驟。進行蝕刻時，首先利用黃光微影製程定義圖形，接著蝕刻去除部分之疊層760以裸露部分之第二阻障層52，蝕刻的深度會大致停止於第二阻障層52的上表面。然後形成陽極A與陰極C於被裸露之第二阻障層52上，並使疊層760與陽極A之間存在一間距，接著透過適當的材料選擇以及/或者經過熱退火等製程步驟使得陽極A與陰極C和第二阻障層52形成歐姆接觸，然而本發明不以上述為限。基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、疊層760的材料、厚度範圍以及功用請參閱第二實施例及第三實施例之相關描述。The manner of fabricating the semiconductor unit 7 is similar to the manner of fabricating the semiconductor unit 3 first. First, the substrate 10 is provided, and then the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the first layer are sequentially formed on the substrate 10. The second barrier layer 52 is then formed over the second barrier layer 52, wherein the second barrier layer 52 serves as a stop layer in the subsequent etching process. The laminate 760 includes a first protective layer 761 (eg, an epitaxially grown tantalum nitride layer) and a first conductive type compound semiconductor layer 763, and the first conductive type compound semiconductor layer 763 and the first protective layer 761 are sequentially placed Above the second barrier layer 52, and after forming the stack 760, an etching step is performed. When etching is performed, the pattern is first defined by a yellow lithography process, and then the portion of the laminate 760 is etched away to expose the second barrier layer 52, and the etching depth is substantially stopped at the upper surface of the second barrier layer 52. The anode A and the cathode C are then formed on the exposed second barrier layer 52 with a spacing between the laminate 760 and the anode A, followed by appropriate material selection and/or thermal annealing and other processing steps to cause the anode A forms an ohmic contact with the cathode C and the second barrier layer 52, but the invention is not limited thereto. For the material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the second barrier layer 52, and the laminate 760, please refer to the second embodiment and the third implementation. A description of the example.
請參閱第8A圖和第8B圖，第8A圖為本發明第八實施例之半導體單元的局部上視示意圖。第8B圖為本發明第八實施例之半導體單元剖面示意圖。 於本實施例中，半導體單元8為兩端點元件，如蕭特基二極體，半導體單元8包括基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、疊層860、陽極A和陰極C。Referring to FIGS. 8A and 8B, FIG. 8A is a partial top plan view of a semiconductor unit according to an eighth embodiment of the present invention. 8B is a cross-sectional view showing a semiconductor unit according to an eighth embodiment of the present invention. In this embodiment, the semiconductor unit 8 is a two-point element, such as a Schottky diode, and the semiconductor unit 8 includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, and a first barrier layer 50. Second barrier layer 52, stack 860, anode A and cathode C.
製作半導體單元8的方式與先前製作半導體單元7的方式類似，首先提供基板10，接著依序於基板10上形成成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52，然後形成疊層860於第二阻障層52之上。兩者的差異在於半導體單元8是先形成第一保護層861然後才形成第一導電型化合物半導體層863，其中第一保護層861可以是磊晶成長的氮化矽層(insitu silicon nitride) ，而第一導電型化合物半導體層863可以是n型的氮化鋁鎵。於形成疊層860之後，利用黃光微影製程定義圖形，接著蝕刻去除部分之疊層860以裸露部分之第二阻障層52，然後形成陽極A與陰極C於被裸露之第二阻障層52上，並使疊層860與陽極A之間存在一間距，接著透過適當的材料選擇以及/或者經過熱退火等製程步驟使得陽極A與陰極C和第二阻障層52形成歐姆接觸，然而本發明不以上述為限。於本實施例中，第一保護層861大致上覆蓋未被陰極C與陽極A覆蓋的第二阻障層52的表面。基板10、成核層20、緩衝層30、通道層40、第一阻障層50、第二阻障層52、疊層760的材料、厚度範圍以及功用請參閱第二實施例及第三實施例之相關描述。The method of fabricating the semiconductor unit 8 is similar to the manner of fabricating the semiconductor unit 7 in the prior art. First, the substrate 10 is provided, and then the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, and the first layer are sequentially formed on the substrate 10. The second barrier layer 52 is then formed over the second barrier layer 52. The difference between the two is that the semiconductor unit 8 first forms the first protective layer 861 and then forms the first conductive type compound semiconductor layer 863, wherein the first protective layer 861 may be an epitaxially grown insitu silicon nitride. The first conductive type compound semiconductor layer 863 may be an n-type aluminum gallium nitride. After forming the stack 860, the pattern is defined by a yellow lithography process, followed by etching away portions of the stack 860 to expose portions of the second barrier layer 52, and then forming the anode A and the cathode C to the exposed second barrier layer 52. And a gap exists between the layer 860 and the anode A, and then the anode A and the cathode C and the second barrier layer 52 are in ohmic contact by a suitable material selection and/or a thermal annealing process. The invention is not limited to the above. In the present embodiment, the first protective layer 861 substantially covers the surface of the second barrier layer 52 that is not covered by the cathode C and the anode A. For the material, thickness range and function of the substrate 10, the nucleation layer 20, the buffer layer 30, the channel layer 40, the first barrier layer 50, the second barrier layer 52, and the laminate 760, please refer to the second embodiment and the third implementation. A description of the example.
第七實施例與第八實施例的半導體單元7、8，分別包含由第一保護層761、861及第一導電型化合物半導體層763、863所組成之疊層766、860。第一保護層761、861可以是磊晶成長的氮化矽層，藉此可以達到改善表面漏電流以及保護磊晶表面之功效。The semiconductor units 7, 8 of the seventh embodiment and the eighth embodiment respectively include the stacks 766, 860 composed of the first protective layers 761, 861 and the first conductive type compound semiconductor layers 763, 863. The first protective layers 761, 861 may be epitaxially grown tantalum nitride layers, whereby the effect of improving surface leakage current and protecting the epitaxial surface can be achieved.
上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟於此項技藝之人士在不違背本發明之技術原理及精神的情況下，對上述實施例所進行之修改及變化，皆可能或理應被涵蓋在本發明內。The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments of the present invention may be or are intended to be included in the present invention without departing from the spirit and scope of the invention.
A‧‧‧陽極A‧‧‧Anode
C‧‧‧陰極C‧‧‧ cathode
E‧‧‧區域E‧‧‧ area
FF’‧‧‧剖線FF’‧‧‧ cut line
S‧‧‧半導體元件S‧‧‧Semiconductor components
1、2、3、4、5、6、7、8‧‧‧半導體單元1, 2, 3, 4, 5, 6, 7, 8‧‧‧ semiconductor units
10‧‧‧基板10‧‧‧Substrate
20‧‧‧成核層20‧‧‧Nuclear layer
30‧‧‧緩衝層30‧‧‧buffer layer
40‧‧‧通道層40‧‧‧Channel layer
50‧‧‧第一阻障層50‧‧‧First barrier layer
52‧‧‧第二阻障層52‧‧‧second barrier layer
54‧‧‧第三阻障層54‧‧‧ third barrier layer
260、360、460、560、660、760、860 ‧‧‧疊層260, 360, 460, 560, 660, 760, 860 ‧ ‧ stacks
261、361、461、561、661、761、861‧‧‧第一保護層261, 361, 461, 561, 661, 761, 861‧‧‧ first protective layer
263、363、463、563、663、763、863‧‧‧第一導電型化合物半導體層263, 363, 463, 563, 663, 763, 863 ‧ ‧ first conductive compound semiconductor layer
70‧‧‧源極70‧‧‧ source
80‧‧‧汲極80‧‧‧汲polar
90、90’‧‧‧閘極90, 90’‧‧‧ gate
100‧‧‧介電層100‧‧‧ dielectric layer
圖式用以促進對本發明之理解，為本說明書之一部分。圖式之實施例配合實施方式之說明以解釋本發明之原理。The drawings are intended to facilitate an understanding of the invention and are part of the specification. The embodiments of the drawings are described in conjunction with the embodiments to explain the principles of the invention.
第1圖為本發明第一實施例之半導體元件的上視圖。Fig. 1 is a top view of a semiconductor element according to a first embodiment of the present invention.
第2A圖為本發明第二實施例之半導體單元的局部上視示意圖。2A is a partial top plan view of a semiconductor unit in accordance with a second embodiment of the present invention.
第2B圖為本發明第二實施例之半導體單元之剖面示意圖。2B is a schematic cross-sectional view showing a semiconductor unit according to a second embodiment of the present invention.
第2C圖為本發明第二實施例之半導體單元之另一剖面示意圖。2C is another schematic cross-sectional view of the semiconductor unit of the second embodiment of the present invention.
第2D圖為本發明第二實施例之半導體單元之另一剖面示意圖。2D is another schematic cross-sectional view of the semiconductor unit of the second embodiment of the present invention.
第3A圖為本發明第三實施例之半導體單元的局部上視示意圖。3A is a partial top plan view of a semiconductor unit according to a third embodiment of the present invention.
第3B圖為本發明第三實施例之半導體單元之剖面示意圖。3B is a schematic cross-sectional view showing a semiconductor unit according to a third embodiment of the present invention.
第4A圖為本發明第四實施例之半導體單元的局部上視示意圖。4A is a partial top plan view showing a semiconductor unit according to a fourth embodiment of the present invention.
第4B圖為本發明第四實施例之半導體單元之剖面示意圖。4B is a schematic cross-sectional view showing a semiconductor unit according to a fourth embodiment of the present invention.
第5A圖為本發明第五實施例之半導體單元的局部上視示意圖。Fig. 5A is a partial top plan view showing a semiconductor unit according to a fifth embodiment of the present invention.
第5B圖為本發明第五實施例之半導體單元之剖面示意圖。Fig. 5B is a schematic cross-sectional view showing a semiconductor unit according to a fifth embodiment of the present invention.
第6A圖為本發明第六實施例之半導體單元的局部上視示意圖。Fig. 6A is a partial top plan view showing a semiconductor unit according to a sixth embodiment of the present invention.
第6B圖為本發明第六實施例之半導體單元之剖面示意圖。6B is a cross-sectional view showing a semiconductor unit according to a sixth embodiment of the present invention.
第7A圖為本發明第七實施例之半導體單元的局部上視示意圖。Fig. 7A is a partial top plan view showing a semiconductor unit according to a seventh embodiment of the present invention.
第7B圖為本發明第七實施例之半導體單元剖面示意圖。Fig. 7B is a schematic cross-sectional view showing a semiconductor unit according to a seventh embodiment of the present invention.
第8A圖為本發明第八實施例之半導體單元的局部上視示意圖。Fig. 8A is a partial top plan view showing a semiconductor unit according to an eighth embodiment of the present invention.
第8B圖為本發明第八實施例之半導體單元剖面示意圖。8B is a cross-sectional view showing a semiconductor unit according to an eighth embodiment of the present invention.
無no
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