CN111710650A - GaN device based on double-channel gate and preparation method thereof - Google Patents
GaN device based on double-channel gate and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/452—Ohmic electrodes on AIII-BV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention provides a GaN device based on a double-channel gate and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, forming an epitaxial structure, forming a source electrode and a drain electrode, etching part of a barrier layer and an epitaxial cap layer of the epitaxial structure to obtain a groove structure and a protruding structure which are alternately arranged, and forming a gate dielectric layer and a gate electrode layer. According to the invention, the first device and the second device which are alternately arranged are formed on the GaN channel layer, and can be an MOS device structure and an HEMT device structure which are alternately arranged, so that the linearity of the whole GaN device can be improved based on the MOS device structure and the HEMT device structure. The gate oxide adopts BeO, the polarization effect and the heat dissipation are enhanced simultaneously, the TixAly layer is adopted as the material of the source electrode and the drain electrode, and the direct contact ohmic contact is realized through the Ti-Al alloy film without gold, so that the high-conductivity 2DEG is favorably maintained, the lower contact resistance and the flatter contact interface are favorably obtained, and the compatibility with the Si process is realized.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to a GaN device based on a double-channel gate and a preparation method thereof.
Background
The transconductance (gm) of a conventional transistor varies with gate Voltage (VGS) as a bell-shaped curve, mainly due to several physical reasons including: (i) self-heating effect; (ii) increasing the dynamic source access resistance; (iii) optical phonon emission; and (iv) a contact barrier. The gm nonlinearity of a device with a vertically stacked multiple quantum well channel is low, i.e., linearity is good, by design, but is not common in practical applications. The adoption of innovative materials, including gallium nitride (GaN) with a nitrogen (N) -polarized surface and the secondary epitaxial growth of a source electrode can promote the linear quality factor of the device, and output the ratio of the third-order intermodulation intercept point (OIP 3) to the direct current power supply (PDC), i.e., OIP3/PDC, which still has room for further improvement of linearity.
At present, the problem of transistor linearity and the bottleneck are usually solved by circuit linearization technique. Linearity is typically improved by compensating circuit elements (components other than GaN devices) in the circuit design, rather than by optimizing the performance of the GaN device itself. For example, using Differential Superposition (DS) and cancellation can extend transistor linearity at low frequencies, but is difficult to implement at high frequencies and cannot handle high power signals.
Therefore, how to provide a GaN device based on dual-channel gate and a method for fabricating the same are needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a dual-channel gate-based GaN device and a method for fabricating the same, which are used to solve the problems of the prior art, such as difficulty in effectively improving the linearity of the GaN device.
In order to achieve the above objects and other related objects, the present invention provides a method for fabricating a dual-channel gate-based GaN device, comprising the steps of:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, a barrier layer positioned on the GaN channel layer and an epitaxial cap layer positioned on the surface of the barrier layer;
preparing a source electrode and a drain electrode on the epitaxial structure;
etching part of the epitaxial cap layer and the barrier layer between the source electrode and the drain electrode to form a plurality of groove structures which are arranged at intervals along the width direction of the gate, namely in the direction perpendicular to the connecting line direction of the source electrode and the source electrode, wherein the GaN channel layer is exposed out of the groove structures, and a plurality of protruding structures are formed between the groove structures;
and forming a gate dielectric layer and a gate electrode layer on the surfaces of the groove structure and the protrusion structure around the groove structure.
Optionally, the barrier layer comprises an AlN layer, and the source and drain electrodes comprise TixAly layers.
Optionally, the epitaxial cap layer comprises a GaN cap layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.
Optionally, after forming the source electrode and the drain electrode and before forming the groove structure, the method further comprises: and forming a device mesa device isolation structure in the epitaxial structure.
Optionally, the step of forming the groove structure and the protrusion structure includes:
removing part of the epitaxial cap layer based on a first process to form a plurality of initial grooves; and
and removing the barrier layer corresponding to the initial groove based on a second process to obtain the groove structure and form the protruding structure, wherein the second process is different from the first process.
Optionally, the first process includes performing an oxygen plasma oxidation process and then a wet removal process on the basis of the mask layer; the second process includes a selective etching process using wet chemical reagents including at least one of KOH reagents and AZ400K reagents.
Optionally, before forming the gate dielectric layer, a step of forming a continuous native oxide layer on the inner wall of the groove structure and the surface of the protrusion structure is further included; forming the gate dielectric layer by adopting an atomic layer deposition process; the method also comprises the step of forming a passivation layer on the surface of the device after the gate electrode layer is formed.
Optionally, the natural oxide layer and the gate dielectric layer are completed based on the same atomic layer deposition process chamber, the natural oxide layer is formed based on ozone, and an oxygen source of the gate dielectric layer includes ozone.
Optionally, the gate dielectric layer includes a BeO material layer, a deposition temperature of the BeO material layer is between 100 ℃ and 300 ℃, and a thickness of the BeO material layer is between 5nm and 50 nm.
Optionally, the width of the groove structure is between 1 and 10 times the width of the protrusion structure along the arrangement direction of the groove structure and the protrusion structure.
The invention also provides a GaN device based on the double-channel gate, wherein the GaN device is preferably prepared by adopting the preparation method provided by the invention, and of course, other methods can also be adopted for preparation, and the GaN device based on the double-channel gate comprises the following steps:
a semiconductor substrate;
the epitaxial structure is formed on the semiconductor substrate and comprises a GaN channel layer, a barrier layer positioned on the GaN channel layer and an epitaxial cap layer positioned on the surface of the barrier layer;
a source electrode and a drain electrode formed on the epitaxial structure;
the GaN channel layer is formed on the substrate, and the GaN channel layer is formed on the substrate;
the gate dielectric layer is positioned on the groove structure and the surface of the protruding structure around the groove structure.
Optionally, the barrier layer comprises an AlN layer, and the source and drain electrodes comprise TixAly layers; the epitaxial cap layer comprises a GaN cap layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.
Optionally, the dual-channel gate-based GaN device further comprises a device isolation structure formed in the epitaxial structure.
Optionally, a natural oxide layer is further formed between the groove structure and the surface of the protruding structure around the groove structure and the gate dielectric layer, and oxygen sources of the natural oxide layer and the gate dielectric layer both include ozone.
Optionally, the gate dielectric layer includes a BeO material layer, and a thickness of the BeO material layer is between 5nm and 50 nm.
Optionally, the width of the groove structure is between 1 and 10 times the width of the protrusion structure along the arrangement direction of the groove structure and the protrusion structure.
As described above, according to the dual-channel gate-based GaN device and the method for manufacturing the same of the present invention, the first device and the second device alternately arranged are formed on the GaN channel layer, and may be formed as an MOS device structure and an HEMT device structure alternately arranged, so that the linearity of the entire GaN device can be improved based on the first device and the second device. In addition, the TixAly layer is adopted as the material of the source electrode and the drain electrode, and the direct contact ohmic contact is realized through the Ti-Al alloy film without gold, so that the high-conductivity 2DEG can be kept, the lower contact resistance and the flatter contact interface can be obtained, and meanwhile, the non-gold ohmic contact electrode can be compatible with the silicon process.
Drawings
Fig. 1 is a flow chart illustrating a process for fabricating a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 2 shows a schematic view of providing a semiconductor substrate in the fabrication of a dual-channel gate-based GaN device in accordance with an example of the present invention.
Fig. 3 is a schematic diagram illustrating the formation of an epitaxial structure in the fabrication of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating the formation of source and drain electrodes in the fabrication of a dual-channel gate-based GaN device according to an example of the present invention.
Fig. 5 is a top view illustrating the formation of source and drain electrodes in the fabrication of a dual-channel gate-based GaN device in accordance with an exemplary embodiment of the present invention.
Fig. 6 is a schematic view illustrating the formation of a photoresist layer in the fabrication of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 7 shows a schematic representation of the formation of a patterned photoresist layer in the fabrication of a dual-channel gate-based GaN device in accordance with an example of the present invention.
Fig. 8 shows a schematic representation of plasma oxidation in the fabrication of a dual-channel gate-based GaN device in accordance with an example of the present invention.
Fig. 9 is a schematic diagram illustrating the formation of an initial groove in the fabrication of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 10 is a schematic view illustrating the formation of a groove structure and a protrusion structure in the fabrication of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 11 is a schematic view illustrating the formation of a native oxide layer based on plasma treatment in the fabrication of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 12 is a schematic diagram illustrating the formation of gate dielectric layers and gate electrode layers in the fabrication of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention.
Fig. 13 is a top view of a dual-channel gate-based GaN device according to an exemplary embodiment of the present invention after formation of a gate electrode layer.
Fig. 14 shows a graph of transconductance versus gate-source voltage for a conventional planar HEMT device with a conventional MOS device and a dual-channel gate-based GaN device of the present invention.
Description of the element reference numerals
101-semiconductor substrate, 102-buffer layer, 103-GaN channel layer, 104-barrier layer, 105-epitaxial cap layer, 106-source electrode, 107-drain electrode, 108-photoresist layer, 109-patterned photoresist layer, 110-oxide layer, 111-initial groove, 112-groove structure, 113-protrusion structure, 114-gate dielectric layer, 115-gate layer, 116-first device, 117-second device, 118-natural oxide layer, and S1-S5.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for manufacturing a GaN device based on a dual-channel gate, comprising the following steps:
s1: providing a semiconductor substrate;
s2: forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, a barrier layer positioned on the GaN channel layer and an epitaxial cap layer positioned on the surface of the barrier layer;
s3: preparing a source electrode and a drain electrode on the epitaxial structure;
s4: etching part of the epitaxial cap layer and the barrier layer between the source electrode and the drain electrode to form a plurality of groove structures which are arranged at intervals in a direction vertical to a connecting line of the source electrode and the source electrode, wherein the GaN channel layer is exposed from the groove structures, and a plurality of protruding structures are formed between the groove structures;
s5: and forming a gate dielectric layer and a gate electrode layer on the surfaces of the groove structure and the protrusion structure around the groove structure.
The method for fabricating the dual-channel gate-based GaN device according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the fabrication sequence of the dual-channel gate-based GaN device protected by the present invention, and those skilled in the art can change the sequence according to the actual process steps, and fig. 1 shows only one exemplary dual-channel gate-based GaN device fabrication step, and those skilled in the art can change the design according to the conventional choice in the art.
First, as shown in S1 in fig. 1 and fig. 2, step S1 is performed to provide the semiconductor substrate 101. The semiconductor substrate 101 includes, but is not limited to, a SiC substrate, a Si substrate, and other substrates commonly used in the art. The semiconductor substrate 101 may be a single-layer material layer or a stacked structure of multiple material layers.
Next, as shown in S2 of fig. 1 and fig. 3, step S2 is performed to form an epitaxial structure on the semiconductor substrate 101, where the epitaxial structure includes a GaN channel layer 103, a barrier layer 104 on the GaN channel layer 103, and an epitaxial cap layer 105 on a surface of the barrier layer 104. In an example, a buffer layer 102 for alleviating lattice mismatch is further formed between the semiconductor substrate 101 and the GaN channel layer 103, and the buffer layer 102 includes, but is not limited to, an AlGaN layer. In an example, the epitaxial cap layer 105 includes, but is not limited to, a GaN layer, the thickness of the epitaxial cap layer 105 is between 1-3nm, such as 1.5nm, 2nm, 2.5nm, and the barrier layer 104 can be protected from contamination, oxidation, and degradation. In another alternative example, a nucleation layer (not shown) for nucleation of epitaxial growth is further formed between the semiconductor substrate 101 and the GaN channel layer 103. In addition, each material layer in the epitaxial structure can be grown by an epitaxial process.
As an example, the barrier layer 104 comprises an AlN layer, and the thickness of the barrier layer 104 is between 2-5nm, such as 3nm, 3.5nm, 4 nm. Therefore, two-dimensional electron gas can be polarized in the GaN channel under the condition of thin thickness.
Next, as shown in S3 of fig. 1 and fig. 4-5, step S3 is performed to form a source electrode 106 and a drain electrode 107 on the epitaxial structure, so as to form source and drain ohmic contacts.
As an example, the source electrode 106 and the drain electrode 107 include a TixAly layer. That is, in this example, the electrode material of the source electrode 106 and the drain electrode 107 is selected to be a Ti-Al alloy thin film, where Ti is already in a Ti-Al alloy form, instead of a conventional Ti/Al multilayer thin film, in this example, the Ti-Al alloy thin film is directly in contact with the barrier layer/the epitaxial cap layer (e.g., AlN/GaN), so that even in the initial annealing stage, due to the presence of Al in Ti, the Al diffusion from the barrier layer (AlN), i.e., the Al diffusion from the barrier layer to the GaN cap layer to the source/drain electrode metal region, is suppressed, thereby maintaining the high conductivity of 2 DEG. For the AlN barrier layer, in the traditional process, Ti/Al metal is subjected to high-temperature annealing at 900 ℃ of 800-. The main principle is that N, Al in the barrier layer can diffuse with Ti metal to form TiN after high-temperature annealing, the shape is rough and uneven, N atoms in the barrier layer are reduced, N-type AlN rich in nitrogen (N) holes is formed (namely, N-type doped AlN, namely N atoms in AlN are reduced, N-type doping rich in nitrogen defects is formed), and ohmic contact is formed between the N-type AlN and the TiN. However, Al in AlN also diffuses toward the metal, which reduces the Al content in AlN, thereby weakening the polarization ability of the GaN channel and affecting the 2DEG density.
In addition, the source electrode 106 and the drain electrode 107 are selected to be TixAly layers, so that the work functions of Ti and Al are small, ohmic contact with Al (ga) N/GaN is easily formed, and the adhesion of the alloy and the resistivity of a device are improved. In an alternative example, the TixAly layer is selected to be Ti5Al1The Ti component is enough to form TiN and ohmic contact with N in AlN and form good ohmic contact with GaN material, and is beneficial to ensuring that the electrode material does not influence 2DEG, namely, the Ti component contains a small amount of Al component. While the non-gold ohmic contact electrode may be compatible with silicon processes.
In one example, the step of forming the source electrode 106 and the drain electrode 107 includes: firstly, immersing a sample into HCl and DI (deionized water) aqueous solution (such as HCl: DI is 1: 2) for a certain time (such as 1 minute) to remove the surface oxide of the epitaxial material; and then, through photoetching, electrode metal material deposition, stripping and annealing, and source and drain ohmic contacts are formed. After removing the surface oxide, forming a source electrode opening and a drain electrode opening through a photolithography process, wherein the epitaxial cap layer 105 is exposed from the source electrode opening and the drain electrode opening, and performing the cleaning process in the step, in combination with the HCl and DI cleaning, two times of cleaning are beneficial to ensuring that no organic matter or oxide exists on the surface of the material before metal deposition, thereby ensuring good metal-semiconductor contact; the sample is then immersed in dilute hydrochloric acid for a period of time (e.g., 1 minute) to remove the native oxide layer, although in another example, the above-described HCl and DI rinse steps may not be performed, and only the step may be performedHydrochloric acid cleaning after the formation of the photolithographic mask in the step; depositing electrode material, such as Ti, on the surface of the photoresist in and around the source and drain electrode openings by magnetron sputtering5Al1a/TiN stack deposition with a thickness set at 60/60nm, TiN to further reduce metal resistance; then carrying out a stripping process; after stripping, the samples were subjected to Rapid Thermal Annealing (RTA) in ambient gas (97% Ar and 3% H2) at a temperature of 600-700 ℃ for 70-80s, such as 60 s.
Next, as shown in S4 of fig. 1 and fig. 6-10, step S4 is performed to etch a portion of the epitaxial cap layer 105 and the barrier layer 104 between the source electrode 106 and the drain electrode 107, so as to form a plurality of groove structures 112 arranged at intervals in a direction perpendicular to a connection line (i.e., a gate width direction) between the source electrode 106 and the source electrode 107, the groove structures 112 expose the GaN channel layer 103, and a plurality of protruding structures 113 are formed between the groove structures 112, as shown in fig. 10. Specifically, a portion of the epitaxial cap layer 105 and the barrier layer 104 stacked above and below is removed to form the groove structure 112, and the remaining unremoved epitaxial cap layer 105 and the barrier layer 104 stacked above and below constitute a protrusion structure 113. For example, the source electrode 106 and the drain electrode 107 are bar-shaped structures arranged in parallel, such as rectangular structures, and extend along the length direction thereof, where the connecting direction of the two is the gate width direction, i.e. the connecting line perpendicular to the length extending direction, that is, the groove structures 112 and the protrusion structures 113 are alternately arranged along the direction in which the lengths of the source electrode and the drain electrode extend.
As an example, the epitaxial cap layer 105 and the barrier layer 104 are removed in two steps to form the recessed structure 112 and the protruding structure 113, and the specific steps may include:
first, as shown in fig. 6-9, a number of initial grooves 111 are formed by removing portions of the epitaxial cap layer based on a first process. In a specific example, a photoresist layer 108 may be formed on the structure obtained in the previous step, as shown in fig. 6, and then a plurality of etching openings are formed through a photolithography process to obtain a patterned photoresist layer 109, where the etching openings correspond to positions where the trench structure 112 needs to be formed, as shown in fig. 7, where fig. 6 is a cross-sectional view along a line direction of the source electrode and the drain electrode, and fig. 7 is a cross-sectional view along a gate width direction, that is, a direction perpendicular to the line direction of the source electrode and the drain electrode. Next, as shown in fig. 8, O2 plasma oxidation is performed on the basis of the patterned photoresist layer 109 (the mask layer), and the epitaxial cap layer 105 (e.g., GaN cap layer) exposed at the corresponding position is oxidized to form an oxide layer 110. The O2 plasma treatment may be performed in an RIE (reactive ion etching) tool. Alternatively, the RF power may be 150-300W (e.g., 200W) at a pressure of 10-30mT (e.g., 20 mT) for 1-5min, e.g., 2 min. In an example, an AlN barrier layer is disposed below the epitaxial cap layer 105 (e.g., a GaN cap layer), and is oxidized by using O plasma, so that oxygen (O) has a too small diffusion coefficient in AlN to effectively prevent oxygen ion diffusion, thereby not affecting the AlN barrier layer and the GaN channel and facilitating the implementation of the lossless etching of the epitaxial cap layer. Next, as shown in fig. 9, a wet etching process is used to remove the oxidized epitaxial cap layer 105, i.e., remove the oxide layer 110, in an example, the oxidized GaN cap layer is removed by a BOE wet method, so as to implement a lossless etching.
Then, as shown in fig. 10, the barrier layer 104 corresponding to the initial groove 111 is removed based on a second process to obtain the groove structure 112 and form the protrusion structure 113. In one example, the second process includes a selective etching process using a wet chemistry including at least one of KOH reagent and AZ400K reagent, and can etch AlN without damage, completely etching the AlN layer, stopping the etching on the GaN channel layer, and without damage to the material surface.
As an example, after forming the source electrode 106 and the drain electrode 107 and before forming the groove structure 112, the method further includes the steps of: device mesa device isolation structures (not shown) are formed in the epitaxial structure. In one example, using chlorine-based plasma (BCl 3/Cl 2/Ar) dry etching, the bottoms of the device isolation structures are lower than a two-dimensional electron gas formed in the GaN channel layer, and device regions are defined between adjacent device isolation structures to form electrical isolation.
Finally, as shown in S5 of fig. 1 and fig. 11 to 13, step S5 is performed to form a gate dielectric layer 114 and a gate electrode layer 115 on the surface of the groove structure 112 and the protrusion structure 113 around the groove structure, so as to form a bent channel-type gate dielectric layer 114 and a bent channel-type gate electrode layer 115, form a first device 116, such as a MOS device, corresponding to the position of the groove structure 112, form a second device 117, such as a HEMT device, corresponding to the position of the protrusion structure 113, and arrange the first device 116 and the second device 117 alternately in the extending direction of the two parallel source electrodes and drain electrodes. In which the second device 117 (HEMT device structure) and the first device 116 (MOS structure) are implemented alternately, the overall device linearity can be improved. Specifically, since the HEMT device is a depletion-mode normally-on device, leading-on, the resistance of the multiple channels in the micro-channel HEMT is higher than the channel resistance of conventional planar devices due to the narrower effective channel width. For a given drain bias, the voltage drop applied to the microchannel is higher than the channel in the case of a conventional planar HEMT. Since the voltage of each microchannel is high, the current density in the microchannel increases. There is a higher electron density injected into the microchannel from the source side than in the case of the planar HEMT. With the increase of VGS, the threshold voltage of the GaN MOS device is reached, so that the part of the device is turned on, the transconductance of the HEMT device is supplemented by the transconductance of the GaN MOS device, and the gm of the whole device is flattened. As shown in fig. 14, which is a graph showing the change of transconductance gm of the conventional planar HEMT device, the conventional planar MOS device, and the device of the present invention in which HEMTs and MOS are alternately arranged (the two devices have equal widths) with gate-source voltage Vgs in an example, it can be seen that the transconductance flatness of the structure of the device of the present invention is significantly improved, and the linearity of the device is improved.
As an example, along the arrangement direction of the groove structures 112 and the protrusion structures 113, the protrusion structuresIs smaller than the width of the groove structure, in a preferred example, the width of the groove structure (e.g., subsequently forming a MOS device) is 1-10 times the width of the protruding structure, such as 2, 3, 5, 8, etc. Wherein, the mobility of a general GaN HEMT device is considered to be 2000cm2Vs, mobility of GaN MOSFET device is 200cm2Therefore, designing the above size ratio is beneficial to make the MOS gm peak value as close to HEMT gm as possible, so as to perform effective gm compensation to improve linearity (gm value is proportional to the product of mobility mu and gate width W, i.e. gm-.
By way of example, the gate dielectric layer 114 includes a layer of BeO material having a deposition temperature between 100 ℃ and 300 ℃ and a thickness between 5nm and 50 nm. In this example, a layer of BeO material is used as the gate oxide, and in one example, the deposition conditions are in the temperature range of 100 deg.C-300 deg.C, which may be, for example, 150 deg.C, 180 deg.C, 200 deg.C. In one example, Be (CH) is utilized3)2And O3As a gas source. In one example, the BeO material layer is deposited to a thickness of 5-50nm, e.g., selected from 10nm, 15nm, 20nm, 25nm, 30nm, 40nm, 45nm, etc.
The BeO obtained based on the mode is used as the gate oxide, and has the advantages of higher thermal conductivity (330W/Km), band gap energy (-11 eV) and dielectric constant (-7) compared with the conventional gate oxide layer such as SiO 2. In addition, diamond is the only material on earth with thermal conductivity exceeding BeO as an insulating material, so BeO can enhance the heat dissipation capability of GaN devices. BeO is used as gate oxide, and heat can be dissipated on the surface of the GaN and the grid in time through the BeO material. Based on the good heat dissipation characteristic of the BeO, heat sinks (such as diamond and graphene films) do not need to be additionally prepared on the surfaces of the devices, and the process is greatly simplified. Further, the BeO material layer is used as a gate oxide layer, so that additional polarization function can be provided in AlN/GaN HEMTs. BeO films exhibit strong spontaneous and piezoelectric polarization due to their non-centrosymmetric crystal structure. The formation of the 2DEG channel in AlN/GaN HEMTs is caused by polarization-induced heterointerface charges. Therefore, when the BeO thin film is combined with the AlN/GaN heterojunction, the polarization field in the thin film can change the polarization of HEMTs, so that the 2DEG carrier density is improved, and the device performance is enhanced. Meanwhile, the structure of BeO/AlN/GaN and BeO/GaN enhances the polarization effect in the corresponding GaN channel, improves the carrier concentration and is beneficial to the electrical property optimization of the device. In addition, BeO gate oxide preparation is carried out through ozone O3, the quality of the BeO single crystal film can be ensured, and the conventional H is avoided2O is used as a gas source to cause the film to be non-crystallized, thereby effectively inhibiting the leakage current of the grid electrode and being integrated with the formed natural oxide layer.
As an example, before forming the gate dielectric layer, a step of forming a continuous natural oxide layer 118 on the inner wall of the groove structure 112 and the surface of the protrusion structure 113 is further included, in an example, as shown in fig. 11, after removing the photoresist layer of the previous step, oxidizing the entire material surface by using O2 plasma to oxidize the surface of the epitaxial cap layer 105 (such as a GaN cap layer) and the GaN channel layer 103, so as to form the natural oxide layer and a GaO thin layer, where the natural oxide layer may be an oxide thin layer with a thickness of 0.5nm to 1nm, such as 0.6nm and 0.8nm, the natural oxide layer may be used as a transition medium, the GaN-GaO has a good interface quality due to natural oxidation, and the BeO/GaO oxide interlayer interface of the subsequent gate dielectric layer is also good, and the total interface defect is low. In one example, the gate dielectric layer 104 is formed using an atomic layer deposition process (ALD) after the native oxide layer is formed, further resulting in good interface contact.
In another example, ozone is used to form the native oxide layer. In a further alternative example, in the ALD chamber, ozone O3 is introduced to perform surface oxidation on the material to form a GaO thin layer, and then an atomic layer deposition process is used to form a gate dielectric layer (e.g., BeO deposition is performed again) in the same ALD chamber, preferably, the gate dielectric layer is formed by using O3 as an oxygen source. The surface oxidation treatment is carried out in the same ALD cavity, then the gate oxide deposition is directly carried out without leaving the cavity, the sample is prevented from being exposed to air, meanwhile, O3 is used as a gas source for depositing the gate oxide, the deposited gate oxide can be more compact, the defects in a gate medium are reduced, and the quality is better. And O3 used as an oxygen source in the gate dielectric layer and O3 used for forming the natural oxidation layer are the same gas, and the two-step process can be regarded as the same procedure, so that an oxygen-rich environment is formed in the ALD chamber, and the forming quality of the material film layer is improved. Meanwhile, the oxygen source is O3, H2O in the traditional process is replaced by the oxygen source, and the ALD chemical method using O3 as the oxygen source gas reduces hydroxyl impurities (OH-) and residual hydrogen (H), so that the oxygen layer body and interface traps are reduced.
By way of example, the gate layer 105 comprises a stacked Ni/Au metal stack, and a 100-500nm thick electrode layer may be deposited by electron beam lithography and lift-off processes. In an example, the length w2 of the gate layer 105 along the connection line direction of the source electrode and the drain electrode (gate metal electrode length, i.e. gate length) is equal to the size w1 of the first device and the second device in the direction (length of the concave-convex topographic region), which may be considered as the size of the groove structure 112 in the direction, and optionally, the sizes w1 and w2 are equal to each other, which is beneficial to ensuring sufficient input carriers and improving linearity of the gate control multi-finger gate. In another example, w2 is smaller than w1, i.e., the gate metal is deposited in the upper region of the etched gate fingers, such as w2 between 1/4-1/2 of w1, such as 1/3, which is advantageous to ensure lithographic alignment. In addition, in an example, a first spacing s1 is provided between the groove structure 112 and the protrusion structure 113 and the source electrode 106, and a second spacing s2 is provided between the groove structure 112 and the protrusion structure 113 and the drain electrode 107, in an example, s1 is smaller than or equal to s2, so that the second spacing s2 is increased to facilitate increasing the withstand voltage of the device.
In addition, after the gate electrode layer 105 is formed, a step of forming a passivation layer (not shown in the figure) on the surface of the device is also included, wherein the passivation layer includes but is not limited to a SiN layer, the thickness of the passivation layer is between 200nm and 1 μm, and the passivation layer can be formed by adopting a PECVD process to realize isolation among different functional structures so as to complete preparation of the device.
In addition, as shown in fig. 12 and 13, referring to fig. 1 to 11 and 14, the present invention provides a GaN device based on a double channel gate, wherein the GaN device is preferably manufactured by the method for manufacturing a GaN device of the present invention, but may be manufactured by other methods. The structure, the positional relationship and the related characteristics of the dual-channel gate-based GaN device in this embodiment may refer to the description of the method for manufacturing the dual-channel gate-based GaN device in this embodiment, and are not described herein again. The dual-channel gate-based GaN device includes:
a semiconductor substrate 101;
an epitaxial structure formed on the semiconductor substrate 101, the epitaxial structure comprising a GaN channel layer 103, a barrier layer 104 on the GaN channel layer, and an epitaxial cap layer 105 on a surface of the barrier layer;
a source electrode 106 and a drain electrode 107 formed on the epitaxial structure;
the GaN channel layer 103 is formed by alternately arranging groove structures 112 and protrusion structures 113, wherein the groove structures 112 are arranged at intervals along a direction perpendicular to a connecting line of the source electrode 106 and the source electrode 107 and expose the GaN channel layer 103, and the protrusion structures 113 are formed between the groove structures 112;
a gate dielectric layer 114 and a gate electrode layer 115 on the gate dielectric layer 114, wherein the gate dielectric layer 114 is located on the groove structure 112 and the surface of the protrusion structure 113 around the groove structure 112.
As an example, the barrier layer 104 includes an AlN layer, and the source electrode 106 and the drain electrode 107 include TixAly layers.
Illustratively, the epitaxial cap layer 105 comprises a GaN cap layer, and the thickness of the epitaxial cap layer 105 is between 1-3 nm.
As an example, the dual-channel gate-based GaN device further includes a device isolation structure (not shown in the drawings) formed in the epitaxial structure.
As an example, a natural oxide layer is further formed between the surface of the groove 112 and the protruding structure 113 around the groove structure and the gate dielectric layer 114, and oxygen sources of the natural oxide layer and the gate dielectric layer both include ozone.
By way of example, the gate dielectric layer comprises a BeO material layer, and the thickness of the BeO material layer is between 5nm and 50 nm.
As an example, the width of the groove structure is between 1 and 10 times the width of the protrusion structure along the arrangement direction of the groove structure and the protrusion structure.
In summary, according to the dual-channel-gate-based GaN device and the method for manufacturing the same of the present invention, the first device and the second device alternately arranged are formed on the GaN channel layer, and may be formed as an MOS device structure and an HEMT device structure alternately arranged, so that the linearity of the entire GaN device can be improved based on the first device and the second device. In addition, the TixAly layer is adopted as the material of the source electrode and the drain electrode, and the direct contact ohmic contact is realized through the Ti-Al alloy film without gold, so that the high-conductivity 2DEG can be kept, and the low contact resistance and the flat contact interface can be obtained. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A preparation method of a GaN device based on a double-channel gate is characterized by comprising the following steps:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, a barrier layer positioned on the GaN channel layer and an epitaxial cap layer positioned on the surface of the barrier layer;
preparing a source electrode and a drain electrode on the epitaxial structure;
etching part of the epitaxial cap layer and the barrier layer between the source electrode and the drain electrode to form a plurality of groove structures which are arranged at intervals in a direction vertical to a connecting line of the source electrode and the source electrode, wherein the GaN channel layer is exposed from the groove structures, and a plurality of protruding structures are formed between the groove structures;
and forming a gate dielectric layer and a gate electrode layer on the surfaces of the groove structure and the protrusion structure around the groove structure.
2. The method of claim 1, wherein the barrier layer comprises an AlN layer, and the source and drain electrodes each comprise a TixAly layer.
3. The method of claim 1, further comprising, after forming the source and drain electrodes and before forming the recess structure: forming a device mesa device isolation structure in the epitaxial structure; the epitaxial cap layer comprises a GaN cap layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.
4. The method of claim 1, wherein the step of forming the recessed structure and the protruding structure comprises:
removing part of the epitaxial cap layer based on a first process to form a plurality of initial grooves; and
and removing the barrier layer corresponding to the initial groove based on a second process to obtain the groove structure and form the protruding structure, wherein the second process is different from the first process.
5. The method according to claim 4, wherein the first process comprises performing an oxygen plasma oxidation process and then a wet removal process based on the mask layer; the second process includes a selective etching process using wet chemical reagents including at least one of KOH reagents and AZ400K reagents.
6. The method of claim 1, further comprising a step of forming a continuous native oxide layer on the inner wall of the recessed structure and the surface of the protruding structure before forming the gate dielectric layer; forming the gate dielectric layer by adopting an atomic layer deposition process; the method also comprises the step of forming a passivation layer on the surface of the device after the gate electrode layer is formed.
7. The method of claim 6, wherein the native oxide layer and the gate dielectric layer are formed based on an atomic layer deposition process chamber, the native oxide layer is formed based on ozone, and an oxygen source of the gate dielectric layer comprises ozone.
8. The method of claim 1, wherein said gate dielectric layer comprises a BeO material layer, said BeO material layer is deposited at a temperature between 100 ℃ and 300 ℃, and said BeO material layer has a thickness between 5nm and 50 nm.
9. The method of any one of claims 1-8, wherein the width of the groove structure is between 1 and 10 times the width of the protrusion structure along the arrangement direction of the groove structure and the protrusion structure.
10. A dual-channel gate-based GaN device, comprising:
a semiconductor substrate;
the epitaxial structure is formed on the semiconductor substrate and comprises a GaN channel layer, a barrier layer positioned on the GaN channel layer and an epitaxial cap layer positioned on the surface of the barrier layer;
a source electrode and a drain electrode formed on the epitaxial structure;
the GaN channel layer is arranged on the substrate, and the GaN channel layer is arranged on the substrate;
the gate dielectric layer is positioned on the groove structure and the surface of the protruding structure around the groove structure.
11. The dual-channel gate-based GaN device of claim 10 wherein the barrier layer comprises an AlN layer and the source and drain electrodes comprise TixAly layers; the epitaxial cap layer comprises a GaN cap layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm; the dual-channel gate-based GaN device further includes a device isolation structure formed in the epitaxial structure.
12. The dual-channel gate-based GaN device of claim 10 wherein the gate dielectric layer comprises a layer of BeO material having a thickness between 5nm-50 nm.
13. The dual-channel gate-based GaN device of claim 10, wherein a native oxide layer is further formed between the surface of the protruding structure around the groove structure and the gate dielectric layer, and oxygen sources of the native oxide layer and the gate dielectric layer both comprise ozone.
14. The dual-channel gate-based GaN device of any of claims 10-13 wherein the width of the trench structure is between 1 and 10 times the width of the protruding structure along the direction of the arrangement of the trench structure and the protruding structure.
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