CN113451228B - High-strength QFN (quad Flat No lead) packaging structure - Google Patents

High-strength QFN (quad Flat No lead) packaging structure Download PDF

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CN113451228B
CN113451228B CN202110621536.5A CN202110621536A CN113451228B CN 113451228 B CN113451228 B CN 113451228B CN 202110621536 A CN202110621536 A CN 202110621536A CN 113451228 B CN113451228 B CN 113451228B
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parts
chip
pad
qfn
heat dissipation
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CN113451228A (en
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马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
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Xi'an Hangsi Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Die Bonding (AREA)
  • Epoxy Resins (AREA)

Abstract

The invention discloses a high-strength QFN packaging structure, which comprises a heat dissipation pad, a chip and a conductive pad, wherein the heat dissipation pad, the chip and the conductive pad are positioned in an epoxy insulator; the raw materials of the epoxy insulator comprise the following components in parts by weight: epoxy resin, novolac resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, silicon micropowder, gamma-methacryloxypropyltrimethoxysilane, 5-fluoro-2-methoxyaniline, 2,4, 6-tris (dimethylaminomethyl) phenol, a mold release agent and a flame retardant. The QFN packaged semiconductor device enhances the overall mechanical property of an epoxy insulator and can meet the requirement of high-power high-heat-generation chip packaging.

Description

High-strength QFN (quad Flat No lead) packaging structure
Technical Field
The invention belongs to the technical field of leadless packaging, and particularly relates to a high-strength QFN packaging structure.
Background
The QFN package is widely applied to a PCB, and the application of the QFN package greatly promotes the development of electronic technology. The QFN package has excellent thermal performance mainly because the package bottom has a large area of heat dissipation solder, in order to effectively conduct the heat from the chip to the PCB, the bottom of the PCB must be designed with a heat dissipation pad and a heat dissipation via corresponding to the heat dissipation solder, the heat dissipation pad provides a reliable soldering area, and the heat dissipation via provides a heat dissipation path.
Conventional QFN packages typically have a large area heat dissipation pad in the PCB, which is usually grounded, and although the heat dissipation pad can perform the function of dissipating heat from the chip, the pad is too large, and the solder brushing during the Surface Mount Technology (SMT) process often causes a short circuit between the large heat dissipation pad in the center of the QFN package and other small conductive pads. In addition, as the integrated circuit package is developed to be high density, high integration and high speed, the package structure is also exposed to a series of reliability risks caused by heat generated by the chip. Therefore, how to develop a heat-resistant packaging structure with a short-circuit prevention function is of great significance to the development of high-performance electronic devices.
Disclosure of Invention
The invention aims to provide a QFN package semiconductor device which has good short circuit prevention function, good overall mechanical performance, stable structure and high reliability.
In order to achieve the purpose, the invention adopts the technical scheme that: a QFN package semiconductor device comprises a heat dissipation pad, a chip and a conductive pad, wherein the heat dissipation pad, the chip and the conductive pad are positioned in an epoxy insulator, the chip is positioned on the heat dissipation pad, a silver paste layer is arranged between the chip and the heat dissipation pad, a plurality of conductive pads are arranged on the periphery of the heat dissipation pad, and the conductive pads are connected with the chip through a lead;
A separating groove is formed in one side, away from the chip, of the heat dissipation welding disc, the width of the separating groove is 0.1-0.3 mm, the separating groove divides one side, away from the chip, of the heat dissipation welding disc into at least 2 welding disc monomers in an equal dividing mode, heat conduction insulating strips are filled in the separating groove, a plurality of T-shaped grooves extending into the heat dissipation welding disc are formed in the wall of the separating groove, and T-shaped portions filled in the T-shaped grooves are formed in the heat conduction insulating strips;
the raw materials of the epoxy insulator comprise the following components in parts by weight: 85 parts of epoxy resin, 60 parts of novolac resin, 15 parts of liquid nitrile rubber, 8 parts of diphenylmethane diisocyanate, 3 parts of diethyl pyrocarbonate, 3 parts of dibenzyl phosphate, 90 parts of silica powder, 4 parts of gamma-methacryloxypropyltrimethoxysilane, 1.5 parts of 5-fluoro-2-methoxyaniline, 3 parts of 2,4, 6-tris (dimethylaminomethyl) phenol, 4 parts of a release agent and 20 parts of a flame retardant.
The technical scheme of further improvement in the technical scheme is as follows:
1. in the above embodiment, the release agent is stearic acid.
2. In the above scheme, the flame retardant is borate.
3. In the above scheme, the thickness of the heat conducting insulating strip is smaller than the depth of the separation groove.
4. In the above scheme, the area of the bonding pad monomer is not less than 0.3 x 0.3mm 2。
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
1. according to the QFN packaged semiconductor device, the liquid nitrile rubber is added into an epoxy resin system according to the formula of an epoxy insulator, 2,4, 6-tri (dimethylaminomethyl) phenol is used as a curing accelerator, and diethyl pyrocarbonate and 5-fluoro-2-methoxybenzene are additionally added, so that the cross-linking density of a cured substance is improved, the overall mechanical property of the epoxy insulator is enhanced, and the stability of a packaging structure is effectively guaranteed.
2. According to the QFN packaged semiconductor device, the epoxy insulator formula is based on epoxy resin, linear phenolic resin and liquid nitrile rubber, and the diphenylmethane diisocyanate and dibenzyl phosphate are added, so that the prepared resin has excellent heat resistance on the premise of ensuring good mechanical properties, the glass transition temperature reaches 190-230 ℃, and the requirements of high-power and high-heat-generating chip packaging can be met.
3. According to the QFN package semiconductor device, the separating grooves are formed in the surfaces of the radiating welding discs far away from one side of a chip, one part of the radiating welding discs far away from the chip is equally divided into at least two welding disc monomers through the separating grooves with different shapes, and after the radiating welding discs are divided into a plurality of welding disc monomers, the surface areas of the welding disc monomers far away from the chip are smaller than the surface areas of the original radiating welding discs far away from the chip, so that the using amount of solder paste is reduced, and the short circuit phenomenon between the radiating welding discs and the conductive welding discs is effectively controlled; meanwhile, after the heat-conducting insulating strips are filled in the separation grooves, epoxy insulating resin with poor heat-conducting effect cannot be filled in the separation grooves, so that the heat-radiating function of the heat-radiating welding plate part is not affected, and the cost of the surface mount technology can be reduced along with the reduction of the usage amount of the solder paste; in addition, when the heat conduction insulating strip is filled into the separation groove in an injection molding mode, part of resin can enter the T-shaped groove to form a T-shaped part, so that the position of the heat conduction insulating strip is firmly clamped by the T-shaped part and the T-shaped groove, and the influence on the use of the heat conduction insulating strip due to the fact that the heat conduction insulating strip is separated from the separation groove due to injection molding quality problems or external force action is avoided.
Drawings
FIG. 1 is a schematic structural diagram of a high-strength QFN package structure of the present invention;
FIG. 2 is an enlarged view of portion A of FIG. 1;
fig. 3 is a schematic view of a QFN package structure with epoxy removed.
In the drawings above: 1. a heat dissipation pad; 11. a separation tank; 111. a T-shaped slot; 12. a thermally conductive, electrically insulating strip; 121. a T-shaped portion; 13. a bonding pad monomer; 2. a silver paste layer; 3. a chip; 4. a conductive pad; 5. a lead wire; 6. an epoxy insulator.
Detailed Description
The invention is further described below with reference to the following examples:
example (b): a QFN package semiconductor device comprises a heat dissipation pad 1, a chip 3 and conductive pads 4, wherein the heat dissipation pad 1, the chip 3 and the conductive pads 4 are positioned in an epoxy insulator 6, the chip 3 is positioned on the heat dissipation pad 1, a silver paste layer 2 is arranged between the chip 3 and the heat dissipation pad 1, a plurality of conductive pads 4 are arranged on the periphery of the heat dissipation pad 1, and the conductive pads 4 are connected with the chip 3 through leads 5;
a separating groove 11 is formed in one side, away from the chip 3, of the heat dissipation pad 1, the width of the separating groove 11 is 0.1-0.3 mm, the separating groove 11 equally separates one side, away from the chip 3, of the heat dissipation pad 1 into at least 2 pad monomers 13, a heat conduction insulating strip 12 is filled in the separating groove 11, a plurality of T-shaped grooves 111 extending into the heat dissipation pad 1 are formed in the wall of the separating groove 11, and a T-shaped portion 121 filled in the T-shaped grooves 111 is arranged on the heat conduction insulating strip 12;
The thickness of the heat conducting insulating strip 12 is smaller than the depth of the separation groove 11;
the area of the bonding pad single body 13 is not less than 0.3 x 0.3mm2；
The distance between the conductive bonding pad 4 and the heat dissipation bonding pad 1 is 0.3 mm;
the conductive pad 4 is a T-shaped block.
The raw materials of the epoxy insulator 6 comprise the following components in parts by weight: 85 parts of epoxy resin, 60 parts of novolac resin, 15 parts of liquid nitrile rubber, 8 parts of diphenylmethane diisocyanate, 3 parts of diethyl pyrocarbonate, 3 parts of dibenzyl phosphate, 90 parts of silica powder, 4 parts of gamma-methacryloxypropyltrimethoxysilane, 1.5 parts of 5-fluoro-2-methoxyaniline, 3 parts of 2,4, 6-tris (dimethylaminomethyl) phenol, 4 parts of a release agent and 20 parts of a flame retardant.
The fine silica powder is fused fine silica powder, the fine silica powder D50 is 4 to 8 μm, and the fine silica powder D100 is 10 to 25 μm.
The release agent is stearate, and the flame retardant is borate.
The preparation method of the raw material of the epoxy insulator 6 comprises the following steps:
s1, uniformly mixing the silicon micropowder, the flame retardant and gamma-methacryloxypropyl trimethoxysilane, and carrying out surface treatment;
s2, adding epoxy resin, novolac resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, 5-fluoro-2-methoxyaniline, 2,4, 6-tris (dimethylaminomethyl) phenol and a release agent, and uniformly mixing;
S3, mixing the mixture at 90-110 ℃ for 3-5 minutes, cooling the product, crushing and sieving.
Comparative examples 1 to 3: an epoxy insulator comprises the following raw materials in parts by weight:
TABLE 1
Figure DEST_PATH_IMAGE002
The fine silicon powder is fused fine silicon powder, the fine silicon powder D50 is 4-8 μm, and the fine silicon powder D100 is 10-25 μm.
The release agent in comparative example 1 was stearic acid, and the flame retardant was borate; the release agent in comparative example 2 was stearate and the flame retardant was borate; the release agent in comparative example 3 was oxidized polyethylene wax and the flame retardant was molybdate.
The preparation process is the same as the embodiment.
The properties of the epoxy insulators prepared in the above examples and comparative examples 1 to 3 are shown in table 2:
TABLE 2
Figure DEST_PATH_IMAGE003
In each of examples and comparative examples, the molding conditions of the epoxy insulator were as follows: the mold temperature is 180 ℃, and the injection pressure is 700kg/cm2Curing time 2 min.
As shown in the evaluation results in table 2, the epoxy insulators in the embodiments have better overall mechanical properties and heat resistance than the comparative examples, and when used in the QFN package structure, the stability of the package structure can be ensured, and the requirements of high-power and high-heat-generation chip package can be met.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (5)

1. A high strength QFN packaging structure which characterized in that: the LED chip comprises a radiating pad (1) positioned in an epoxy insulator (6), a chip (3) and a conductive bonding pad (4), wherein the chip (3) is positioned on the radiating pad (1), a silver paste layer (2) is arranged between the chip (3) and the radiating pad (1), a plurality of conductive bonding pads (4) are arranged on the periphery of the radiating pad (1), and the conductive bonding pads (4) are connected with the chip (3) through leads (5);
a separating groove (11) is formed in one side, away from the chip (3), of the radiating pad (1), the width of the separating groove (11) is 0.1-0.3 mm, the separating groove (11) divides one side, away from the chip (3), of the radiating pad (1) into at least 2 pad monomers (13) in an equal partition mode, a heat-conducting insulating strip (12) is filled in the separating groove (11), a plurality of T-shaped grooves (111) extending into the radiating pad (1) are formed in the wall of the separating groove (11), and a T-shaped portion (121) filled in the T-shaped grooves (111) is arranged on the heat-conducting insulating strip (12);
the raw materials of the epoxy insulator (6) comprise the following components in parts by weight: 85 parts of epoxy resin, 60 parts of novolac resin, 15 parts of liquid nitrile rubber, 8 parts of diphenylmethane diisocyanate, 3 parts of diethyl pyrocarbonate, 3 parts of dibenzyl phosphate, 90 parts of silica powder, 4 parts of gamma-methacryloxypropyltrimethoxysilane, 1.5 parts of 5-fluoro-2-methoxyaniline, 3 parts of 2,4, 6-tris (dimethylaminomethyl) phenol, 4 parts of a release agent and 20 parts of a flame retardant.
2. The high strength QFN package structure of claim 1, wherein: the release agent is fatty acid salt.
3. The high strength QFN package structure of claim 1, wherein: the flame retardant is borate.
4. The high strength QFN package structure of claim 3, wherein: the distance between the conductive bonding pad (4) and the heat dissipation bonding pad (1) is 0.3 mm.
5. The high strength QFN package structure of claim 1, wherein: the conductive bonding pad (4) is a T-shaped block.
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CN109904124B (en) 2021-04-23
CN113451228A (en) 2021-09-28
CN113451227B (en) 2022-07-19
CN113451226A (en) 2021-09-28
CN113451226B (en) 2022-07-19
CN113451227A (en) 2021-09-28

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