CN107275305B - QFN chip - Google Patents

QFN chip Download PDF

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Publication number
CN107275305B
CN107275305B CN201710570519.7A CN201710570519A CN107275305B CN 107275305 B CN107275305 B CN 107275305B CN 201710570519 A CN201710570519 A CN 201710570519A CN 107275305 B CN107275305 B CN 107275305B
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China
Prior art keywords
tin
longitudinal
grooves
transverse
pad
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Active
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CN201710570519.7A
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Chinese (zh)
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CN107275305A (en
Inventor
于浩
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Zhengzhou Yunhai Information Technology Co Ltd
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Zhengzhou Yunhai Information Technology Co Ltd
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Priority to CN201710570519.7A priority Critical patent/CN107275305B/en
Publication of CN107275305A publication Critical patent/CN107275305A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The invention discloses a QFN chip, which comprises a chip body, wherein a bonding pad is arranged on the chip body, a plurality of transverse tin guiding grooves and a plurality of longitudinal tin guiding grooves are formed in the bonding pad, and the transverse tin guiding grooves and the longitudinal tin guiding grooves are arranged in a mutually crossed mode and are mutually communicated. Firstly, brushing solder paste on a bonding pad on a circuit board, then moving the chip body to the circuit board, further enabling the bonding pad on the chip body and the bonding pad on the circuit board to be stuck together through the solder paste, and then heating, melting the solder paste and realizing welding; in the process, the bonding pad is divided into a plurality of small blocks by the transverse tin guiding grooves and the longitudinal tin guiding grooves, so that the heated solder paste can flow conveniently, and the coverage area of the solder paste on the two bonding pads is increased; meanwhile, the transverse tin guiding grooves and the longitudinal tin guiding grooves provide flow paths for the solder paste, and are beneficial to increasing the welding area and the coverage rate of the solder paste on the two bonding pads, so that the welding strength is increased, and the welding quality and the product quality are also effectively improved.

Description

QFN chip
Technical Field
The invention relates to the technical field of QFN (quad Flat No-lead) packaging, in particular to a QFN chip.
Background
At present, the integration level of electronic parts is higher and higher, and more electronic parts are designed by using an Integrated Circuit (IC) with higher integration level. Usually, the server system or the personal computer is designed as a motherboard, and the number of ICs with higher integration level is very large. However, because the space on the main board is limited, the risk of ESD (Electro-static discharge) is also high, and the package method using pins (pins) is gradually eliminated.
At present, a QFN Package (Quad Flat No-lead Package) is the most common, and the specific manner of QFN Package is as follows: and pads (copper foils) are arranged on the circuit board and the QFN chip, and the two pads are welded together to realize QFN packaging. However, in the production process, because the welding surfaces of the two bonding pads are both planes with larger sectional areas, the covering area of the solder paste on the two bonding pads does not reach the standard during welding, and further the contact area of the two bonding pads is small (the contact of the two bonding pads is realized by the solder paste), the poor welding condition is caused, and the welding quality and the product quality are greatly influenced.
Disclosure of Invention
The embodiment of the invention aims to provide a QFN chip, which achieves the aims of improving the welding quality and the product quality.
In order to solve the technical problem, the technical scheme of the embodiment of the invention is as follows: a QFN chip comprises a chip body, wherein a bonding pad is arranged on the chip body, a plurality of transverse-direction tin guiding grooves and a plurality of longitudinal-direction tin guiding grooves are formed in the bonding pad, and the transverse-direction tin guiding grooves and the longitudinal-direction tin guiding grooves are arranged in a mutually crossed mode and are mutually communicated;
wherein, still be equipped with following structure on the pad:
a plurality of bulges are arranged on the bonding pad positioned in the transverse tin guiding groove and the longitudinal tin guiding groove, the bulges are not arranged at the communication position of the transverse tin guiding groove and the longitudinal tin guiding groove, and a space is arranged between every two adjacent bulges; the extending direction of the protrusion is consistent with the extending direction of the transverse tin guiding groove or the longitudinal tin guiding groove, the height of the protrusion is smaller than the depth of the transverse tin guiding groove or the longitudinal tin guiding groove, and the cross section of the protrusion is trapezoidal;
or, with horizontal guide tin recess with vertical guide tin recess corresponds the position be equipped with at least one shrinkage pool on the pad, the shrinkage pool is followed the direction of height extension of pad, just the shrinkage pool with horizontal guide tin recess or vertical guide tin recess communicates each other, and every shrinkage pool that is located horizontal guide tin recess and vertical guide tin recess all corresponds a fritter pad, wherein, the fritter pad is cut apart the pad through horizontal guide tin recess and vertical guide tin recess and forms.
As an improvement, all the transverse tin guiding grooves and all the longitudinal tin guiding grooves are arranged perpendicular to each other.
As a further improvement, all the transverse tin-guiding grooves are arranged in an array in the width direction of the bonding pad; all the longitudinal tin guide grooves are arranged in an array in the length direction of the bonding pad.
As a further improvement, the distance between two adjacent transverse tin guiding grooves is equal to the distance between two adjacent longitudinal tin guiding grooves.
As a still further improvement, the lateral tin-guiding groove and the longitudinal tin-guiding groove are both omega grooves.
Due to the adoption of the technical scheme, the QFN chip provided by the embodiment of the invention has the following beneficial effects:
because the welding pad is provided with a plurality of transverse tin guiding grooves and a plurality of longitudinal tin guiding grooves which are arranged in a crossed manner, when the QFN chip is welded on the circuit board, firstly, the welding pad on the circuit board is brushed with tin paste, then, the chip body is moved onto the circuit board, the welding pad on the chip body and the welding pad on the circuit board are mutually corresponding up and down, then, the two welding pads are stuck together through the tin paste, then, the heating is carried out, the tin paste is melted, and the two welding pads are welded together; in the process, due to the existence of the plurality of transverse-direction tin guide grooves and the plurality of longitudinal-direction tin guide grooves, the bonding pad is divided into a plurality of small blocks, so that the heated solder paste can flow conveniently during welding, and the coverage area of the solder paste on the two bonding pads is greatly increased; meanwhile, the communicated transverse tin guide groove and the longitudinal tin guide groove provide a flow path for heated tin paste, so that the increase of the welding area is facilitated, the coverage rate of the tin paste on the two bonding pads is improved, the welding strength is greatly increased, and the welding quality and the product quality are also effectively improved.
Because all the transverse-direction tin guide grooves and all the longitudinal-direction tin guide grooves are perpendicular to each other, the processing is convenient, and the flowing of tin paste in the welding process is facilitated.
All the transverse tin guiding grooves are arranged in an array in the width direction of the bonding pad; all the longitudinal tin guide grooves are arranged in an array in the length direction of the bonding pad, so that the processing of a plurality of transverse tin guide grooves and longitudinal tin guide grooves is facilitated.
Because the distance between two adjacent horizontal guide tin grooves is equal to the distance between two adjacent vertical guide tin grooves, the bonding pad is divided into a plurality of small blocks with the same size through the structure, and the improvement of the welding quality is facilitated.
Because the transverse tin guiding groove and the longitudinal tin guiding groove are omega grooves, the bonding force between the solder paste (after being heated and cured) and the bonding pad is improved through the omega grooves.
Because be equipped with at least one shrinkage pool on the pad with transversely leading the tin recess and vertically leading the tin recess corresponding position, the shrinkage pool extends along the direction of height of pad, and the shrinkage pool with transversely lead the tin recess or vertically lead the tin recess and communicate each other, thereby through this structure, the tin cream after the heating passes through in the horizontal guide tin recess or vertically leads the tin recess and gets into the notch, the area of contact of tin cream with the pad has been increased, the cohesion of tin cream (after heating and solidification) and pad is helped improving equally.
Because be located and be equipped with many archs on the pad in horizontal guide tin recess and the vertical guide tin recess, be equipped with the interval between the two adjacent archs, bellied extending direction is unanimous with the extending direction who transversely leads tin recess or vertically leads tin recess, and bellied highly be less than the degree of depth of horizontal guide tin recess or vertically leading tin recess, thereby through many archs, transversely lead tin recess and vertically lead the tin recess and form wave structure or notch cuttype structure, and then greatly increased the area of contact of tin cream and pad, help improving the cohesion of tin cream (after heating and solidification) and pad.
Drawings
FIG. 1 is a schematic structural diagram of a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a third embodiment of the present invention;
FIG. 4 is a cross-sectional view A-A of FIG. 3;
FIG. 5 is a schematic structural diagram of a fourth embodiment of the present invention;
FIG. 6 is an enlarged view of B in FIG. 5;
in the figure, 1-chip body; 101-a pad; 102-transverse tin guiding grooves; 103-longitudinal tin guiding grooves; 104-concave holes; 105-convex.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The first embodiment is as follows:
as shown in fig. 1, a QFN chip includes a chip body 1, a pad 101 is disposed on the chip body 1, a plurality of transverse tin guiding grooves 102 and a plurality of longitudinal tin guiding grooves 103 are disposed on the pad 101, and the transverse tin guiding grooves 102 and the longitudinal tin guiding grooves 103 are all disposed in a cross manner and are communicated with each other.
Preferably, all the transverse tin-guiding grooves 102 and all the longitudinal tin-guiding grooves 103 are arranged perpendicular to each other; and all the transverse tin-conducting grooves 102 are arranged in an array in the width direction of the pad 101, and all the longitudinal tin-conducting grooves 103 are arranged in an array in the length direction of the pad 101.
The distance between two adjacent transverse tin guiding grooves 102 is equal to the distance between two adjacent longitudinal tin guiding grooves 103, and the width of the transverse tin guiding groove 102 is the same as that of the longitudinal tin guiding groove 103.
Example two:
the structure of this embodiment is substantially the same as that of the first embodiment, and the difference is that: the transverse tin guiding groove 102 and the longitudinal tin guiding groove 103 are omega grooves (see fig. 2).
Example three:
the structure of this embodiment is substantially the same as that of the first embodiment, and the difference is that: at least one concave hole 104 is arranged on the bonding pad 101 at the position corresponding to the transverse tin guiding groove 102 and the longitudinal tin guiding groove 103, the concave hole 104 extends along the height direction of the bonding pad 101, and the concave hole 104 is communicated with the transverse tin guiding groove 102 or the longitudinal tin guiding groove 103 (see fig. 3 and 4). In this embodiment, each concave hole 104 located in the transverse tin guiding groove 102 and the longitudinal tin guiding groove 103 corresponds to a small pad (the small pad is formed by dividing the pad 101 through the transverse tin guiding groove 102 and the longitudinal tin guiding groove 103).
Example four:
the structure of this embodiment is substantially the same as that of the first embodiment, and the difference is that: the bonding pad 101 located in the transverse tin guiding groove 102 and the longitudinal tin guiding groove 103 is provided with a plurality of protrusions 105, the cross-sectional shape of the protrusions 105 is trapezoidal, but other shapes can be adopted, such as: arc, etc.; a space is arranged between every two adjacent trapezoidal protrusions 105, and the space is a groove formed between every two adjacent trapezoidal protrusions 105; the extending direction of the protrusion 105 is consistent with the extending direction of the transverse tin guiding groove 102 or the longitudinal tin guiding groove 103, and the height of the protrusion 105 is smaller than the depth of the transverse tin guiding groove 102 or the longitudinal tin guiding groove 103 (see fig. 5 and 6). Preferably, no bump 105 is provided at the communication position of the transverse tin guiding groove 102 and the longitudinal tin guiding groove 103, so that the heated solder paste flows.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (5)

1. A QFN chip is characterized by comprising a chip body, wherein a bonding pad is arranged on the chip body, a plurality of transverse-direction tin guiding grooves and a plurality of longitudinal-direction tin guiding grooves are formed in the bonding pad, and the transverse-direction tin guiding grooves and the longitudinal-direction tin guiding grooves are arranged in a mutually crossed mode and are mutually communicated;
wherein, still be equipped with following structure on the pad:
a plurality of bulges are arranged on the bonding pad positioned in the transverse tin guiding groove and the longitudinal tin guiding groove, the bulges are not arranged at the communication position of the transverse tin guiding groove and the longitudinal tin guiding groove, and a space is arranged between every two adjacent bulges; the extending direction of the protrusion is consistent with the extending direction of the transverse tin guiding groove or the longitudinal tin guiding groove, the height of the protrusion is smaller than the depth of the transverse tin guiding groove or the longitudinal tin guiding groove, and the cross section of the protrusion is trapezoidal;
or, with horizontal guide tin recess with vertical guide tin recess corresponds the position be equipped with at least one shrinkage pool on the pad, the shrinkage pool is followed the direction of height extension of pad, just the shrinkage pool with horizontal guide tin recess or vertical guide tin recess communicates each other, and every shrinkage pool that is located horizontal guide tin recess and vertical guide tin recess all corresponds a fritter pad, wherein, the fritter pad is cut apart the pad through horizontal guide tin recess and vertical guide tin recess and forms.
2. The QFN chip of claim 1, wherein all the lateral tin grooves and all the longitudinal tin grooves are disposed perpendicular to each other.
3. The QFN chip of claim 2, wherein all the lateral tin-guiding grooves are arranged in an array in a width direction of the pad; all the longitudinal tin guide grooves are arranged in an array in the length direction of the bonding pad.
4. The QFN chip as claimed in claim 3, wherein the distance between two adjacent transverse solder grooves is equal to the distance between two adjacent longitudinal solder grooves.
5. The QFN chip of any of claims 1-4, wherein the lateral and longitudinal solder grooves are omega grooves.
CN201710570519.7A 2017-07-13 2017-07-13 QFN chip Active CN107275305B (en)

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CN201710570519.7A CN107275305B (en) 2017-07-13 2017-07-13 QFN chip

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CN107275305B true CN107275305B (en) 2020-03-10

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845721A (en) * 2017-10-23 2018-03-27 山东晶泰星光电科技有限公司 A kind of LED support for being used for upside-down mounting or vertical LED chip
CN107833960A (en) * 2017-10-23 2018-03-23 山东晶泰星光电科技有限公司 A kind of LED support and its manufacture method with overflow ducts and overflow launder
CN108075026A (en) * 2017-12-08 2018-05-25 蔡志嘉 Three defending type LED component and preparation method thereof
CN113451227B (en) * 2019-03-06 2022-07-19 西安航思半导体有限公司 High-reliability QFN (quad Flat No lead) packaging device structure
CN109904125B (en) * 2019-03-06 2021-02-19 西安航思半导体有限公司 Preparation method of high-temperature-resistant QFN packaging structure
CN112909153B (en) * 2019-12-03 2022-12-16 深圳市聚飞光电股份有限公司 Flip LED chip, circuit board and electronic equipment
CN111451666A (en) * 2020-05-01 2020-07-28 贤阳汇聚精密科技(苏州)有限公司 Preforming soldering lug

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CN103579166A (en) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 Pad structure
CN103794583A (en) * 2012-10-30 2014-05-14 中国科学院上海微***与信息技术研究所 Method for enhancing the adhesiveness between solder ball and UBM
CN206193724U (en) * 2015-09-03 2017-05-24 东友精细化工有限公司 Touch panel reaches display device including touch panel
CN106910728A (en) * 2017-02-28 2017-06-30 郑州云海信息技术有限公司 A kind of improvement QFN encapsulates the method for designing of chip welding quality

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US6953990B2 (en) * 2003-09-19 2005-10-11 Agilent Technologies, Inc. Wafer-level packaging of optoelectronic devices
JP2008294172A (en) * 2007-05-24 2008-12-04 Panasonic Corp Lead frame, semiconductor device, and manufacturing method of semiconductor device
JP2011198796A (en) * 2010-03-17 2011-10-06 Fujitsu Ltd Semiconductor device and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
CN103579166A (en) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 Pad structure
CN103794583A (en) * 2012-10-30 2014-05-14 中国科学院上海微***与信息技术研究所 Method for enhancing the adhesiveness between solder ball and UBM
CN206193724U (en) * 2015-09-03 2017-05-24 东友精细化工有限公司 Touch panel reaches display device including touch panel
CN106910728A (en) * 2017-02-28 2017-06-30 郑州云海信息技术有限公司 A kind of improvement QFN encapsulates the method for designing of chip welding quality

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