CN109904124B - QFN (quad Flat No-lead) packaging structure with short-circuit prevention function - Google Patents

QFN (quad Flat No-lead) packaging structure with short-circuit prevention function Download PDF

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CN109904124B
CN109904124B CN201910166939.8A CN201910166939A CN109904124B CN 109904124 B CN109904124 B CN 109904124B CN 201910166939 A CN201910166939 A CN 201910166939A CN 109904124 B CN109904124 B CN 109904124B
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parts
pad
prevention function
chip
circuit prevention
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CN109904124A (en
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马磊
党鹏
杨光
彭小虎
王新刚
庞朋涛
任斌
王妙妙
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Xi'an Hangsi Semiconductor Co ltd
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Xi'an Hangsi Semiconductor Co ltd
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Priority to CN202110621536.5A priority Critical patent/CN113451228B/en
Priority to CN201910166939.8A priority patent/CN109904124B/en
Priority to CN202110620907.8A priority patent/CN113451226B/en
Priority to CN202110620909.7A priority patent/CN113451227B/en
Priority to CN202110620908.2A priority patent/CN113451235B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Epoxy Resins (AREA)
  • Die Bonding (AREA)

Abstract

The invention discloses a QFN (quad Flat No-lead) packaging structure with a short-circuit prevention function, which comprises a radiating pad, a chip and a conductive pad, wherein the radiating pad, the chip and the conductive pad are positioned in an epoxy insulator; the epoxy insulator comprises the following raw materials in parts by weight: 80-100 parts of epoxy resin, linear phenolic resin, liquid nitrile rubber, diphenylmethane diisocyanate, diethyl pyrocarbonate, dibenzyl phosphate, silicon micropowder, gamma-methacryloxypropyl trimethoxysilane, 5-fluoro-2-methoxyaniline, 2,4, 6-tris (dimethylaminomethyl) phenol, a release agent and a flame retardant. The QFN packaging structure has a good short circuit prevention function, good overall mechanical performance, stable structure and high reliability.

Description

QFN (quad Flat No-lead) packaging structure with short-circuit prevention function
Technical Field
The invention belongs to the technical field of pin-free packaging, and particularly relates to a QFN packaging structure with a short-circuit prevention function.
Background
The QFN package is widely applied to a PCB, and the application of the QFN package greatly promotes the development of electronic technology. The QFN package has excellent thermal performance mainly because the package bottom has a large area of heat dissipation solder, in order to effectively conduct the heat from the chip to the PCB, the bottom of the PCB must be designed with a heat dissipation pad and a heat dissipation via corresponding to the heat dissipation solder, the heat dissipation pad provides a reliable soldering area, and the heat dissipation via provides a heat dissipation path.
Conventional QFN packages typically have a large area heat dissipation pad in the PCB, which is usually grounded, and although the heat dissipation pad can perform the function of dissipating heat from the chip, the pad is too large, and the solder brushing during the Surface Mount Technology (SMT) process often causes a short circuit between the large heat dissipation pad in the center of the QFN package and other small conductive pads. In addition, as the integrated circuit package is developed to be high density, high integration and high speed, the package structure is also exposed to a series of reliability risks caused by heat generated by the chip. Therefore, how to develop a heat-resistant packaging structure with a short-circuit prevention function is of great significance to the development of high-performance electronic devices.
Disclosure of Invention
The invention aims to provide a QFN packaging structure with a short-circuit prevention function, which has a good short-circuit prevention function, good overall mechanical property, stable structure and high reliability.
In order to achieve the purpose, the invention adopts the technical scheme that: a QFN packaging structure with a short circuit prevention function comprises a heat dissipation pad, a chip and a conductive pad, wherein the heat dissipation pad, the chip and the conductive pad are positioned in an epoxy insulator;
a separating groove is formed in one side, away from the chip, of the heat dissipation welding disc, the width of the separating groove is 0.1-0.3 mm, the separating groove divides one side, away from the chip, of the heat dissipation welding disc into at least 2 welding disc monomers in an equal dividing mode, heat conduction insulating strips are filled in the separating groove, a plurality of T-shaped grooves extending into the heat dissipation welding disc are formed in the wall of the separating groove, and T-shaped portions filled in the T-shaped grooves are formed in the heat conduction insulating strips;
the epoxy insulator comprises the following raw materials in parts by weight:
80-100 parts of epoxy resin,
45-60 parts of linear phenolic resin,
15-20 parts of liquid nitrile rubber,
6-10 parts of diphenylmethane diisocyanate,
3-8 parts of diethyl pyrocarbonate,
2-6.5 parts of dibenzyl phosphate,
60-90 parts of silicon micro-powder,
3-8 parts of gamma-methacryloxypropyltrimethoxysilane,
0.3 to 2 parts of 5-fluoro-2-methoxyaniline,
0.5 to 4 parts of 2,4, 6-tris (dimethylaminomethyl) phenol,
2-5 parts of a mold release agent,
10-25 parts of a flame retardant.
The technical scheme of further improvement in the technical scheme is as follows:
1. in the above embodiment, the release agent is at least one selected from stearic acid, stearate, and oxidized polyethylene wax.
2. In the scheme, the flame retardant is borate and/or molybdate.
3. In the above scheme, the silica fume is fused silica fume.
4. In the scheme, the silicon micropowder D50 is 4-8 μm, and the silicon micropowder D100 is 10-25 μm.
5. In the above scheme, the thickness of the heat conducting insulating strip is smaller than the depth of the separation groove.
6. In the above scheme, the area of the bonding pad monomer is not less than 0.3 x 0.3mm2。
7. In the above scheme, the distance between the conductive pad and the heat dissipation pad is 0.3 mm.
8. In the above scheme, the conductive pad is a T-shaped block.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
1. according to the QFN packaging structure with the short-circuit prevention function, 15-20 parts of liquid nitrile rubber is added into an epoxy resin system according to the formula of an epoxy insulator, 0.5-4 parts of 2,4, 6-tri (dimethylaminomethyl) phenol are used as a curing accelerator, and 3-8 parts of diethyl pyrocarbonate and 0.3-2 parts of 5-fluoro-2-methoxyaniline are additionally added, so that the crosslinking density of a cured product is improved, the overall mechanical property of the epoxy insulator is enhanced, and the stability of the packaging structure is effectively guaranteed.
2. The invention relates to a QFN packaging structure with a short-circuit prevention function, wherein an epoxy insulator is prepared by adding 6-10 parts of diphenylmethane diisocyanate and 2-6.5 parts of dibenzyl phosphate on the basis of 80-100 parts of epoxy resin, 45-60 parts of linear phenolic resin and 15-20 parts of liquid nitrile rubber, and the prepared resin has excellent heat resistance and vitrification temperature of 190-230 ℃ on the premise of ensuring good mechanical property and can meet the requirement of high-power high-heating chip packaging.
3. The invention has QFN packaging structure with short-circuit prevention function, the surface of the radiating pad far away from one side of the chip is provided with the separating groove, the part of the radiating pad far away from the chip is equally divided into at least two pad monomers by the separating grooves with different shapes, and after the radiating pad is divided into a plurality of pad monomers, the surface area of one side of the pad monomer far away from the chip is smaller than that of the original radiating pad far away from the chip, thereby reducing the using amount of solder paste and further effectively controlling the short-circuit phenomenon between the radiating pad and the conductive pad; meanwhile, after the heat-conducting insulating strips are filled in the separation grooves, epoxy insulating resin with poor heat-conducting effect cannot be filled in the separation grooves, so that the heat-radiating function of the heat-radiating welding pad part is not affected, and the cost of the surface mount technology can be reduced along with the reduction of the use amount of the solder paste; in addition, when the heat-conducting insulating strip is filled into the separation groove in an injection molding mode, part of resin can enter the T-shaped groove to form a T-shaped part, so that the position of the heat-conducting insulating strip is firmly clamped by the T-shaped part and the T-shaped groove, and the phenomenon that the heat-conducting insulating strip is separated from the separation groove to influence the use of the heat-conducting insulating strip due to injection molding quality problems or external force is avoided.
Drawings
FIG. 1 is a schematic diagram of a QFN package structure with short-circuit prevention function according to the present invention;
fig. 2 is an enlarged view of a portion of fig. 1A.
In the above drawings: 1. a heat-dissipating pad; 11. a separation tank; 111. a T-shaped slot; 12. a thermally conductive insulating strip; 121. a T-shaped portion; 13. a bonding pad monomer; 2. a silver paste layer; 3. a chip; 4. a conductive pad; 5. a lead wire; 6. an epoxy insulator.
Detailed Description
The invention is further described below with reference to the following examples:
examples 1 to 4: a QFN packaging structure with a short circuit prevention function comprises a heat dissipation pad 1, a chip 3 and a conductive pad 4, wherein the heat dissipation pad 1, the chip 3 and the conductive pad 4 are positioned in an epoxy insulator 6, the chip 3 is positioned on the heat dissipation pad 1, a silver paste layer 2 is arranged between the chip 3 and the heat dissipation pad 1, a plurality of conductive pads 4 are arranged on the periphery of the heat dissipation pad 1, and the conductive pads 4 are connected with the chip 3 through leads 5;
a separating groove 11 is formed in one side, away from the chip 3, of the heat dissipation pad 1, the width of the separating groove 11 is 0.1-0.3 mm, the separating groove 11 equally separates one side, away from the chip 3, of the heat dissipation pad 1 into at least 2 pad monomers 13, a heat conduction insulating strip 12 is filled in the separating groove 11, a plurality of T-shaped grooves 111 extending into the heat dissipation pad 1 are formed in the wall of the separating groove 11, and a T-shaped portion 121 filled in the T-shaped grooves 111 is arranged on the heat conduction insulating strip 12;
the thickness of the heat conducting insulating strip 12 is smaller than the depth of the separation groove 11;
the area of the bonding pad single body 13 is not less than 0.3 x 0.3mm2；
The distance between the conductive bonding pad 4 and the heat dissipation bonding pad 1 is 0.3 mm;
the conductive pad 4 is a T-shaped block.
The raw materials of the epoxy insulator 6 comprise the following components in parts by weight:
TABLE 1
Components Example 1 Example 2 Example 3 Example 4
Epoxy resin 80 85 90 100
Phenol novolac resin 50 60 45 55
Liquid nitrile rubber 20 15 16 18
Diphenylmethane diisocyanate 6 8 9 10
Pyrocarbonic acid diethyl ester 7 3 5 8
Phosphoric acid dibenzyl ester 6.5 3 5 2
Silicon micropowder 60 90 80 70
Gamma-methacryloxypropyltrimethoxysilane 6 4 3 8
5-fluoro-2-methoxyaniline 0.3 1.5 2 1
2,4, 6-tris (dimethylaminomethyl) phenol 4 3 1.5 0.5
Release agent 3 4 2 5
Flame retardant 25 20 15 10
The fine silica powder is fused fine silica powder, the fine silica powder D50 is 4 to 8 μm, and the fine silica powder D100 is 10 to 25 μm.
The mold release agent in example 1 was stearic acid and the flame retardant was borate; the mold release agent in example 2 was stearate and the flame retardant was borate; the release agent in example 3 was oxidized polyethylene wax and the flame retardant was molybdate; the mold release agent in example 4 was a mixture of stearic acid and oxidized polyethylene wax, and the flame retardant was molybdate.
The preparation method of the raw material of the epoxy insulator 6 comprises the following steps:
s1, uniformly mixing 60-90 parts of silicon micropowder, 10-25 parts of flame retardant and 3-8 parts of gamma-methacryloxypropyltrimethoxysilane, and performing surface treatment;
s2, adding 80-100 parts of epoxy resin, 45-60 parts of novolac resin, 15-20 parts of liquid nitrile rubber, 6-10 parts of diphenylmethane diisocyanate, 3-8 parts of diethyl pyrocarbonate, 2-6.5 parts of dibenzyl phosphate, 0.3-2 parts of 5-fluoro-2-methoxyaniline, 0.5-4 parts of 2,4, 6-tris (dimethylaminomethyl) phenol and 2-5 parts of a mold release agent, and uniformly mixing;
s3, mixing the mixture at 90-110 ℃ for 3-5 minutes, cooling the product, crushing and sieving.
Comparative examples 1 to 3: the epoxy insulator comprises the following raw materials in parts by weight:
TABLE 2
Components Comparative example 1 Comparative example 2 Comparative example 3
Epoxy resin 90 80 100
Phenol novolac resin 60 45 55
Liquid nitrile rubber 20 5 16
Diphenylmethane diisocyanate 2 6 3
Pyrocarbonic acid diethyl ester 8 3 -
Phosphoric acid dibenzyl ester 6.5 - -
Silicon micropowder 60 90 80
Gamma-methacryloxypropyltrimethoxysilane 5 3 8
5-fluoro-2-methoxyaniline - 1.5 2
2,4, 6-tris (dimethylaminomethyl) phenol 4 0.5 2
Release agent 4 2 5
Release agent 25 10 15
The fine silica powder is fused fine silica powder, the fine silica powder D50 is 4 to 8 μm, and the fine silica powder D100 is 10 to 25 μm.
The release agent in comparative example 1 was stearic acid and the flame retardant was borate; the release agent in comparative example 2 was stearate and the flame retardant was borate; the release agent in comparative example 3 was oxidized polyethylene wax and the flame retardant was molybdate.
The preparation process is the same as the embodiment.
The properties of the epoxy insulators prepared in examples 1 to 4 and comparative examples 1 to 3 are shown in Table 3:
TABLE 3
Figure DEST_PATH_IMAGE001
In each of examples and comparative examples, the molding conditions of the epoxy insulator were as follows: the mold temperature is 180 ℃, and the injection pressure is 700kg/cm2Curing time 2 min.
As shown in the evaluation results in table 3, the epoxy insulators in the embodiments have better overall mechanical properties and heat resistance than the comparative examples, and when used in the QFN package structure, the stability of the package structure can be ensured, and the requirements of high-power and high-heat-generation chip package can be met.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (8)

1. The utility model provides a QFN packaging structure with prevent short circuit function which characterized in that: the LED packaging structure comprises a radiating pad (1), a chip (3) and a conductive pad (4) which are positioned in an epoxy insulator (6), wherein the chip (3) is positioned on the radiating pad (1), a silver paste layer (2) is arranged between the chip (3) and the radiating pad (1), a plurality of conductive pads (4) are arranged on the periphery of the radiating pad (1), and the conductive pad (4) is connected with the chip (3) through a lead (5);
a separating groove (11) is formed in one side, away from the chip (3), of the heat dissipation pad (1), the width of the separating groove (11) is 0.1-0.3 mm, the separating groove (11) divides the side, away from the chip (3), of the heat dissipation pad (1) into at least 2 pad single bodies (13) in an equal division mode, a heat conduction insulating strip (12) is filled in the separating groove (11), a plurality of T-shaped grooves (111) extending into the heat dissipation pad (1) are formed in the wall of the separating groove (11), and a T-shaped portion (121) filled in the T-shaped grooves (111) is arranged on the heat conduction insulating strip (12);
the epoxy insulator (6) comprises the following raw materials in parts by weight:
80-100 parts of epoxy resin,
45-60 parts of linear phenolic resin,
15-20 parts of liquid nitrile rubber,
6-10 parts of diphenylmethane diisocyanate,
3-8 parts of diethyl pyrocarbonate,
2-6.5 parts of dibenzyl phosphate,
60-90 parts of silicon micro-powder,
3-8 parts of gamma-methacryloxypropyltrimethoxysilane,
0.3 to 2 parts of 5-fluoro-2-methoxyaniline,
0.5 to 4 parts of 2,4, 6-tris (dimethylaminomethyl) phenol,
2-5 parts of a mold release agent,
10-25 parts of a flame retardant.
2. The QFN package structure with short circuit prevention function according to claim 1, wherein: the release agent is selected from at least one of stearic acid, stearate or oxidized polyethylene wax.
3. The QFN package structure with short circuit prevention function according to claim 1, wherein: the flame retardant is borate and/or molybdate.
4. The QFN package structure with short circuit prevention function according to claim 1, wherein: the silicon micropowder is fused silicon micropowder.
5. The QFN package structure with short circuit prevention function according to claim 1, wherein: the thickness of the heat conduction insulating strip (12) is smaller than the depth of the separation groove (11).
6. The QFN package structure with short circuit prevention function according to claim 1, wherein: the area of the bonding pad single body (13) is not less than 0.3 x 0.3mm2。
7. The QFN package structure with short-circuit prevention function as claimed in claim 3, wherein: the distance between the conductive pad (4) and the heat dissipation pad (1) is 0.3 mm.
8. The QFN package structure with short circuit prevention function according to claim 1, wherein: the conductive bonding pad (4) is a T-shaped block.
CN201910166939.8A 2019-03-06 2019-03-06 QFN (quad Flat No-lead) packaging structure with short-circuit prevention function Active CN109904124B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN202110621536.5A CN113451228B (en) 2019-03-06 2019-03-06 High-strength QFN (quad Flat No lead) packaging structure
CN201910166939.8A CN109904124B (en) 2019-03-06 2019-03-06 QFN (quad Flat No-lead) packaging structure with short-circuit prevention function
CN202110620907.8A CN113451226B (en) 2019-03-06 2019-03-06 Heat-resistant QFN (quad Flat No lead) packaging semiconductor device
CN202110620909.7A CN113451227B (en) 2019-03-06 2019-03-06 High-reliability QFN (quad Flat No lead) packaging device structure
CN202110620908.2A CN113451235B (en) 2019-03-06 2019-03-06 QFN (quad Flat No lead) packaged semiconductor device

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CN202110620909.7A Division CN113451227B (en) 2019-03-06 2019-03-06 High-reliability QFN (quad Flat No lead) packaging device structure
CN202110620908.2A Division CN113451235B (en) 2019-03-06 2019-03-06 QFN (quad Flat No lead) packaged semiconductor device
CN202110621536.5A Division CN113451228B (en) 2019-03-06 2019-03-06 High-strength QFN (quad Flat No lead) packaging structure

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CN202110620907.8A Active CN113451226B (en) 2019-03-06 2019-03-06 Heat-resistant QFN (quad Flat No lead) packaging semiconductor device
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