CN112382614B - Power semiconductor device and method for manufacturing the same - Google Patents
Power semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112382614B CN112382614B CN202011271887.XA CN202011271887A CN112382614B CN 112382614 B CN112382614 B CN 112382614B CN 202011271887 A CN202011271887 A CN 202011271887A CN 112382614 B CN112382614 B CN 112382614B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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Abstract
The invention provides a power semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the power semiconductor device comprises the following steps: forming a first groove in the substrate of the cellular region and a second groove in the substrate of the terminal voltage-resisting region; forming a first dielectric layer to cover the inner walls of the first groove and the second groove and the top surface of the substrate; filling the first conductive layer in the first trench and the second trench; removing at least the first dielectric layer on the top surface of the substrate in the cellular area, and reserving the first dielectric layer on the top surface of the substrate in the terminal voltage-resisting area; and at least using the first dielectric layer on the terminal voltage-resistant area as a mask to execute an ion implantation process so as to form a body area in the substrate of the cellular area. According to the technical scheme, the process step of blocking the terminal pressure-resistant area by adopting the photoresist can be saved, and the electric field concentration difference between the terminal pressure-resistant area and the cellular area can be increased, so that the cost is saved, and the breakdown point can be ensured to be positioned in the cellular area.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a manufacturing method thereof.
Background
For a high-voltage power device, in order to ensure that a breakdown point is in internal breakdown (that is, the breakdown point is located in the cell region), it is necessary to increase the surface lateral distance of a voltage-withstanding ring in the terminal voltage-withstanding region and/or increase the electric field concentration difference between the terminal voltage-withstanding region and the cell region (the electric field concentration of the cell region is greater than that of the terminal voltage-withstanding region). Since increasing the surface lateral distance of the voltage-withstanding ring in the terminal voltage-withstanding region requires more voltage-withstanding rings, which may result in an increase in the size of the device and affect the performance of the device, a method of increasing the electric field concentration difference between the terminal voltage-withstanding region and the cell region is generally used. Then, in order to increase the electric field concentration difference between the terminal voltage-withstanding region and the cell region, a process of blocking the terminal voltage-withstanding region by using a photoresist needs to be added before the ion implantation of the cell region in the body region, and the added process steps can increase the cost.
Therefore, how to save the process step of blocking the terminal voltage-resistant region by using photoresist and increase the electric field concentration difference between the terminal voltage-resistant region and the cellular region, thereby ensuring that the breakdown point is located in the cellular region is a problem which needs to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a power semiconductor device and a manufacturing method thereof, which can save the process step of blocking a terminal voltage-resistant area by adopting photoresist, increase the electric field concentration difference between the terminal voltage-resistant area and a cellular area, further save the cost and ensure that a breakdown point is positioned in the cellular area.
In order to achieve the above object, the present invention provides a method of manufacturing a power semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a cellular area and a terminal voltage-resisting area;
forming a first groove in the substrate of the cellular region, and forming a second groove in the substrate of the terminal voltage-resisting region;
forming a first dielectric layer which covers the inner walls of the first trench and the second trench and also covers the top surface of the substrate;
filling a first conductive layer in the first trench and the second trench, wherein the top position of the first conductive layer is not lower than that of the first trench;
removing at least the first dielectric layer on the top surface of the substrate of the cellular area, and reserving the first dielectric layer on the top surface of the substrate of the terminal voltage-resisting area; and the number of the first and second groups,
and performing an ion implantation process by using at least the first dielectric layer on the terminal voltage-withstanding region as a mask to form a body region in the substrate of the cellular region.
Optionally, the step of removing at least the first dielectric layer on the top surface of the substrate in the cell region includes:
forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer covers the terminal voltage-resistant region and exposes the cell region;
etching the first dielectric layer by taking the patterned photoresist layer as a mask so as to remove the part of the first dielectric layer, which is positioned on the top surface of the substrate of the cellular area; and the number of the first and second groups,
and removing the patterned photoresist layer.
Optionally, when the first dielectric layer is etched, a part of the first dielectric layer in the first trench is also partially removed, so that the top of the first conductive layer protrudes out of the remaining first dielectric layer, and a gap is formed between the protruding top of the first conductive layer and the sidewall of the first trench;
and, before performing the ion implantation process, further comprising:
performing a thermal oxidation process to oxidize the top of the protrusion in the first conductive layer to form an isolation oxide layer, wherein the first conductive layer under the isolation oxide layer forms a shielding electrode of the transistor unit;
forming a second conductive layer in the void of the first trench to constitute a gate electrode of a transistor cell.
Optionally, the thermal oxidation process further includes: and oxidizing the side wall of the first groove exposed in the gap to form a second dielectric layer, wherein the thickness of the second dielectric layer is smaller than that of the first dielectric layer.
Optionally, when the first dielectric layer is etched, a part of the first dielectric layer and a part of the first conductive layer in the first trench are also removed, and the remaining first conductive layer forms a shielding electrode of the transistor unit;
and, before performing the ion implantation process, further comprising: and sequentially forming an isolation layer and a gate electrode in the first trench.
Optionally, the method for forming the first trench and the second trench includes: forming a patterned mask layer on the substrate, and etching the substrate by taking the mask layer as a mask to form the first trench and the second trench;
and the first dielectric layer also covers the top surface of the mask layer on the terminal pressure-resistant area, and when the ion implantation process is executed, the ion implantation process is executed on the terminal pressure-resistant area by using the first dielectric layer and the mask layer as masks.
The present invention also provides a power semiconductor device comprising:
the device comprises a substrate, a first voltage-withstanding region, a second voltage-withstanding region and a first voltage-withstanding region, wherein the substrate is provided with a cellular region and a terminal voltage-withstanding region;
the first dielectric layer is formed on the inner walls of the first groove and the second groove and also covers the top surface of the substrate of the terminal voltage-proof area;
the first conductive layer is filled in the first trench and the second trench, wherein the first conductive layer in the first trench is used for forming a shielding electrode of a transistor unit, and the first conductive layer in the second trench is used for forming a voltage-resistant ring of a terminal structure;
and the body region is formed in the substrate at the side of the first groove.
Optionally, in the cellular region, the top positions of the first dielectric layer and the shielding electrode are lower than the top position of the first trench, and an isolation oxide layer is formed on the shielding electrode in an aligned manner;
and, the power semiconductor device further includes:
the second dielectric layer is formed on the side wall of the first groove, which is higher than the first dielectric layer, of the first groove, and the thickness of the second dielectric layer is smaller than that of the first dielectric layer;
and the gate electrode is formed in a gap between the isolation oxide layer and the side wall of the first groove.
Optionally, in the cell region, the top positions of the first dielectric layer and the shielding electrode are lower than the top position of the first trench;
and, the power semiconductor device further includes:
an isolation layer formed on the shielding electrode to cover the shielding electrode;
the second dielectric layer is formed on the side wall of the first groove, higher than the isolation layer, of the first groove, and the thickness of the second dielectric layer is smaller than that of the first dielectric layer;
and a gate electrode formed over the isolation layer.
Optionally, the power semiconductor device further includes: and the third dielectric layer is formed between the first dielectric layer on the top surface of the substrate of the terminal voltage-resistant area and the substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the power semiconductor device, the first dielectric layer on the top surface of the substrate of the cellular area is at least removed, the first dielectric layer on the top surface of the substrate of the terminal pressure-resistant area is at least used as a mask, an ion implantation process is executed, and a body area is formed in the substrate of the cellular area, so that the process step of blocking the terminal pressure-resistant area by photoresist is saved, the electric field concentration difference between the terminal pressure-resistant area and the cellular area can be increased, the cost is saved, and the breakdown point can be ensured to be positioned in the cellular area.
2. The power semiconductor device comprises a first dielectric layer formed on the top surface of a substrate of a terminal voltage-proof area; and the body region is formed in the substrate of the cellular region, so that the electric field concentration difference between the terminal voltage-resisting region and the cellular region can be increased, and the breakdown point is ensured to be positioned in the cellular region.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a power semiconductor device according to an embodiment of the present invention;
fig. 2 to 12 are device schematic diagrams of a first embodiment in the manufacturing method of the power semiconductor device shown in fig. 1;
fig. 13 to 17 are device schematic views of a second embodiment in the method of manufacturing the power semiconductor device shown in fig. 1;
fig. 18 is a device schematic view of a third embodiment in the manufacturing method of the power semiconductor device shown in fig. 1;
fig. 19 is a device schematic view of a fourth embodiment in the manufacturing method of the power semiconductor device shown in fig. 1;
fig. 20 is a trend graph of the variation of the leakage current of the power semiconductor device formed by injecting the body region into both the cell region and the termination voltage-withstanding region and injecting the body region into only the cell region.
Wherein the reference numerals of figures 1 to 20 are as follows:
10-a substrate; 101-a first trench; 102-a second trench; 103-a first void; 104-a second void; 11-a first dielectric layer; 12-a first conductive layer; 121-isolation oxide layer; 122. 123-shield electrodes; 13-a patterned photoresist layer; 14-a second conductive layer; 141. 142-a gate electrode; 143-a spacer layer; 15-a second dielectric layer; 16-a mask layer; 161-a first oxide layer; 162-a second oxide layer; 17-a pressure ring; 18-body region.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the power semiconductor device and the method for manufacturing the same proposed by the present invention are described in further detail below. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a power semiconductor device, and referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention, where the method for manufacturing a power semiconductor device includes:
step S1, providing a substrate, wherein the substrate is provided with a cellular area and a terminal voltage-proof area;
step S2, forming a first trench in the substrate of the cell region, and forming a second trench in the substrate of the terminal voltage-withstanding region;
step S3, forming a first dielectric layer covering the inner walls of the first trench and the second trench and also covering the top surface of the substrate;
step S4, filling a first conductive layer in the first trench and the second trench, wherein the top position of the first conductive layer is not lower than the top position of the first trench;
step S5, removing at least the first dielectric layer on the top surface of the substrate in the cell area, and reserving the first dielectric layer on the top surface of the substrate in the terminal voltage-proof area;
step S6, at least using the first dielectric layer on the terminal voltage-withstanding region as a mask, performing an ion implantation process to form a body region in the substrate of the cell region.
The method for manufacturing the power semiconductor device according to the present embodiment is described in more detail with reference to fig. 2 to 19, fig. 2 to 19 are device diagrams in the method for manufacturing the power semiconductor device shown in fig. 1, and fig. 2 to 19 are longitudinal cross-sectional diagrams of the power semiconductor device.
According to step S1, a substrate 10 is provided, the substrate 10 having a cell region a1 and a terminal voltage-withstanding region a 2. The terminal pressure-resistant area A2 surrounds a cellular array composed of a plurality of cellular areas A1.
The material of the substrate 10 may be any suitable material known to those skilled in the art, such as monocrystalline silicon, silicon germanium, silicon carbide, and the like.
In step S2, a first trench 101 is formed in the substrate 10 of the cell region a1, and a second trench 102 is formed in the substrate 10 of the termination voltage withstanding region a 2.
The method for forming the first trench 101 and the second trench 102 includes: forming a patterned mask layer 16 on the substrate 10, and etching the substrate 10 by using the mask layer 16 as a mask to form the first trench 101 and the second trench 102. The mask layer 16 may have a single layer structure or at least a two-layer structure, for example, the mask layer 16 shown in fig. 2 includes a first oxide layer 161 and a second oxide layer 162 sequentially covering the substrate 10. The first oxide layer 161 may be formed by a thermal oxidation process, the second oxide layer 162 may be formed by a deposition process, and the first oxide layer 161 and the second oxide layer 162 may have a desired thickness by adjusting process parameters.
In addition, after the first trench 101 and the second trench 102 are formed, the mask layer 16 on the substrate 10 at the periphery of the first trench 101 and the second trench 102 may be continuously remained or the mask layer 16 may be removed. Fig. 3 to 17 show an embodiment in which the mask layer 16 is removed, and fig. 18 to 19 show an embodiment in which the mask layer 16 is left.
Taking the mask layer 16 as an example, after sequentially covering the first oxide layer 161 and the second oxide layer 162 on the top surface of the substrate 10, referring to fig. 2 and 3, the step of forming the first trench 101 and the second trench 102 includes: firstly, as shown in fig. 2, sequentially etching the second oxide layer 162, the first oxide layer 161, and a part of the thickness of the substrate 10 to form a first trench 101 and a second trench 102, where the first trench 101 and the second trench 102 both penetrate through the second oxide layer 162 and the first oxide layer 161 and extend into the part of the thickness of the substrate 10, the second trench 102 in the termination voltage-withstanding region a2 surrounds the first trench 101 in the cellular array, and the second oxide layer 162 and the first oxide layer 161 are used to protect the top surface of the substrate 10 where the first trench 101 and the second trench 102 are not formed during etching; next, as shown in fig. 3, the remaining second oxide layer 162 and the first oxide layer 161 are removed.
A first trench 101 or a second trench 102 may be formed at a boundary between the cell region a1 and the terminal voltage-withstanding region a2, or a first trench 101 and a second trench 102 are respectively formed on two sides of a boundary between the cell region a1 and the terminal voltage-withstanding region a 2. In the embodiments shown in fig. 2 to 19, a side wall of the second trench 102 closest to the cell region a1 in the terminal voltage-resisting region a2, which faces the cell region a1 side, is located at a boundary between the cell region a1 and the terminal voltage-resisting region a 2.
According to step S3, a first dielectric layer 11 is formed, where the first dielectric layer 11 covers the inner walls of the first trench 101 and the second trench 102, and also covers the top surface of the substrate 10. The material of the first dielectric layer 11 may be an insulating material such as silicon oxide or silicon oxynitride.
After the first trench 101 and the second trench 102 are formed, if the mask layer 16 on the substrate 10 at the periphery of the first trench 101 and the second trench 102 is continuously remained, the mask layer 16 is still sandwiched between the first dielectric layer 11 on the top surface of the substrate 10 and the substrate 10; after the first trench 101 and the second trench 102 are formed, if the mask layer 16 is removed, as shown in fig. 4, the bottom surface of the first dielectric layer 11 on the top surface of the substrate 10 is directly contacted with the top surface of the substrate 10.
According to step S4, a first conductive layer 12 is filled in the first trench 101 and the second trench 102, and the top position of the first conductive layer 12 is not lower than the top position of the first trench 101. The first conductive layer 12 may be made of polysilicon, which is used for forming a shielding electrode later.
The step of forming the first conductive layer 12 may include: as shown in fig. 5, filling a material of a first conductive layer 12 in the first trench 101 and the second trench 102, the material of the first conductive layer 12 filling the first trench 101 and the second trench 102 and burying the first dielectric layer 11 therein, and planarizing the material of the first conductive layer 12 by using a chemical mechanical polishing process until the top surface of the first dielectric layer 11 on the top surface of the substrate 10 is exposed; then, as shown in fig. 6, a part of the material of the first conductive layer 12 is removed until the top surface of the first conductive layer 12 is formed to be flush with the top surface of the substrate 10.
According to step S5, at least the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 is removed, and the first dielectric layer 11 on the top surface of the substrate 10 of the termination voltage withstand region a2 is remained.
Wherein, after the first trench 101 and the second trench 102 are formed, if the mask layer 16 on the substrate 10 at the periphery of the first trench 101 and the second trench 102 is continuously remained, when at least the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 is removed, the mask layer 16 between the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 and the substrate 10 is also removed; after the first trench 101 and the second trench 102 are formed, if the mask layer 16 is removed, only the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 is removed.
Next, taking the removal of the mask layer 16 after the formation of the first trench 101 and the second trench 102 as an example, the step of removing at least the first dielectric layer 11 on the top surface of the substrate 10 in the cell region a1 will be described, which includes the steps of:
firstly, a patterned photoresist layer 13 is formed on the substrate 10, where the patterned photoresist layer 13 covers at least the first dielectric layer 11 on the substrate 10 of the terminal voltage-withstanding region a2, that is, the patterned photoresist layer 13 may only cover the first dielectric layer 11 on the substrate 10 of the terminal voltage-withstanding region a2, and the patterned photoresist layer 13 may also cover the first dielectric layer 11 on the substrate 10 of the terminal voltage-withstanding region a2 and the first dielectric layer 11 and the first conductive layer 12 in the second trench 102 of part or all of the terminal voltage-withstanding region a 2; the patterned photoresist layer 13 shown in fig. 7 covers the first dielectric layer 11 on the substrate 10 of the terminal voltage-withstanding region a2, part of the first dielectric layer 11 and part of the first conductive layer 12 in the second trench 102 closest to the cell region a1 in the terminal voltage-withstanding region a2, and the first dielectric layer 11 and the first conductive layer 12 in all other second trenches 102 in the terminal voltage-withstanding region a 2; wherein, the step of forming the patterned photoresist layer 13 on the substrate 10 is an existing process for manufacturing a power semiconductor device (for forming a gate electrode later), and only the coverage of the patterned photoresist layer 13 is adjusted in the present invention, so that the first dielectric layer 11 on the top surface of the substrate 10 of the terminal voltage-resisting region a2 can be covered;
then, using the patterned photoresist layer 13 as a mask, removing the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 exposed by the patterned photoresist layer 13 and the first dielectric layer 11 in the first trench 101 of the cell region a1 with a partial height, as shown in fig. 8, so that the top of the first conductive layer 12 in the first trench 101 protrudes from the remaining first dielectric layer 11, and a gap (defined as a first gap 103) is formed between the protruding top of the first conductive layer 12 and the sidewall of the first trench 101; alternatively, as shown in fig. 13, using the patterned photoresist layer 13 as a mask, removing the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 exposed by the patterned photoresist layer 13, and the first dielectric layer 11 with a partial height and the first conductive layer 12 with a partial height in the first trench 101 of the cell region a1, wherein the remaining first conductive layer 12 in the first trench 101 constitutes a shielding electrode of a transistor cell;
in the embodiment shown in fig. 8, the first dielectric layer 11 with a partial height of another portion in the second trench 102 closest to the cell region a1 in the terminal voltage-proof region a2 exposed by the patterned photoresist layer 13 is also removed, so as to form a second gap 104 (for distinguishing from the first gap 103 in the cell region a 1) between the sidewall of the second trench 102 closest to the cell region a1 in the terminal voltage-proof region a2 and the first conductive layer 12; in the embodiment shown in FIG. 13, the first dielectric layer 11 and the first conductive layer 12 in the terminal voltage-withstanding region A2, which are exposed by the patterned photoresist layer 13 and are closest to another portion of the height in the second trench 102 of the cell region A1, are also removed;
in addition, in order to avoid the occurrence of lateral etching in the process of removing the above layers exposed by the patterned photoresist layer 13, dry etching may be used to remove the above layers exposed by the patterned photoresist layer 13;
next, the patterned photoresist layer 13 is removed, as shown in fig. 9 and 14.
In addition, after removing at least the first dielectric layer 11 on the top surface of the substrate 10 in the cell region a1 and before performing the ion implantation process subsequently, the method for manufacturing a power semiconductor device further includes:
as shown in fig. 10, performing a thermal oxidation process to oxidize the top of the protrusion in the first conductive layer 12 in the first trench 101 to form an isolation oxide layer 121, where a bottom surface of the isolation oxide layer 121 is lower than a top surface of the remaining first dielectric layer 11 in the first trench 101, and a top surface of the isolation oxide layer 121 is higher than a top surface of the substrate 10; and further comprising in the thermal oxidation process: oxidizing the side wall of the first trench 101 exposed in the first gap 103 to form a second dielectric layer 15, wherein the thickness of the second dielectric layer 15 is smaller than that of the first dielectric layer 11; meanwhile, the top surface of the substrate 10 of the cell region a1, the sidewalls of the second gap 104 and the top surface of the first conductive layer 12 in the second trench 102 are also thermally oxidized, i.e., the second dielectric layer 15 is also formed on the top surface of the substrate 10 of the cell region a1, the sidewalls of the second gap 104 and the top surface of the first conductive layer 12 in the second trench 102;
as shown in fig. 11, a second conductive layer 14 is formed in the first gap 103 of the first trench 101, and the second conductive layer 14 is also filled in the second gap 104.
As shown in fig. 12, the second conductive layer 14 in the first gap 103 forms a gate electrode 141 of a transistor unit, the first conductive layer 12 located below the isolation oxide layer 121 forms a shield electrode 122 of the transistor unit, the gate electrode 141 and the shield electrode 122 are isolated by the isolation oxide layer 121, and the gate electrodes 141 on both sides of the isolation oxide layer 121 share the lower shield electrode 122; the first conductive layer 12 in the second trench 102 is used to form a voltage ring 17 of the termination structure.
Alternatively, after removing at least the first dielectric layer 11 on the top surface of the substrate 10 in the cell region a1 and before performing the ion implantation process subsequently, the method for manufacturing a power semiconductor device further includes: an isolation layer 143, a second dielectric layer 15 and a gate electrode 142 are sequentially formed in the first trench 101. Specifically, as shown in fig. 15, a deposition process and an etching process may be first employed to form the isolation layer 143, the isolation layer 143 may cover the remaining first dielectric layer 11 and the remaining first conductive layer 12 in the first trench 101, and the isolation layer 143 may also cover a top surface of the first conductive layer 12 in the second trench 102 and a top surface of the remaining first dielectric layer 11 and the first conductive layer 12 in the second trench 102 closest to the cell region a1 in the terminal voltage-withstanding region a 2; then, as shown in fig. 15, a thermal oxidation process is performed to form a second dielectric layer 15 on the sidewall of the first trench 101 higher than the isolation layer 143 in the first trench 101, where the second dielectric layer 15 may also be formed on the top surface of the substrate 10 in the cell region a1, the sidewall of the second trench 102 closest to the cell region a1 in the termination voltage-withstanding region a2, and the sidewall of the first conductive layer 12 therein, and the thickness of the second dielectric layer 15 is smaller than the thickness of the first dielectric layer 11; then, as shown in fig. 16, the first trench 101 is filled with a second conductive layer 14, and at the same time, the second conductive layer 14 is also filled in the second trench 102 closest to the cell region a1 in the termination voltage-withstanding region a 2.
As shown in fig. 17, the second conductive layer 14 in the first trench 101 constitutes a gate electrode 142 of a transistor unit, and the remaining first conductive layer 12 in the first trench 101 constitutes a shield electrode 123 of the transistor unit, and the gate electrode 142 and the shield electrode 123 are isolated by the isolation layer 143; the first conductive layer 12 in the second trench 102 is used to form a voltage ring 17 of the termination structure.
In the above embodiment, which takes the removal of the mask layer 16 as an example, and describes the step of removing at least the first dielectric layer 11 on the top surface of the substrate 10 in the cell region a1, the thickness of the second dielectric layer 15 on the top surface of the substrate 10 in the cell region a1 is smaller than the thickness of the first dielectric layer 11 on the top surface of the substrate 10 in the terminal voltage-withstanding region a 2; then, if the mask layer 16 on the substrate 10 at the periphery of the first trench 101 and the second trench 102 is continuously remained after the first trench 101 and the second trench 102 are formed, the thickness of the second dielectric layer 15 on the top surface of the substrate 10 of the cell region a1 is smaller than the sum of the thicknesses of the first dielectric layer 11 and the first mask layer 16 on the top surface of the substrate 10 of the terminal voltage-withstanding region a 2. The thickness of the first dielectric layer 11 on the top surface of the substrate 10 in the termination voltage withstanding region a2 may be greater than
Then, the sum of the thicknesses of the first dielectric layer 11 and the mask layer 16 on the top surface of the substrate 10 in the termination voltage withstanding region a2 is also larger than
(ii) a The thickness of the second dielectric layer 15 on the top surface of the substrate 10 of the cell region a1 may be
。
According to step S6, an ion implantation process is performed with at least the first dielectric layer 11 on the termination voltage withstanding region a2 as a mask to form a body region 18 in the substrate 10 of the cell region a 1. Ions are also implanted into the gate and shield electrodes in the cell area a1 and the voltage ring 17 in the termination voltage region a 2.
If the mask layer 16 on the substrate 10 at the periphery of the first trench 101 and the second trench 102 is continuously remained after the first trench 101 and the second trench 102 are formed, when the ion implantation process is performed, the ion implantation process is performed on the terminal pressure-resistant region a2 by using the first dielectric layer 11 and the mask layer 16 as masks, as shown in fig. 18 and 19, and using the first dielectric layer 11, the second oxide layer 162, and the first oxide layer 161 on the top surface of the substrate 10 in the terminal pressure-resistant region a2 as masks; if the mask layer 16 is removed after the first trench 101 and the second trench 102 are formed, the ion implantation process is performed only with the first dielectric layer 11 on the top surface of the substrate 10 in the termination voltage withstanding region a2 as a mask, as shown in fig. 12 and 17.
Moreover, since the thickness of the second dielectric layer 15 on the top surface of the substrate 10 in the cell area a1 is smaller than the thickness of the first dielectric layer 11 on the top surface of the substrate 10 in the terminal voltage-withstanding area a2, the second dielectric layer 15 on the top surface of the substrate 10 in the cell area a1 cannot block ions from being implanted into the substrate 10 in the cell area a1 when the ion implantation process is performed.
From the foregoing steps S1 to S6, it can be known that, since the first dielectric layer 11 on the top surface of the substrate 10 of the cell region a1 is removed (or both the first dielectric layer 11 and the mask layer 16 are removed), and the first dielectric layer 11 on the top surface of the substrate 10 of the terminal voltage-withstanding region a2 is reserved (or both the first dielectric layer 11 and the mask layer 16 are reserved), and the thickness of the first dielectric layer 11 is sufficiently thick, when the ion implantation process is performed, the first dielectric layer 11 (or both the first dielectric layer 11 and the mask layer 16) on the top surface of the substrate 10 of the terminal voltage-withstanding region a2 can block ions from being implanted into the substrate 10 of the terminal voltage-withstanding region a2, and ions are only implanted into the substrate 10 of the cell region a1, so that the electric field concentration in the cell region a1 is greater than the electric field concentration in the terminal voltage-withstanding region a2, and a junction of the electric field strength between the cell region a1 and the terminal voltage-withstanding region a2 occurs, therefore, the breakdown point is ensured to be positioned in the cell area A1 with higher electric field intensity, the effect is realized without a process (photoetching) of covering photoresist to block the terminal voltage-resisting area A2, the formed photoresist needs to be removed in a subsequent process, and the first dielectric layer 11 (or the first dielectric layer 11 and the mask layer 16) on the top surface of the substrate 10 of the terminal voltage-resisting area A2 can be reserved for continuous use, so that the cost is reduced.
Referring to fig. 20, the abscissa is a test voltage (unit: V), the ordinate is a leakage current (unit: a), a curve L1 is a variation trend diagram of the leakage current of the power semiconductor device formed by performing ion implantation on both the cell region a1 and the terminal voltage-withstanding region a2 (i.e., the cell region a1 and the terminal voltage-withstanding region a2 have no structure for blocking ion implantation), a curve L2 is a variation trend diagram of the leakage current of the power semiconductor device formed by performing ion implantation only on the cell region a1 (i.e., the terminal voltage-withstanding region a2 has the first dielectric layer 11 for blocking ion implantation), and it can be seen from fig. 20 that the leakage current corresponding to the curve L2 is smaller than the leakage current corresponding to the curve L1, which indicates that the electric field concentration in the cell region a1 is greater than the electric field concentration in the terminal voltage-withstanding region a2, so that the leakage current is reduced, and it is ensured that the breakdown point is located in the cell region a 1.
In addition, after the body region 18 is formed in the substrate 10 of the cell region a1, the second dielectric layer 15 on the top surface of the substrate 10 of the cell region a1 may be removed, and a portion of the isolation oxide layer 121 higher than the substrate 10 may be removed.
In summary, the method for manufacturing a power semiconductor device provided by the present invention includes: providing a substrate, wherein the substrate is provided with a cellular area and a terminal voltage-resisting area; forming a first groove in the substrate of the cellular region, and forming a second groove in the substrate of the terminal voltage-resisting region; forming a first dielectric layer which covers the inner walls of the first trench and the second trench and also covers the top surface of the substrate; filling a first conductive layer in the first trench and the second trench, wherein the top position of the first conductive layer is not lower than that of the first trench; removing at least the first dielectric layer on the top surface of the substrate of the cellular region, and reserving the first dielectric layer on the top surface of the substrate of the terminal voltage-withstanding region; and at least using the first dielectric layer on the terminal voltage-resistant area as a mask to execute an ion implantation process so as to form a body area in the substrate of the cellular area. The manufacturing method of the power semiconductor device can save the process step of blocking the terminal voltage-resistant area by adopting photoresist, and can increase the electric field concentration difference between the terminal voltage-resistant area and the cellular area, thereby saving the cost and ensuring that a breakdown point is positioned in the cellular area.
An embodiment of the present invention provides a power semiconductor device, referring to fig. 12, fig. 17, fig. 18 and fig. 19, the power semiconductor device includes a substrate 10, a first dielectric layer 11, a first conductive layer 12 and a body region 18, the substrate 10 has a cell region a1 and a termination voltage-withstanding region a2, a first trench (i.e., the first trench 101 in fig. 3) is formed in the substrate 10 of the cell region a1, and a second trench (i.e., the second trench 102 in fig. 3) is formed in the substrate 10 of the termination voltage-withstanding region a 2; the first dielectric layer 11 is formed on the inner walls of the first trench 101 and the second trench 102 and also covers the top surface of the substrate 10 of the termination voltage-proof region a 2; the first conductive layer 12 is filled in the first trench 101 and the second trench 102, wherein the first conductive layer 12 located in the first trench 101 is used to form a shield electrode of a transistor cell, and the first conductive layer 12 located in the second trench 102 is used to form a voltage-withstanding ring of a terminal structure a 2; the body region 18 is formed in the substrate 10 at the side of the first trench 101.
The power semiconductor device of the present embodiment will be described in more detail with reference to fig. 12, 17, 18, and 19.
The substrate 10 has a cell area a1 and a terminal voltage-resistant area a2, and the terminal voltage-resistant area a2 surrounds a cell array formed by a plurality of cell areas a 1.
The material of the substrate 10 may be any suitable material known to those skilled in the art, such as monocrystalline silicon, silicon germanium, silicon carbide, and the like.
A first trench 101 is formed in the substrate 10 of the cell region a1, a second trench 102 is formed in the substrate 10 of the termination voltage-withstanding region a2, and the second trench 102 surrounds the first trench 101 in the cell array.
A first trench 101 or a second trench 102 may be formed at a boundary between the cell region a1 and the terminal voltage-withstanding region a2, or a first trench 101 and a second trench 102 are respectively formed at two sides of a boundary between the cell region a1 and the terminal voltage-withstanding region a 2. In the embodiment shown in fig. 12, 17, 18, and 19, the sidewall of the second trench 102 closest to the cell region a1 in the terminal voltage-withstanding region a2 facing the cell region a1 is located at the boundary between the cell region a1 and the terminal voltage-withstanding region a 2.
The first dielectric layer 11 is formed on the inner walls of the first trench 101 and the second trench 102, and the first dielectric layer 11 also covers the top surface of the substrate 10 of the termination voltage-withstanding region a2, i.e., the first dielectric layer 11 is not formed on the top surface of the substrate 10 of the cell region a 1.
The first conductive layer 12 is filled in the first trench 101 and the second trench 102, wherein the first conductive layer 12 located in the first trench 101 is used to form a shielding electrode (i.e., the shielding electrode 122 and the shielding electrode 123) of a transistor unit, and the first conductive layer 12 located in the second trench 102 is used to form a voltage-withstanding ring 17 of a termination structure. The material of the first conductive layer 12 may be polysilicon.
In the cell area a1, the top positions of the first dielectric layer 11 and the shielding electrode are lower than the top position of the first trench 101; in the termination voltage-proof region a2, the top positions of the first dielectric layer 11 and the voltage-proof ring 17 in the second trench 102 closest to the cell region a1 may be lower than the top position of the second trench 102.
As shown in fig. 12 and 18, an isolation oxide layer 121 is also formed on the shield electrode 122 in an aligned manner, a bottom surface of the isolation oxide layer 121 is lower than a top surface of the first dielectric layer 11 in the first trench 101, and a top surface of the isolation oxide layer 121 is higher than a top surface of the substrate 10. The power semiconductor device further comprises a second dielectric layer 15 and a gate electrode 141, wherein the second dielectric layer 15 is formed on the side wall of the first groove 101, which is higher than the first dielectric layer 11, of the first groove 101, and the thickness of the second dielectric layer 15 is smaller than that of the first dielectric layer 11; the second dielectric layer 15 can also be formed on the top surface of the substrate 10 in the cell region a1, the top of the first dielectric layer 11 and the pressure ring 17 in the second trench 102 closest to the cell region a1, and the top surfaces of the pressure rings 17 in the other second trenches 102; the gate electrode 141 is formed in a gap between the isolation oxide layer 121 and the sidewall of the first trench 101 (i.e., the first gap 103 in the above-mentioned method for manufacturing a power semiconductor device), the gate electrode 141 and the shielding electrode 122 are isolated by the isolation oxide layer 121, and the gate electrodes 141 on both sides of the isolation oxide layer 121 share the shielding electrode 122 below.
Alternatively, as shown in fig. 17 and fig. 19, the power semiconductor device further includes an isolation layer 143, a second dielectric layer 15, and a gate electrode 142, where the isolation layer 143 is formed on the shielding electrode 123 to cover the shielding electrode 123, and the isolation layer 143 may further cover the first dielectric layer 11 in the first trench 101; the second dielectric layer 15 is formed on the sidewall of the first trench 101 higher than the isolation layer 143 in the first trench 101, the second dielectric layer 15 may also be formed on the top surface of the substrate 10 in the cell region a1, and the sidewall of the second trench 102 closest to the cell region a1 in the termination voltage-resistant region a2 and the sidewall of the first conductive layer 12 therein, and the thickness of the second dielectric layer 15 is smaller than the thickness of the first dielectric layer 11; the gate electrode 142 is formed above the isolation layer 143, the gate electrode 142 and the shield electrode 123 are isolated by the isolation layer 143, and when the gate electrode 142 is formed, a material forming the gate electrode 142 may be further filled in the second trench 102 closest to the cell region a1 in the termination voltage-withstanding region a 2.
In addition, as shown in fig. 12 and 17, the first dielectric layer 11 may be directly formed on the top surface of the substrate 10 in the terminal voltage withstand region a2, i.e., the bottom surface of the first dielectric layer 11 located on the top surface of the substrate 10 in the terminal voltage withstand region a2 is directly in contact with the top surface of the substrate 10. Alternatively, the power semiconductor device may further include a third dielectric layer (i.e., the mask layer 16 in the manufacturing method of the power semiconductor device described above), which is formed between the first dielectric layer 11 on the top surface of the substrate 10 of the termination voltage-resisting region a2 and the substrate 10. The third dielectric layer may have a single-layer structure or at least a two-layer structure, for example, the third dielectric layer shown in fig. 18 and 19 includes a first oxide layer 161 and a second oxide layer 162 sequentially covering the substrate 10 of the termination voltage-withstanding region a 2.
If the power semiconductor device includes the third dielectric layer, as shown in fig. 18 and 19, the thickness of the second dielectric layer 15 on the top surface of the substrate 10 in the cell region a1 is smaller than the sum of the thicknesses of the first dielectric layer 11 and the third dielectric layer on the top surface of the substrate 10 in the terminal voltage-withstanding region a 2.
The thickness of the first dielectric layer 11 on the top surface of the substrate 10 in the termination voltage withstanding region a2 may be greater than
Then, the sum of the thicknesses of the first dielectric layer 11 and the third dielectric layer on the top surface of the substrate 10 in the termination voltage withstanding region a2 is also larger than
(ii) a The thickness of the second dielectric layer 15 on the top surface of the substrate 10 of the cell region a1 may be
。
The body region 18 is formed in the substrate 10 at the side of the first trench 101. If the third dielectric layer is not sandwiched between the first dielectric layer 11 on the top surface of the substrate 10 in the terminal voltage-withstanding region a2 and the substrate 10, as shown in fig. 12 and 17, an ion implantation process may be performed with the first dielectric layer 11 on the top surface of the substrate 10 in the terminal voltage-withstanding region a2 as a mask to form the body region 18 in the substrate 10 in the cell region a 1; if the third dielectric layer is sandwiched between the first dielectric layer 11 on the top surface of the substrate 10 in the terminal voltage-withstanding region a2 and the substrate 10, as shown in fig. 18 and 19, an ion implantation process may be performed with the first dielectric layer 11 and the third dielectric layer on the top surface of the substrate 10 in the terminal voltage-withstanding region a2 as masks, so as to form the body region 18 in the substrate 10 in the cell region a 1. Ions are also implanted into the gate and shield electrodes in the cell area a1 and the voltage ring 17 in the termination voltage region a 2.
Since the thickness of the second dielectric layer 15 on the top surface of the substrate 10 in the cell area a1 is smaller than the thickness of the first dielectric layer 11 on the top surface of the substrate 10 in the terminal voltage-withstanding area a2, when ion implantation is performed in the substrate 10, the second dielectric layer 15 on the top surface of the substrate 10 in the cell area a1 cannot block the ion implantation into the substrate 10 in the cell area a 1.
As can be seen from the above, since the first dielectric layer 11 is not formed on the top surface of the substrate 10 of the cellular region a1, and the first dielectric layer 11 (or the first dielectric layer 11 and the third dielectric layer) is formed on the top surface of the substrate 10 of the terminal voltage-withstanding region a2, and the thickness of the first dielectric layer 11 is thick enough, when an ion implantation process is performed, the first dielectric layer 11 (or the first dielectric layer 11 and the third dielectric layer) on the top surface of the substrate 10 of the terminal voltage-withstanding region a2 can block ions from being implanted into the substrate 10 of the terminal voltage-withstanding region a2, the body region 18 is only formed in the substrate 10 of the cellular region a1, so that the electric field concentration in the cellular region a1 is greater than the electric field concentration in the terminal voltage-withstanding region a2, and a sudden change occurs at the boundary between the cellular region a1 and the terminal voltage-withstanding region a2, thereby ensuring that the breakdown point is located in the cellular region a1 with higher electric field strength, the above effect is achieved without a process (photolithography) of covering photoresist to block the terminal voltage-resisting region a2, the formed photoresist needs to be removed in a subsequent process, and the first dielectric layer 11 (or the first dielectric layer 11 and the third dielectric layer) on the top surface of the substrate 10 of the terminal voltage-resisting region a2 can be retained for continuous use, so that the cost is reduced.
Referring to fig. 20, the abscissa is a test voltage, the ordinate is a leakage current, a curve L1 is a variation trend graph of a leakage current of a power semiconductor device formed by performing ion implantation on both the cell region a1 and the terminal voltage-withstanding region a2 (i.e., a structure in which no blocking ion implantation is formed on the cell region a1 and the terminal voltage-withstanding region a 2), and a curve L2 is a variation trend graph of a leakage current of a power semiconductor device formed by performing ion implantation only on the cell region a1 (i.e., the first dielectric layer 11 for blocking ion implantation is formed on the terminal voltage-withstanding region a 2), which can be seen from fig. 20 that the leakage current corresponding to the curve L2 is smaller than the leakage current corresponding to the curve L1, which indicates that the electric field concentration in the cell region a1 is greater than the electric field concentration in the terminal voltage-withstanding region a2, so that the leakage current is reduced, and that a breakdown point is located in the cell region a 1.
In summary, the power semiconductor device provided by the present invention includes: the device comprises a substrate, a first voltage-withstanding region, a second voltage-withstanding region and a first voltage-withstanding region, wherein the substrate is provided with a cellular region and a terminal voltage-withstanding region; the first dielectric layer is formed on the inner walls of the first groove and the second groove and also covers the top surface of the substrate of the terminal voltage-proof area; the first conducting layer is filled in the first trench and the second trench, wherein the first conducting layer in the first trench is used for forming a shielding electrode of a transistor unit, and the first conducting layer in the second trench is used for forming a voltage-resistant ring of a terminal structure; and the body region is formed in the substrate at the side of the first groove. The power semiconductor device provided by the invention can increase the electric field concentration difference between the terminal voltage-resistant area and the cellular area, thereby ensuring that the breakdown point is positioned in the cellular area.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. A method of manufacturing a power semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a cellular area and a terminal voltage-resisting area;
forming a first groove in the substrate of the cellular region, and forming a second groove in the substrate of the terminal voltage-resistant region; the method for forming the first trench and the second trench includes: forming a patterned mask layer on the substrate, and etching the substrate by taking the mask layer as a mask to form the first groove and the second groove;
forming a first dielectric layer covering inner walls of the first trench and the second trench and also covering a top surface of the mask layer;
filling a first conductive layer in the first trench and the second trench, wherein the top position of the first conductive layer is not lower than that of the first trench;
removing at least the first dielectric layer and the mask layer on the top surface of the substrate of the cellular region, and reserving the first dielectric layer and the mask layer on the top surface of the substrate of the terminal voltage-resisting region; and the number of the first and second groups,
and at least using the first dielectric layer on the terminal voltage-resisting area and the mask layer as masks to execute an ion implantation process so as to form a body area in the substrate of the cellular area.
2. The method of manufacturing a power semiconductor device according to claim 1, wherein the step of removing at least the first dielectric layer on the top surface of the substrate of the cell region comprises:
forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer covers the terminal voltage-resistant region and exposes the cell region;
etching the first dielectric layer by taking the patterned photoresist layer as a mask so as to remove the part of the first dielectric layer, which is positioned on the top surface of the substrate of the cellular area; and the number of the first and second groups,
and removing the patterned photoresist layer.
3. The method for manufacturing a power semiconductor device according to claim 2, wherein when the first dielectric layer is etched, a portion in the first trench is also partially removed, so that the top of the first conductive layer protrudes out of the remaining first dielectric layer, and a gap is formed between the protruded top of the first conductive layer and the sidewall of the first trench;
and, before performing the ion implantation process, further comprising:
performing a thermal oxidation process to oxidize the top of the protrusion in the first conductive layer to form an isolation oxide layer, wherein the first conductive layer under the isolation oxide layer forms a shielding electrode of the transistor unit;
forming a second conductive layer in the void of the first trench to constitute a gate electrode of a transistor cell.
4. The method for manufacturing a power semiconductor device according to claim 3, further comprising, in the thermal oxidation process: and oxidizing the side wall of the first trench exposed in the gap to form a second dielectric layer, wherein the thickness of the second dielectric layer is smaller than that of the first dielectric layer.
5. The method for manufacturing a power semiconductor device according to claim 2, wherein when the first dielectric layer is etched, a part of the first dielectric layer and a part of the first conductive layer in the first trench are also removed, and the remaining first conductive layer forms a shield electrode of the transistor unit;
and, before performing the ion implantation process, further comprising: and sequentially forming an isolation layer and a gate electrode in the first trench.
6. A power semiconductor device, comprising:
the device comprises a substrate, a first voltage-withstanding region, a second voltage-withstanding region and a first voltage-withstanding region, wherein the substrate is provided with a cellular region and a terminal voltage-withstanding region;
the first dielectric layer is formed on the inner walls of the first groove and the second groove and also covers the top surface of the substrate of the terminal voltage-resisting area, and a third dielectric layer is also formed between the first dielectric layer on the top surface of the substrate of the terminal voltage-resisting area and the substrate;
the first conducting layer is filled in the first trench and the second trench, wherein the first conducting layer in the first trench is used for forming a shielding electrode of a transistor unit, and the first conducting layer in the second trench is used for forming a voltage-resistant ring of a terminal structure; and the number of the first and second groups,
and the body region is formed in the substrate at the side of the first groove.
7. The power semiconductor device according to claim 6, wherein in the cell region, the top positions of the first dielectric layer and the shielding electrode are lower than the top position of the first trench, and an isolation oxide layer is formed on the shielding electrode in an aligned manner;
and, the power semiconductor device further includes:
the second dielectric layer is formed on the side wall of the first groove, which is higher than the first dielectric layer, of the first groove, and the thickness of the second dielectric layer is smaller than that of the first dielectric layer;
and the gate electrode is formed in a gap between the isolation oxide layer and the side wall of the first groove.
8. The power semiconductor device according to claim 6, wherein in the cell region, a top position of each of the first dielectric layer and the shield electrode is lower than a top position of the first trench;
and, the power semiconductor device further includes:
an isolation layer formed on the shielding electrode to cover the shielding electrode;
the second dielectric layer is formed on the side wall of the first groove, higher than the isolation layer, of the first groove, and the thickness of the second dielectric layer is smaller than that of the first dielectric layer;
and a gate electrode formed over the isolation layer.
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