CN113140615A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN113140615A
CN113140615A CN202110035225.0A CN202110035225A CN113140615A CN 113140615 A CN113140615 A CN 113140615A CN 202110035225 A CN202110035225 A CN 202110035225A CN 113140615 A CN113140615 A CN 113140615A
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diffusion layer
potential side
side circuit
type diffusion
circuit region
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CN113140615B (zh
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吉野学
清水和宏
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Mitsubishi Electric Corp
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Abstract

得到不会使高耐压分离区域和高耐压MOS的RESURF耐压降低，能够对高耐压分离区域和高耐压MOS之间的泄漏电流进行抑制的半导体装置。高耐压分离区域具有在半导体基板(8)的主面形成的第2导电型的第1扩散层(9)。高耐压MOS具有在半导体基板(8)的主面形成的第2导电型的第2扩散层(10)。低电位侧电路区域具有在半导体基板(8)的主面形成的第1导电型的第3扩散层(11)。在第1扩散层(9)和第2扩散层(10)之间露出的半导体基板(8)的主面形成有杂质浓度比半导体基板(8)高的第1导电型的第4扩散层(12)。第4扩散层(12)从高电位侧电路区域向低电位侧电路区域延伸，该第4扩散层没有与第3扩散层(11)接触。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
在构成半桥的功率芯片的驱动中使用HVIC(High Voltage IC)。HVIC具有：低电位侧电路区域，其以基板电位为基准；高电位侧电路区域，其被与基板高耐压地分离；以及电平移位电路，其进行低电位侧电路区域和高电位侧电路区域之间的信号传送。从低电位侧电路区域向高电位侧电路区域进行信号传送的电平移位电路通过高耐压MOS的接通/断开而在保持高耐压的同时进行信号传送。
高电位侧电路区域的外周被高耐压分离区域包围而与低电位侧电路区域分离。高耐压分离区域由RESURF分离构造形成。另外，高耐压MOS形成于与高耐压分离区域相同的RESURF分离构造内。高耐压分离区域的N型扩散层和高耐压MOS的N型扩散层通过在P型半导体基板的表面露出的狭缝状的分离部而彼此电分离(例如，参照专利文献1)。
分离部的杂质浓度设定为产生不使高耐压分离区域和高耐压MOS的RESURF耐压降低的程度的耗尽化。分离部的宽度设定为使得高耐压分离区域和高耐压MOS之间的击穿耐压大于或等于控制电路电源电压。
另外，如果由于配线层等的电位的影响使分离部的表面反转为N型而形成寄生沟道，则在高耐压分离区域和高耐压MOS之间流动泄漏电流。为了对其进行抑制，在分离部的表面形成有浓度高于P型半导体基板的P型扩散层。该P型扩散层在俯视观察时与低电位侧电路区域的P型层接触。
专利文献1：日本专利第3917211号公报
但是，如果将P型扩散层的杂质浓度增大到充分抑制寄生沟道的形成的程度，则高耐压分离区域和高耐压MOS的RESURF耐压降低。存在下述问题，即，如果设为RESURF耐压不降低的程度的浓度，则无法充分抑制寄生沟道的形成。
发明内容
本发明就是为了解决上述那样的课题而提出的，其目的在于得到不会使高耐压分离区域和高耐压MOS的RESURF耐压降低，能够对高耐压分离区域和高耐压MOS之间的泄漏电流进行抑制的半导体装置。
本发明涉及的半导体装置的特征在于具有：高电位侧电路区域；低电位侧电路区域；以及RESURF分离构造，其包围所述高电位侧电路区域的外周，使所述高电位侧电路区域和所述低电位侧电路区域分离，所述高电位侧电路区域、所述低电位侧电路区域及所述RESURF分离构造形成于第1导电型的单一的半导体基板，所述RESURF分离构造具有高耐压分离区域和高耐压MOS，所述高耐压分离区域具有在所述半导体基板的主面形成的第2导电型的第1扩散层，所述高耐压MOS具有在所述半导体基板的主面形成的第2导电型的第2扩散层，所述低电位侧电路区域具有在所述半导体基板的主面形成的第1导电型的第3扩散层，在所述第1扩散层和所述第2扩散层之间露出的所述半导体基板的主面形成有杂质浓度比所述半导体基板高的第1导电型的第4扩散层，所述第4扩散层从所述高电位侧电路区域向所述低电位侧电路区域延伸，该第4扩散层没有与所述第3扩散层接触。
发明的效果
在本发明中，高浓度的第4扩散层没有与低电位侧电路区域的第3扩散层接触。因此，低电位侧的半导体基板被耗尽，高电位侧的第4扩散层变得电浮动，由此能够对RESURF耐压的降低进行抑制。另外，通过在高耐压MOS和高耐压分离区域之间产生电位差的高电位侧形成高浓度的第4扩散层，从而能够对寄生沟道的形成进行抑制。因此，不会使高耐压分离区域和高耐压MOS的RESURF耐压降低，能够对高耐压分离区域和高耐压MOS之间的泄漏电流进行抑制。
附图说明
图1是表示实施方式1涉及的半导体装置的图。
图2是表示实施方式1涉及的电平移位电路的高耐压NchMOS的图。
图3是表示实施方式1涉及的半导体装置的俯视图。
图4是沿图3的A-A′的剖视图。
图5是沿图3的B-B′的剖视图。
图6是沿图3的C-C′的剖视图。
图7是沿图3的D-D′的剖视图。
图8是表示对比例涉及的半导体装置的俯视图。
图9是表示对比例涉及的半导体装置的高耐压分离区域和高耐压MOS的分离部的耗尽层的扩展的俯视图。
图10是沿图9的A-A′的剖视图。
图11是表示实施方式1涉及的半导体装置的高耐压分离区域和高耐压MOS的分离部的耗尽层的扩展的俯视图。
图12是沿图11的A-A′的剖视图。
图13是沿图11的B-B′的剖视图。
图14是表示实施方式2涉及的半导体装置的俯视图。
图15是表示实施方式2涉及的半导体装置的制造工序的俯视图。
图16是表示实施方式3涉及的半导体装置的俯视图。
图17是表示实施方式3涉及的半导体装置的制造工序的俯视图。
图18是表示实施方式4涉及的半导体装置的俯视图。
图19是表示实施方式4涉及的半导体装置的制造工序的俯视图。
图20是表示实施方式5涉及的半导体装置的制造工序的俯视图。
图21是表示实施方式6涉及的半导体装置的俯视图。
图22是表示实施方式7涉及的半导体装置的俯视图。
具体实施方式
参照附图对实施方式涉及的半导体装置进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1.
图1是表示实施方式1涉及的半导体装置的图。该半导体装置是对构成半桥的功率芯片1、2进行驱动的HVIC(High Voltage IC)3。HVIC 3具有：高电位侧电路区域4，其对功率芯片1进行驱动；低电位侧电路区域5，其对功率芯片2进行驱动；以及电平移位电路6，其进行低电位侧电路区域5和高电位侧电路区域4之间的信号传送。
图2是表示实施方式1涉及的电平移位电路的高耐压NchMOS的图。从低电位侧电路区域5向高电位侧电路区域4的信号传送由电平移位电路6的高耐压NchMOS 7进行。此外，从高电位侧电路区域4向低电位侧电路区域5的信号传送由高耐压PchMOS(未图示)进行。
图3是表示实施方式1涉及的半导体装置的俯视图。为了简便，仅图示出一部分结构。RESURF分离构造在俯视观察时包围高电位侧电路区域的外周，使高电位侧电路区域和低电位侧电路区域分离。RESURF分离构造具有高耐压分离区域和高耐压MOS。高耐压MOS可以是上述高耐压NchMOS 7和高耐压PchMOS的任意者。高电位侧电路区域、低电位侧电路区域及RESURF分离构造形成于单一的P型基板8。低电位侧电路区域以基板电位为基准，高耐压分离区域将高电位侧电路区域与基板电位高耐压地分离。高耐压MOS具有与高耐压分离区域等同的耐压。
高耐压分离区域具有在P型基板8的主面形成的N型扩散层9。N型扩散层9为RESURF区域。高耐压MOS具有在P型基板8的主面形成的N型扩散层10。低电位侧电路区域具有在P型基板8的主面形成的P型扩散层11。
P型基板8在N型扩散层9和N型扩散层10之间、高耐压MOS的N型扩散层10和高电位侧电路区域之间露出。通过该露出的P型基板8，高耐压MOS与高耐压分离区域及高电位侧电路区域电分离。另外，在露出的P型基板8的主面形成有杂质浓度比P型基板8高的P型扩散层12。P型扩散层12从高电位侧电路区域向低电位侧电路区域延伸，在高电位侧电路区域侧不间断地形成，在低电位侧具有未形成P型扩散层12的区域且P型扩散层12没有与P型扩散层11接触。低电位侧的未形成P型扩散层12的区域成为在将高电压施加于高电位侧电路区域时低电位侧的P型基板8耗尽的程度的距离。
图4是沿图3的A-A′的剖视图，示出高耐压MOS的剖面构造。高耐压MOS的N型扩散层10与高耐压分离区域的N型扩散层9电分离，该N型扩散层10与漏极漂移层对应。在N型扩散层10的表面形成有热氧化膜13。在P型扩散层11的表面的一部分形成有P+型扩散层14。在P型扩散层11和热氧化膜13之间的N型扩散层10的表面形成有P型扩散层15。在P型扩散层15的表面的一部分形成有N+型扩散层16。在P型扩散层15的表面的一部分形成有P+型扩散层17。
P型基板8在与N型扩散层10分离地形成于高电位侧电路区域的N型扩散层9和高耐压MOS的N型扩散层10之间露出，被热氧化膜18覆盖。在热氧化膜13和热氧化膜18之间，在N型扩散层10的表面形成有N+型扩散层19。在高电位侧电路区域的N型扩散层9的表面的一部分形成有N+型扩散层20。
以覆盖热氧化膜13的两端的方式彼此分离地形成有多晶硅21、22。多晶硅21还隔着栅极氧化膜形成于P型扩散层15之上。多个多晶硅23在多晶硅21、22之间彼此分离地形成于热氧化膜13之上，在俯视观察时包围高电位侧电路区域。而且，在其之上以覆盖半导体装置的方式形成有绝缘层24。
在绝缘层24之上形成有金属配线层25-29。金属配线层25通过形成于绝缘层24的接触孔而与P+型扩散层14电连接。金属配线层26通过形成于绝缘层24的接触孔而与P+型扩散层17和N+型扩散层16电连接。金属配线层27通过形成于绝缘层24的接触孔而与多晶硅21电连接。金属配线层28通过形成于绝缘层24的接触孔而与多晶硅22及N+型扩散层19电连接。金属配线层29通过形成于绝缘层24的接触孔而与N+型扩散层20电连接。
彼此分离而没有电连接的多个金属配线层30在金属配线层27和金属配线层28之间形成于绝缘层24之上，在俯视观察时包围高电位侧电路区域。多个金属配线层30以一定的宽度与多晶硅23重叠。由此，多晶硅23和金属配线层30经由绝缘层24电容耦合。
图5是沿图3的B-B′的剖视图，示出高耐压分离区域的剖面构造。N型扩散层9的杂质浓度比P型扩散层11低且比P型基板8高。N型扩散层9满足RESURF条件，浓度越低、厚度越薄则越会得到RESURF效果。在P型扩散层11的内侧以与P型扩散层11局部重叠的方式形成有P型扩散层31。在P型扩散层31的表面的一部分形成有P+型扩散层32。在与P型扩散层11分离开一定距离的N型扩散层9的表面形成有N+型扩散层33。N+型扩散层20和N+型扩散层33被电连接。
在P型扩散层11和N+型扩散层33之间的N型扩散层9的表面形成有热氧化膜13。以覆盖热氧化膜13的两端的方式彼此分离地形成有多晶硅34、35。多个多晶硅23在多晶硅34、35之间彼此分离地形成于热氧化膜13之上，在俯视观察时包围高电位侧电路区域。
在绝缘层24之上形成有金属配线层36、37。金属配线层36通过形成于绝缘层24的接触孔而与P+型扩散层32和多晶硅34电连接。金属配线层37通过形成于绝缘层24的接触孔而与N+型扩散层33和多晶硅35电连接。金属配线层25和金属配线层36被电连接。金属配线层29和金属配线层37被电连接。
图6是沿图3的C-C′的剖视图，示出低电位侧的高耐压MOS和高耐压分离区域的分离部的剖面构造。图7是沿图3的D-D′的剖视图，示出高电位侧的高耐压MOS和高耐压分离区域的分离部的剖面构造。它们都是穿过多晶硅23的剖视图。
P型基板8在N型扩散层9和N型扩散层10之间露出，该部分构成使N型扩散层9和N型扩散层10分离的分离部。在高电位侧，在该露出的P型基板8的主面形成有杂质浓度比P型基板8高的P型扩散层12。
接下来，与对比例进行比较而对本实施方式的效果进行说明。图8是表示对比例涉及的半导体装置的俯视图。在对比例中，P型扩散层12与P型扩散层11接触。
图9是表示对比例涉及的半导体装置的高耐压分离区域和高耐压MOS的分离部的耗尽层的扩展的俯视图。图10是沿图9的A-A′的剖视图。N+型扩散层19、20各自为用于实现N型扩散层10、9的高电位侧的接触的N型扩散层。将低电位侧电路区域的P型扩散层11的电位设为GND，向高电位侧电路区域的N+型扩散层19、20施加高电压。在该情况下，N+型扩散层10、9通过RESURF构造完全耗尽。耗尽层38从N型扩散层9和P型基板8的PN结界面及N型扩散层10和P型基板8的PN结界面扩展。两者夹断，P型基板8的耗尽层38向基板下表面扩展。
另一方面，P型扩散层12由于是高浓度而没有完全耗尽。特别地，由于在低电位侧施加于P型基板8和N型扩散层9、10之间的电压低，因此P型扩散层12成为更难以显著地耗尽的状态。在对比例中，P型扩散层12与电位为GND的P型扩散层11电连接并且没有被耗尽。因此，在高电位侧其电位也被固定为GND。
如果将P型扩散层12设为高耐压分离区域和高耐压MOS的RESURF耐压不降低的程度的浓度，则对寄生沟道的形成的抑制变得不充分。因此，为了对寄生沟道的形成进行抑制，必须使在P型基板8的上表面形成的热氧化膜13形成得厚。因此，需要高温、长时间的热处理，在热氧化膜13的边缘形成的鸟喙(birds beak)变长，因此难以实现布局的缩小。
由于N型扩散层9、10的高电位侧被施加高电压，因此在P型扩散层12和N型扩散层9、10之间产生高电位差。因此，在施加电压达到RESURF耐压前在P型扩散层12和P型基板8的界面处引起雪崩击穿而使耐压降低。
图11是表示实施方式1涉及的半导体装置的高耐压分离区域和高耐压MOS的分离部的耗尽层的扩展的俯视图。图12是沿图11的A-A′的剖视图。图13是沿图11的B-B′的剖视图。
N型扩散层9、10通过RESURF构造完全耗尽。在低电位侧，从与两侧的N型扩散层的PN结界面扩展的耗尽层38进行夹断，由此被N型扩散层9和N型扩散层10夹着的P型基板8的表面完全耗尽。
在高电位侧，高浓度的P型扩散层12没有完全耗尽。由于P型基板8在低电位侧完全耗尽，因此P型扩散层12的电位与GND电位的P型扩散层11分离而成为浮动状态。因此，P型扩散层12的电压与N型扩散层9、10一起升高为高电压。由此，在P型扩散层12和N型扩散层9、10之间没有产生高电位差，因此不会引起如对比例那样的雪崩击穿，能够得到高耐压。
另一方面，低电位侧被GND电位的P型扩散层11包围，N型扩散层9和N型扩散层10之间的电位差小。因此，即使在P型基板8的主面没有P型扩散层12，也能够对由寄生沟道引起的N型扩散层9和N型扩散层10之间的泄漏电流进行抑制。
如以上说明所述，在本实施方式中，高浓度的P型扩散层12没有与低电位侧电路区域的P型扩散层11接触。因此，低电位侧的P型基板8被耗尽，高电位侧的P型扩散层12变得电浮动，因此能够对RESURF耐压的降低进行抑制。另外，通过将高浓度的P型扩散层12形成于在高耐压MOS和高耐压分离区域之间产生电位差的高电位侧，从而能够对寄生沟道的形成进行抑制。因此，不会使高耐压分离区域和高耐压MOS的RESURF耐压降低，能够对高耐压分离区域和高耐压MOS之间的泄漏电流进行抑制。
此外，也可以在P型基板8之上形成P型外延层，以与P型外延层的下表面接触的方式形成N+型埋入扩散层。另外，也可以替代在热氧化膜13之上由多晶硅23和金属配线层30形成的电容耦合，作为将高电位侧电路区域的外周包围的漩涡状的电阻体而形成多晶硅。
实施方式2.
图14是表示实施方式2涉及的半导体装置的俯视图。P型扩散层39以在P型扩散层12的端部和P型扩散层11之间与P型扩散层12的端部接触的方式形成于P型基板8的主面。P型扩散层39的杂质浓度比P型扩散层12低且比P型基板8高。
图15是表示实施方式2涉及的半导体装置的制造工序的俯视图。通过与用于形成P型扩散层12的杂质注入相同的工序，从点状的注入窗口将杂质注入至P型基板8而形成点40。通过使该点40的杂质扩散而形成P型扩散层39。通过杂质从点状的小的注入窗口的扩散而使P型扩散层39成为低浓度。
通过形成浓度比P型扩散层12低的P型扩散层39，从而缓和P型扩散层12的端部的电场集中。由此，能够提高耐压降低的抑制的稳定性。
实施方式3.
图16是表示实施方式3涉及的半导体装置的俯视图。在实施方式2中P型扩散层39与低电位侧的P型扩散层11分离，但在本实施方式中P型扩散层39与低电位侧的P型扩散层11接触。
图17是表示实施方式3涉及的半导体装置的制造工序的俯视图。通过与用于形成P型扩散层12的杂质注入相同的工序，从配置为一列的点状的注入窗口将杂质注入至P型基板8而形成多个点40。通过使该点40的杂质扩散而形成P型扩散层39。通过杂质从点状的小的注入窗口的扩散而使P型扩散层39成为低浓度。
由于在将低电位侧电路区域的P型扩散层11的电位设为GND，将高电压施加于高电位侧电路区域的N+型扩散层19、20时，低浓度的P型扩散层39被耗尽，因此对耐压降低进行抑制。另外，由于浓度比P型基板8高的P型扩散层39与P型扩散层11接触，因此能够进一步对N型扩散层9和N型扩散层10之间的泄漏电流进行抑制。
实施方式4.
图18是表示实施方式4涉及的半导体装置的俯视图。在实施方式1中P型扩散层39的宽度与P型扩散层12的宽度相同，但在本实施方式中P型扩散层39的宽度比P型扩散层12的宽度宽。
图19是表示实施方式4涉及的半导体装置的制造工序的俯视图。通过与用于形成P型扩散层12的杂质注入相同的工序，从配置为多列的点状的注入窗口将杂质注入至P型基板8而形成多个点40。通过使该点40的杂质扩散而形成P型扩散层39。通过杂质从点状的小的注入窗口的扩散而使P型扩散层39成为低浓度。
由于在将低电位侧电路区域的P型扩散层11的电位设为GND，将高电压施加于高电位侧电路区域的N+型扩散层19、20时，低浓度的P型扩散层39被耗尽，因此对耐压降低进行抑制。另外，由于浓度比P型基板8高的P型扩散层39形成得宽，因此能够进一步对N型扩散层9和N型扩散层10之间的泄漏电流进行抑制。
实施方式5.
图20是表示实施方式5涉及的半导体装置的制造工序的俯视图。从多个点状的注入窗口将杂质注入至P型基板8而形成多个点40。通过使该点40的杂质扩散而形成P型扩散层39。
使点40的间隔S从高电位侧电路区域向低电位侧电路区域逐渐扩大。相邻的点40的间隔S越宽，则从相邻的点40扩散出的杂质的重叠越小。因此，P型扩散层39的杂质浓度从高电位侧电路区域向低电位侧电路区域逐渐变低。
在将低电位侧电路区域的P型扩散层11的电位设为GND，将高电压施加于高电位侧电路区域的N+型扩散层19、20时，施加于P型基板8和N型扩散层9、10之间的电位差从低电位侧向高电位侧逐渐变高。因此，P型基板8容易从低电位侧向高电位侧逐渐耗尽。另一方面，在向N+型扩散层19和N+型扩散层20之间施加了与控制电路电源电压相当的电位差的情况下，N型扩散层9和N型扩散层10之间的电位差从高电位侧向低电位侧逐渐变低。因此，由寄生沟道引起的泄漏电流从高电位侧向低电位侧逐渐变小。
相对于此，在本实施方式中，从高电位侧向低电位侧逐渐使P型扩散层39的杂质浓度降低。由此，能够在高电位侧和低电位侧之间的各位置处将P型扩散层39的浓度相对于耐压降低的抑制和由寄生沟道引起的泄漏电流的抑制这两者而设为最佳值。
此外，也可以使注入窗口的尺寸从高电位侧电路区域向低电位侧电路区域逐渐减小。通过使注入窗口减小，从而形成的扩散层的浓度变低。在该情况下，由于P型扩散层39的杂质浓度从高电位侧电路区域向低电位侧电路区域逐渐变低，因此也能够得到上述效果。
实施方式6.
图21是表示实施方式6涉及的半导体装置的俯视图。P型扩散层39的宽度从高电位侧电路区域向低电位侧电路区域逐渐变窄。由此，能够得到与实施方式5相同的效果。另外，能够通过比使用点状的注入窗口的情况简单的布局设计而实现。此外，也可以是P型扩散层39的低电位侧的端部为在将低电位侧电路区域的P型扩散层11的电位设为GND、将高电压施加于高电位侧电路区域的N+型扩散层19、20时耗尽的程度的宽度，与P型扩散层11接触。
实施方式7.
图22是表示实施方式7涉及的半导体装置的俯视图。在实施方式1中，在N型扩散层9和N型扩散层10之间露出的P型基板8的宽度是固定的。相对于此，在本实施方式中，该宽度从高电位侧电路区域向低电位侧电路区域逐渐变窄。如果将低电位侧的宽度设为WL，将高电位侧的宽度设为WH，则WL<WH。使需要耗尽的P型基板8的宽度向低电位侧电路区域变窄。由此，在将低电位侧电路区域的P型扩散层11的电位设为GND，将高电压施加于高电位侧电路区域的N+型扩散层19、20时，从P型基板8和N型扩散层9、10之间的PN结界面向P型基板8侧扩展的耗尽层容易夹断。因此，能够进一步对耐压降低进行抑制。
此外，P型基板8并不限于由硅形成，也可以由比硅带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料、或金刚石。由于由这样的宽带隙半导体形成的半导体装置的耐压性、允许电流密度高，因此能够小型化。通过使用该被小型化后的半导体装置，从而组装有该半导体芯片的半导体模块也能够被小型化、高集成化。另外，由于半导体装置的耐热性高，因此能够将散热器的散热片小型化，能够使水冷部空冷化，因此能够进一步将半导体模块小型化。另外，由于半导体装置的功率损耗低且高效，因此能够使半导体模块高效化。
标号的说明
8P型基板(半导体基板)，9N型扩散层(第1扩散层)，10N型扩散层(第2扩散层)，11P型扩散层(第3扩散层)，12P型扩散层(第4扩散层)，39P型扩散层(第5扩散层)

Claims (8)

1.一种半导体装置，其特征在于，具有：
高电位侧电路区域；
低电位侧电路区域；以及
RESURF分离构造，其包围所述高电位侧电路区域的外周，使所述高电位侧电路区域和所述低电位侧电路区域分离，
所述高电位侧电路区域、所述低电位侧电路区域及所述RESURF分离构造形成于第1导电型的单一的半导体基板，
所述RESURF分离构造具有高耐压分离区域和高耐压MOS，
所述高耐压分离区域具有在所述半导体基板的主面形成的第2导电型的第1扩散层，
所述高耐压MOS具有在所述半导体基板的主面形成的第2导电型的第2扩散层，
所述低电位侧电路区域具有在所述半导体基板的主面形成的第1导电型的第3扩散层，
在所述第1扩散层和所述第2扩散层之间露出的所述半导体基板的主面形成有杂质浓度比所述半导体基板高的第1导电型的第4扩散层，
所述第4扩散层从所述高电位侧电路区域向所述低电位侧电路区域延伸，该第4扩散层没有与所述第3扩散层接触。
2.根据权利要求1所述的半导体装置，其特征在于，
第1导电型的第5扩散层以在所述第4扩散层的端部和所述第3扩散层之间与所述第4扩散层的端部接触的方式形成于所述半导体基板的主面，
所述第5扩散层的杂质浓度比所述第4扩散层低且比所述半导体基板高。
3.根据权利要求2所述的半导体装置，其特征在于，
所述第5扩散层与所述第3扩散层接触。
4.根据权利要求2或3所述的半导体装置，其特征在于，
所述第5扩散层的宽度比所述第4扩散层的宽度宽。
5.根据权利要求2至4中任一项所述的半导体装置，其特征在于，
所述第5扩散层的杂质浓度从所述高电位侧电路区域向所述低电位侧电路区域逐渐变低。
6.根据权利要求1所述的半导体装置，其特征在于，
第1导电型的第5扩散层在所述第4扩散层的端部和所述第3扩散层之间形成于所述半导体基板的主面，
所述第5扩散层的宽度从所述高电位侧电路区域向所述低电位侧电路区域逐渐变窄。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
在所述第1扩散层和所述第2扩散层之间露出的所述半导体基板的宽度从所述高电位侧电路区域向所述低电位侧电路区域逐渐变窄。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，
所述半导体基板由宽带隙半导体形成。
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