CN112997272A - 外延层和3d nand存储器的形成方法、退火设备 - Google Patents

外延层和3d nand存储器的形成方法、退火设备 Download PDF

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CN112997272A
CN112997272A CN201880096615.5A CN201880096615A CN112997272A CN 112997272 A CN112997272 A CN 112997272A CN 201880096615 A CN201880096615 A CN 201880096615A CN 112997272 A CN112997272 A CN 112997272A
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annealing
silicon
forming
insulating layer
epitaxial layer
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CN112997272B (zh
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郭海峰
王孝进
朱宏斌
赖琳
程腾
肖莉红
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Yangtze Memory Technologies Co Ltd
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Abstract

一种外延层和3D NAND存储器的形成方法、退火设备，其中所述外延层的形成方法，先进行第一退火，以消除堆叠结构中产生的应力，在进行第一退火时，所述凹槽的侧壁和底部表面形成含硅的混合物，因而第一退火后，进行第二退火，进行第二退火，以去除所述凹槽侧壁和底部表面的含硅的混合物，使得后续在形成外延层时的生长界面为纯净的衬底材料界面，防止凹槽中形成的外延层中产生孔洞缺陷。

Description

PCT国内申请，说明书已公开。

Claims (23)

  1. PCT国内申请，权利要求书已公开。
CN201880096615.5A 2018-11-20 2018-11-20 外延层和3d nand存储器的形成方法、退火设备 Active CN112997272B (zh)

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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
CN111952317B (zh) * 2020-08-04 2024-04-09 长江存储科技有限责任公司 三维存储器及其制备方法
CN113228279B (zh) * 2021-03-31 2024-04-09 长江存储科技有限责任公司 用于形成半导体结构的方法
WO2023225199A1 (en) * 2022-05-18 2023-11-23 Applied Materials, Inc. Epitaxial silicon channel growth
US20230413569A1 (en) * 2022-05-18 2023-12-21 Applied Materials, Inc. Epitaxial silicon channel growth

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004770A1 (en) * 2007-06-26 2009-01-01 Dongbu Hitek Co., Ltd. Method for manufacturing vertical cmos image sensor
CN102800595A (zh) * 2011-05-26 2012-11-28 中芯国际集成电路制造(上海)有限公司 Nmos晶体管形成方法及对应cmos结构形成方法
CN103137462A (zh) * 2011-11-25 2013-06-05 中芯国际集成电路制造(上海)有限公司 自对准金属硅化物的形成方法
CN103498196A (zh) * 2008-09-29 2014-01-08 美格纳半导体有限会社 硅晶片的制造方法
CN107611130A (zh) * 2017-08-23 2018-01-19 长江存储科技有限责任公司 一种3d nand闪存结构中硅外延生长的工艺

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100784860B1 (ko) * 2005-10-31 2007-12-14 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
US10354995B2 (en) * 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US9536970B2 (en) * 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
CN104882374B (zh) * 2014-02-27 2018-03-06 旺宏电子股份有限公司 刻蚀方法与刻蚀组成物
KR102323571B1 (ko) * 2014-07-01 2021-11-09 삼성전자주식회사 반도체 장치 및 그 제조방법
JP2017055082A (ja) * 2015-09-11 2017-03-16 株式会社東芝 不揮発性記憶装置の製造方法
TWI570838B (zh) * 2015-11-12 2017-02-11 財團法人工業技術研究院 碳化矽基板上的溝槽結構以及其製作方法
JP2018006533A (ja) * 2016-06-30 2018-01-11 東京エレクトロン株式会社 真空処理装置、真空処理方法及び記憶媒体
TWI630709B (zh) * 2017-03-14 2018-07-21 旺宏電子股份有限公司 三維半導體元件及其製造方法
KR102333439B1 (ko) 2017-04-28 2021-12-03 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN108807410B (zh) * 2018-07-16 2021-02-05 长江存储科技有限责任公司 3d存储器件及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004770A1 (en) * 2007-06-26 2009-01-01 Dongbu Hitek Co., Ltd. Method for manufacturing vertical cmos image sensor
CN103498196A (zh) * 2008-09-29 2014-01-08 美格纳半导体有限会社 硅晶片的制造方法
CN102800595A (zh) * 2011-05-26 2012-11-28 中芯国际集成电路制造(上海)有限公司 Nmos晶体管形成方法及对应cmos结构形成方法
CN103137462A (zh) * 2011-11-25 2013-06-05 中芯国际集成电路制造(上海)有限公司 自对准金属硅化物的形成方法
CN107611130A (zh) * 2017-08-23 2018-01-19 长江存储科技有限责任公司 一种3d nand闪存结构中硅外延生长的工艺

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WO2020102990A1 (zh) 2020-05-28
TW202021099A (zh) 2020-06-01
TWI676273B (zh) 2019-11-01
US10741390B2 (en) 2020-08-11
TW202020931A (zh) 2020-06-01
TWI693628B (zh) 2020-05-11
CN112997272B (zh) 2024-03-29

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