CN112992834B - 一种源栅间接电连接的先进二极管封装结构 - Google Patents

一种源栅间接电连接的先进二极管封装结构 Download PDF

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CN112992834B
CN112992834B CN202110177369.XA CN202110177369A CN112992834B CN 112992834 B CN112992834 B CN 112992834B CN 202110177369 A CN202110177369 A CN 202110177369A CN 112992834 B CN112992834 B CN 112992834B
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metal sheet
semiconductor device
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device chip
bonding pad
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刘静
黄健
孙闫涛
顾昀浦
宋跃桦
吴平丽
张楠
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Jiejie Microelectronics Shanghai Technology Co ltd
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Abstract

本发明公开了一种源栅间接电连接的先进二极管封装结构，包括半导体器件芯片、阴极金属片、阳极金属片、塑封体；半导体器件芯片的第一表面设置有源极焊盘和栅极焊盘；半导体器件芯片的第二表面设置有漏极焊盘；半导体器件芯片的源极和栅极未直接短接；当所述源极焊盘和栅极焊盘直接短接时，半导体器件芯片为一MOS型先进二极管；源极焊盘、栅极焊盘分别通过电连接件与阳极金属片键合。本发明利用封装电连接电阻，在先进二极管正向工作时，在源极和栅极之间引入一个额外的压降，促进沟道开启，从而在维持漏电流IR不变或者更低的情况下降低了器件的正向导通电压VF，提升了先进二极管的性能；不增加器件复杂程度，具有广泛的适用性。

Description

一种源栅间接电连接的先进二极管封装结构
技术领域
本发明涉及功率半导体技术领域，具体为一种源栅间接电连接的先进二极管封装结构。
背景技术
传统的PN结结构的硅二极管由于其PN结区域微粒间的吸引束缚作用形成内部电场，从而其正向导通电压(VF)通常在0.7V左右。而随着当今的技术发展，各种不同结构的先进二极管突破该限制，在反向漏电流较低的前提下进一步降低了正向导通电压，其正向导通电压可低至0.4V，同时还具有其他优良性能。其中包括一类具有MOS结构区的先进二极管，利用对MOS结构区的沟道控制实现正向导通电压低、开关速度快、关断漏电少以及优秀的高温特性等优点而得到广泛应用。
现有技术中，由于先进二极管的半导体器件芯片通常具有正面电极和背面电极，需要通过封装将两个电极引至同一面上，以便与电路的其他部进行电连接。图1示出了现有技术中的一种常规的封装方法，将裸片设置在阴极金属片上使其背面电极与阴极金属片键合，通过引线将其正面电极与阳极金属片键合后塑封。其等效电路如图2所示，所述正面电极是由源极和栅极在芯片上直接短接得到。
对先进二极管而言，若能够在更低的正向电压下维持其中沟道的开启，则正向导通电压VF也会相应更低，进一步降低能量损耗。现有技术，例如公告号为CN102904421B的文件中提供了运用控制电路对MOS管的栅极电压进行控制以实现低电压下开启沟道的替代电路方案，但该方案中设置的元器件较多，结构复杂，在开关速度、高温特性等性能上受限，不能普适于各种大功率应用场景。
发明内容
本发明的目的在于提供一种先进二极管中源极和栅极间接电连接的方式，利用封装电连接电阻，在先进二极管正向工作时在源极和栅极之间引入一个额外的压降，促进先进二极管中MOS结构区的沟道的开启，在漏电流IR不变或者更低的情况下降低正向导通电压VF，提升先进二极管的整体性能。
为实现上述目的，本发明提供了一种源栅间接电连接的先进二极管封装结构，包括半导体器件芯片、阴极金属片、阳极金属片、塑封体；
所述半导体器件芯片的第一表面上设置有源极焊盘和栅极焊盘；所述半导体器件芯片的第二表面上设置有漏极焊盘；所述半导体器件芯片包括具有MOS结构区的有源区；所述MOS结构区的阈值电压Vth小于0.7V，进一步地，Vth小于0.4V；所述半导体器件芯片的源极和栅极未直接短接；当所述源极焊盘和栅极焊盘直接短接时，所述半导体器件芯片为一先进二极管，所述先进二极管的正向导通电压VF小于0.7V；所述先进二极管的性能更佳时，本发明的性能也相应更佳，所述先进二极管的VF低至0.4V时，本发明的VF可低至0.3V。
所述半导体器件芯片设置在阴极金属片上；所述漏极焊盘与阴极金属片键合；所述源极焊盘、栅极焊盘分别通过电连接件与阳极金属片键合；
所述塑封体包覆半导体器件芯片、阴极金属片、阳极金属片、电连接件；所述阴极金属片、所述阳极金属片的一端分别为阴极引脚、阳极引脚；所述阴极引脚、阳极引脚分别暴露于塑封体之外。
较佳地，所述电连接件为引线或者导电金属片；较佳地，所述导电金属片为金属铜片。
与现有技术相比，本发明具有如下有益效果：
1、本发明利用封装电连接电阻，在先进二极管正向工作时，在源极和栅极之间引入一个额外的压降，促进沟道开启，从而在维持漏电流IR不变或者更低的情况下降低了器件的正向导通电压VF，提升了先进二极管的性能。
2、本发明中仅需在半导体器件芯片和封装结构上进行较小的改动，即可提升先进二极管的性能，不增加器件复杂程度，具有广泛的适用性。
附图说明
图1为现有技术中先进二极管封装结构的示意图；
图2为现有技术中先进二极管封装结构的等效电路图；
图3为本发明的第一实施例的半导体器件芯片的剖面结构示意图；
图4为本发明的第一实施例的封装结构示意图；
图5为本发明的等效电路图；
图6为本发明的第二实施例的封装结构示意图；
图7为本发明的第三实施例的封装结构示意图；
图中：1、半导体器件芯片；2、正面电极；21、源极焊盘；22、栅极焊盘；3、阴极金属片；31、阴极引脚；4、阳极金属片；41、阳极引脚；5、塑封体；6、引线；61、源极引线；62栅极引线；7、导电金属片；R、封装电连接电阻；R1、源极电连接电阻；R2、栅极电连接电阻；S、源极；G、栅极；D、漏极；I、工作电流；IS、源极电流；IG、栅极电流；11、N+型衬底；12、N-型外延层；13、P掺杂体区；14、沟槽栅极填充区；15、栅氧化层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
第一实施例
图3示出了本实施例的半导体器件芯片1的剖面结构，包括有源区，有源区内包括若干个相互并联的器件元胞单元，器件元胞单元包括设置在有源区第二表面的N+型衬底11，以及位于N+型衬底11上的N-型外延层12，N-型外延层12内设置有沟槽，沟槽从有源区的第一表面延伸至N-型外延层4的内部；沟槽内设置有多晶硅的沟槽栅极填充区14；沟槽栅极填充区14和沟槽的侧、底壁之间隔离有栅氧化层15；N-型外延层4上还设置有P掺杂体区13；P掺杂体区13与沟槽的外侧壁接触；沟槽栅极填充区14的深度大于P掺杂体区13的深度。
本实施例中的半导体器件芯片1的结构仅作为一个范例示出；在其他的实施例中，半导体器件芯片1也可以具有其他结构，例如公开号为CN211743165U、CN111987170A的专利文件所述之半导体器件结构，其限制在于，所述半导体器件结构包括具有MOS结构的有源区，所述MOS结构的Vth低于0.7V。
图1示出了现有技术中先进二极管的封装结构。以相同结构的半导体器件芯片1为例，现有技术在第一表面上设置正面电极2将P掺杂体区13与沟槽栅极填充区14短接，封装后形成一先进二极管，其正向导通电压为0.4V。
图4示出了本实施例的封装结构，包括半导体器件芯片1、阴极金属片3、阳极金属片4、塑封体5；
半导体器件芯片1的第一表面上设置有源极焊盘21和栅极焊盘22；半导体器件芯片1的第二表面上设置有漏极焊盘；源极焊盘21与P掺杂体区13电连接；栅极焊盘22与沟槽栅极填充区14电连接；漏极焊盘与N+型衬底11电连接；
半导体器件芯片1设置在阴极金属片3上；漏极焊盘朝向阴极金属片3并键合；源极焊盘21、栅极焊盘22分别通过源极引线61、栅极引线62与阳极金属片4键合；
塑封体5包覆半导体器件芯片1、阴极金属片3、阳极金属片4、源极引线61、栅极引线62；阴极金属片3、所述阳极金属片4的一端分别为阴极引脚31、阳极引脚41；阴极引脚31、阳极引脚41分别暴露于塑封体5之外。
较佳地，用于将所述源极引线61设置有多于一根，以使电流分布更均匀、提升散热性能；源极焊盘21的面积大于栅极焊盘22；本领域技术人员可以根据需要调节源极引线61的长度、横截面积与数目，以调整其等效源极电连接电阻R1的大小。
图5示出了本发明的等效电路图，与图2所示的现有技术的等效电路图对比，本发明中源极(S)和栅极(G)之间并非直接短接，而是通过源极引线61、阳极金属片4、栅极引线62进行电连接，其中阳极金属片4的电阻相对于源极电连接电阻R1和栅极电连接电阻R2而言可以忽略。
在本实施例正向工作时，工作电流I从阳极通过引线分别流向源极和栅极形成源极电流IS和栅极电流IG，则I＝IG+IS，而栅源压差VGS＝-IG·R2+IS·R1。由于栅极电流IG≈0而远小于工作电流I和源极电流IS，可知I≈IS而VGS≈I·R1>0，该电压可以促使沟道开启，从而降低正向导通电压VF。在本实施例中，正向导通电压VF可从现有技术的0.4V降低至0.3V。在本实施例逆向工作时，类似地，栅源压差VGS<0，进一步促使沟道关闭，可以减小漏电流IR。综上可得，本实施例在结构变化较小，其他性能维持不变或更佳的条件下，进一步降低了正向导通电压VF，提升了先进二极管的总体性能。
需要注意的是，本发明实施例正向工作时，源极和漏极(D)之间的压差为VSD时，VF≈I·R1+VSD，源极电连接电阻R1越大，电阻压差损耗对正向导通电压VF的影响越大。因此，本领域技术人员需要根据实际应用需求以及半导体器件芯片1本身的性能参数，对源极电连接电阻R1的具体数值进行优化，以达到较佳的正向导通电压VF。本领域技术人员能够通过软件模拟等方式优化出其他条件一定的情况下的较佳阻值，该方式为本领域技术人员的常用手段，于此不再详述。
第二实施例
如图6所示，本实施例与第一实施例的区别在于，源极焊盘21通过导电金属片7与阳极金属片4键合。本领域技术人员可以根据需要调节导电金属片7的长度、宽度与厚度，以调整其等效源极电连接电阻R1的大小。
第三实施例
如图7所示，本实施例与第一实施例的区别在于，源极焊盘21、栅极焊盘22分别通过导电金属片7与阳极金属片4键合。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (6)

1.一种源栅间接电连接的先进二极管封装结构，其特征在于，包括半导体器件芯片、阴极金属片、阳极金属片、塑封体；
所述半导体器件芯片的第一表面上设置有源极焊盘和栅极焊盘；所述半导体器件芯片的第二表面上设置有漏极焊盘；所述半导体器件芯片包括具有MOS结构区的有源区；所述半导体器件芯片的源极和栅极未直接短接；当所述源极焊盘和栅极焊盘直接短接时，所述半导体器件芯片为一先进二极管，
所述半导体器件芯片设置在阴极金属片上；所述漏极焊盘与阴极金属片键合；所述源极焊盘、栅极焊盘分别通过电连接件与阳极金属片键合，利用封装电连接电阻，在先进二极管正向工作时，在源极和栅极之间引入一个额外的压降，促进沟道开启；
所述塑封体包覆半导体器件芯片、阴极金属片、阳极金属片、电连接件；所述阴极金属片、所述阳极金属片的一端分别为阴极引脚、阳极引脚；所述阴极引脚、阳极引脚分别暴露于塑封体之外。
2.根据权利要求1所述的源栅间接电连接的先进二极管封装结构，其特征在于，所述MOS结构区的阈值电压Vth小于0.7V。
3.根据权利要求2所述的源栅间接电连接的先进二极管封装结构，其特征在于，所述MOS结构区的阈值电压Vth小于0.4V。
4.根据权利要求1所述的源栅间接电连接的先进二极管封装结构，其特征在于，所述先进二极管的正向导通电压VF小于0.7V。
5.根据权利要求1所述的源栅间接电连接的先进二极管封装结构，其特征在于，所述电连接件为引线或者导电金属片。
6.根据权利要求5所述的源栅间接电连接的先进二极管封装结构，其特征在于，所述导电金属片为金属铜片。
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