CN112802757B - Substrate preparation method, substrate structure, chip packaging method and chip packaging structure - Google Patents
Substrate preparation method, substrate structure, chip packaging method and chip packaging structure Download PDFInfo
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- CN112802757B CN112802757B CN202011576169.3A CN202011576169A CN112802757B CN 112802757 B CN112802757 B CN 112802757B CN 202011576169 A CN202011576169 A CN 202011576169A CN 112802757 B CN112802757 B CN 112802757B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The invention discloses a substrate preparation method, a substrate structure, a chip packaging method and a chip packaging structure, wherein the substrate preparation method comprises the following steps: providing a first glass substrate, embedding a plurality of first conductive columns in the first glass substrate, and respectively exposing two end faces of the first conductive columns to two sides of the first glass substrate along the thickness direction of the first glass substrate to obtain a first sub-base plate; providing a second glass substrate, forming a circuit groove on one side of the second glass substrate, forming a plurality of via holes penetrating through the second glass substrate in the circuit groove, manufacturing a second conductive column in the via holes, and manufacturing a first redistribution layer connected with the second conductive column in the circuit groove to obtain a second sub-substrate; and attaching the first sub-substrate and the second sub-substrate together, and electrically connecting the first conductive column with the first redistribution layer to obtain the substrate structure. The conductive circuit of the substrate structure manufactured by the method has good connection stability, the manufacturing method is simple, the subsequent chip mounting is convenient, and the product yield is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a substrate preparation method, a substrate structure, a chip packaging method and a chip packaging structure.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. In order to comply with the development of new generation electronic products, especially the development of products such as mobile phones, notebooks, intelligent wearable devices, etc., chips are developed in the direction of higher density, faster speed, smaller size, lower cost, etc.
In the packaging process, due to the difference of the thermal expansion coefficients of materials such as plastic, silicon and metal, the volume changes of the materials are asynchronous, so that stress is generated and warping is caused. The difference between the thermal expansion coefficients of the chip and the injection molding material enables the stress generated in the cooling process of the injection molding material to be the most main cause of the warpage generation in the packaging technology.
In addition, in the chip fan-out package process, it is usually necessary to drill a plastic package layer of the covered flip chip and fabricate a conductive post by electroplating, so as to electrically lead out the flip chip. In the process of opening the holes, the depth of the holes is not easy to control, so that the chips are easily damaged or other conductive circuits are broken down, and the yield of the chip packaging structure is influenced.
Disclosure of Invention
One of the objectives of the present invention is to provide a substrate manufacturing method and a substrate structure manufactured by the method, in which the conductive circuit of the substrate structure has good connection stability, the manufacturing method is simple, and the subsequent chip mounting is facilitated, thereby improving the yield of products.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a method for preparing a substrate is provided,
providing a first glass substrate, embedding a plurality of first conductive columns in the first glass substrate, and respectively exposing two end surfaces of the first conductive columns to two sides of the first glass substrate along the thickness direction of the first glass substrate to obtain a first sub-base plate;
providing a second glass substrate, forming a circuit groove on one side of the second glass substrate, forming a plurality of via holes penetrating through the second glass substrate in the circuit groove, manufacturing a second conductive column in each via hole, and manufacturing a first redistribution layer connected with the second conductive column in the circuit groove to obtain a second sub-base plate;
and adhering the first sub-substrate and the second sub-substrate together, and electrically connecting the first conductive column with the first redistribution layer to obtain the substrate structure.
According to the invention, the first sub-substrate is prepared by embedding the first conductive column in the first glass substrate, the first redistribution layer is embedded in the second glass substrate, the second sub-substrate is prepared by embedding the first redistribution layer and the second conductive column in the second glass substrate, and then the first sub-substrate and the second sub-substrate are bonded, so that the first redistribution layer is electrically led out from two sides through the first conductive column and the second conductive column respectively.
Further, in one embodiment of the present invention, the first sub-substrate is specifically prepared by the following steps:
providing a first glass substrate, adhering a first photosensitive dry film on one side of the first glass substrate, and forming a plurality of windows after exposure and development;
forming a TGV through hole in the window for the first glass substrate;
manufacturing a first conductive column in the TGV through hole, enabling two end faces of the first conductive column to be flush with two sides of the first glass substrate respectively, and removing the residual first photosensitive dry film;
the second sub-substrate is prepared by the following steps:
providing a second glass substrate, forming a circuit groove on one side of the second glass substrate, and forming a through hole penetrating through the second glass substrate in the circuit groove;
manufacturing a first seed layer in the line groove;
pasting a second photosensitive dry film on the first seed layer, and forming a first patterning hole at least exposing the via hole after exposure and development;
manufacturing a second conductive pillar in the through hole and manufacturing a first redistribution layer in the first patterning hole;
removing the residual second photosensitive dry film and the first seed layer exposed out of the first redistribution layer to form a connecting groove corresponding to the position of the first conductive pillar;
and attaching the first sub-substrate and the second sub-substrate together, and attaching one end of the first conductive column to the surface of the first redistribution layer to obtain the substrate structure.
And the two opposite surfaces of the first conductive column of the first sub-substrate and the first redistribution layer of the second sub-substrate are attached face to realize electric connection so as to prepare the substrate structure with the double-sided electric contact points. The second conductive columns are integrally connected with the first redistribution layer, and the interconnection stability between the structures is improved.
Preferably, in another technical solution of the present invention, the first sub-substrate is specifically prepared by the following steps:
providing a first glass substrate, adhering a first photosensitive dry film on one side of the first glass substrate, and forming a plurality of windows after exposure and development;
forming a TGV through hole in the window for the first glass substrate;
manufacturing a first conductive column in the TGV through hole, enabling one end face of the first conductive column to be flush with one side of the first glass substrate, and enabling the other end face of the first conductive column to protrude out of the other side of the first glass substrate to form a boss;
the second sub-substrate is prepared by the following steps:
providing a second glass substrate, forming a circuit groove on one side of the second glass substrate, and forming a through hole penetrating through the second glass substrate in the circuit groove;
manufacturing a first seed layer in the line groove and on the surface of the via hole;
adhering a second photosensitive dry film on the first seed layer positioned on the circuit groove, exposing and developing to form a first patterned hole at least exposing the via hole, and enabling the residual second photosensitive dry film to at least cover the region of the first seed layer corresponding to the first conductive column and to be in contact with the hole wall of the first patterned hole;
manufacturing a second conductive pillar in the through hole and manufacturing a first redistribution layer in the first patterning hole;
removing the residual second photosensitive dry film and the first seed layer exposed out of the first redistribution layer to form a connecting groove corresponding to the position of the first conductive pillar;
and attaching the first sub-substrate and the second sub-substrate together, and inserting the first conductive columns into the connecting grooves to be electrically connected with the side face of the first redistribution layer to obtain the substrate structure.
In this embodiment, the first conductive pillar embedded in the first glass substrate is directly embedded in the connecting groove embedded in the first redistribution layer in the second glass substrate, so as to realize electrical connection, further enhance the interface bonding reliability between the first sub-substrate and the second sub-substrate, and greatly improve the interconnection stability between the conductive lines in the substrate structure.
Further, the method for opening the TGV through hole, the line slot and the via hole comprises the following steps: carrying out laser focusing modification on a region to be perforated to destroy the molecular chain structure of the region, and then etching by adopting liquid medicine; particularly for the opening of the line grooves and the via holes on the second glass substrate, the method can ensure that the line grooves and the via holes are formed and molded at one time, and improves the opening efficiency and quality.
Preferably, the liquid medicine is a hydrofluoric acid solution, and more preferably a hydrofluoric acid solution or an ammonium bifluoride solution.
According to the method, the time of laser focusing modification is controlled according to the thickness of a glass substrate and the depth of holes to be opened (TGV through holes, line grooves and via holes), and then hydrofluoric acid solution is adopted for soaking to etch the area subjected to laser focusing modification, so that the needed TGV through holes, line grooves and via holes are prepared.
In the present invention, the hole forming method is not limited to the above-mentioned methods, and mechanical drilling may be selected again or laser hole forming may be directly adopted, which is not described in detail.
According to the invention, the first sub-substrate and/or the second sub-substrate are/is stained with nano metal powder, the first sub-substrate and the second sub-substrate are bonded through hot pressing, and the first conductive columns are electrically connected with the first redistribution layer;
alternatively, the first sub-substrate and the second sub-substrate are subjected to plasma cleaning treatment, and then the first sub-substrate and the second sub-substrate are bonded by electrostatic adsorption, and the first conductive pillar is electrically connected to the first redistribution layer.
In another aspect, a substrate structure manufactured by the method for manufacturing a substrate includes:
the first glass substrate and the first conductive column embedded into the first glass substrate are provided, and two ends of the first conductive column are respectively exposed out of the first glass substrate;
a second glass substrate located at one side of the first glass substrate;
the first redistribution layer is embedded into the second glass substrate, and the surface of the first redistribution layer is flush with one surface, close to the first glass substrate, of the second glass substrate and is electrically connected with the first conductive columns;
and the second conductive pillars are embedded into the second glass substrate, are positioned on one side, away from the first glass substrate, of the first redistribution layer and are electrically connected with the first redistribution layer, and one ends, away from the first redistribution layer, of the second conductive pillars are exposed out of the second glass substrate.
As a preferable mode of the substrate structure, an end surface of the first conductive pillar is flush with a surface of the first glass substrate and is electrically connected to a surface of the first redistribution layer;
or, one end of the first conductive column close to the second glass substrate protrudes out of the first glass substrate to form a boss, the side surface of the first redistribution layer is provided with a plurality of connecting grooves, the boss is inserted into the connecting grooves and electrically connected with the first redistribution layer, and the interface combination stability of the substrate structure is relatively stronger.
Specifically, in order to form the first conductive column with the boss, a temporary carrier plate with a groove can be attached to one side of the first glass substrate, the structure of the groove can be designed according to specific conditions, a temporary bonding material is attached to the temporary carrier plate, and bonding removal processing is performed after the conductive column is manufactured in the TGV through hole through electroplating, so that the first conductive column is provided with the boss protruding out of the first glass substrate, and details are not repeated.
The second purpose of the present invention is to provide a chip packaging method and a chip packaging structure manufactured by the method, wherein the chip packaging method is based on the substrate manufacturing method in the above technical scheme, the chip packaging is convenient, the warpage phenomenon is reduced, the signal output of the chip is stable, and the product yield is improved.
In one aspect, a chip packaging method is provided, which includes the following steps:
s100, manufacturing a substrate structure according to the substrate manufacturing method, and manufacturing a second redistribution layer electrically connected with the first conductive pillar on a first glass substrate of the substrate structure;
s200, providing a plurality of chips, and inversely installing the chips on the second rewiring layer and carrying out plastic package;
s300, manufacturing a solder mask layer on a second glass substrate of the substrate structure and exposing the second conductive column;
s400, providing a plurality of metal bumps, and implanting the metal bumps at the positions of the second conductive pillars.
Wherein, step S100 specifically includes the following steps:
s100a, providing a substrate structure prepared by the substrate preparation method, and preparing a second seed layer on a first glass substrate of the substrate structure;
s100b, attaching a third photosensitive dry film on the second seed layer, and carrying out exposure and development processing on the third photosensitive dry film to form a second patterned hole;
s100c, manufacturing a second rewiring layer in the second patterning hole;
s100d, removing the residual third photosensitive dry film and the exposed second seed layer.
According to the invention, the second rewiring layer is manufactured after the second seed layer is manufactured on the first glass substrate, so that the adhesion stability of the second rewiring layer on the first glass substrate is improved, the limited range of the mounting position of the flip chip is reduced, and the chip packaging is facilitated.
When the chip is provided with the copper column, the copper column of the chip is dipped with nano metal powder and is inversely arranged on the second rewiring layer, and laser sintering treatment is carried out on one side, far away from the first glass substrate, of the second glass substrate by adopting laser, so that the copper column is fixedly connected with the second rewiring layer, and the chip mounting stability is improved.
On the other hand, a chip packaging structure is provided, which is manufactured by the chip packaging method, and comprises the following steps:
a substrate structure;
the second rewiring layer is positioned on one side, away from the second glass substrate, of the first glass substrate of the base plate structure and is electrically connected with the first conductive columns;
a plurality of chips which are inversely arranged on the second rewiring layer;
the plastic packaging layer is positioned on one side, away from the second glass substrate, of the first glass substrate and covers the chip and the second rewiring layer;
the solder mask is positioned on one side, away from the first glass substrate, of the second glass substrate, and welding positions for exposing the second conductive columns are formed in the solder mask;
and the plurality of metal bumps are positioned in the welding positions and are electrically connected with the second conductive columns.
The substrate structure may be any one of the substrate structures described in the above technical solutions, and details are not repeated.
The invention has the beneficial effects that:
(1) according to the invention, the first sub-substrate is prepared by embedding the first conductive column in the first glass substrate, the second sub-substrate is prepared by embedding the first redistribution layer and the second conductive column in the second glass substrate, and then the first sub-substrate is attached to the second sub-substrate, so that the first redistribution layer is electrically led out from two sides through the first conductive column and the second conductive column respectively, the prepared substrate structure is convenient for chip mounting, the conductive column is prepared by opening the substrate after the chip is mounted, the substrate made of glass material can effectively reduce the warping phenomenon generated during chip packaging, and the product yield is improved;
(2) carrying out laser focusing modification on a region to be perforated to destroy the molecular chain structure of the region, and then etching by adopting liquid medicine; particularly for the arrangement of the line grooves and the via holes on the second glass substrate, the line grooves and the via holes can be formed at one time by adopting the method, so that the hole forming efficiency is improved;
(3) one end, close to the second glass substrate, of the first conductive column protrudes out of the first glass substrate to form a boss, the side face of the first redistribution layer is provided with a plurality of connecting grooves, and the boss is inserted into the connecting grooves and electrically connected with the first redistribution layer, so that the interface combination stability of the substrate structure is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic cross-sectional view of a first glass substrate with TGV through holes according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of the first glass substrate with the first conductive pillar embedded therein according to the first embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a second glass substrate with a line groove and a via hole according to a first embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of the second glass substrate with the first redistribution layer and the second conductive pillar embedded therein according to the first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of the first sub-substrate and the second sub-substrate after being bonded according to the first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a substrate structure according to a first embodiment of the invention, after a first redistribution layer is formed on a first glass substrate.
Fig. 7 is a schematic cross-sectional view of a chip flip-chip mounted on a first redistribution layer according to a first embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of a packaged chip according to a first embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of a substrate structure according to a first embodiment of the present invention, in which a solder mask layer is formed on a second glass substrate and a solder site is formed on the second glass substrate.
Fig. 10 is a schematic cross-sectional view of the metal bump implant bonding site and the second conductive pillar after connection according to the first embodiment of the invention.
Fig. 11 is a schematic cross-sectional view of the first glass substrate with the first conductive pillars embedded therein according to the second embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of a second glass substrate with a line trench and a via hole according to a second embodiment of the invention.
Fig. 13 is a schematic cross-sectional view of the second glass substrate with the first redistribution layer and the second conductive pillars embedded therein and the connection grooves exposed according to the second embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view of the first sub-substrate and the second sub-substrate bonded together according to the second embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view of the substrate structure according to the second embodiment of the present invention after a first redistribution layer is formed on a first glass substrate.
Fig. 16 is a schematic cross-sectional view of a chip according to a second embodiment of the present invention after being flip-chip mounted on a first redistribution layer.
Fig. 17 is a schematic cross-sectional view of a packaged chip according to the second embodiment of the invention.
Fig. 18 is a schematic cross-sectional view of a substrate structure according to a second embodiment of the present invention, in which a solder resist layer is formed on a second glass substrate and a solder site is formed.
Fig. 19 is a schematic cross-sectional view of the metal bump implant bonding site and the second conductive pillar according to the second embodiment of the invention.
In the figure:
11. a first glass substrate; 12. a TGV through hole; 13. a first conductive post;
21. a second glass substrate; 22. a line slot; 23. a via hole; 24. a second conductive post; 25. a first rewiring layer; 26. connecting grooves;
31. a second rewiring layer; 32. a chip; 33. a plastic packaging layer; 34. a solder resist layer; 35. and a metal bump.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
Example one
The chip packaging method of the embodiment comprises the following steps:
s10, preparing a first sub-substrate:
s10a, providing a first glass substrate 11, attaching a first photosensitive dry film on one side of the first glass substrate 11, and forming a plurality of windows after exposure and development;
s10b, performing laser focus modification on the first glass substrate 11 exposed out of the window, and then etching the laser focus modification area with a hydrofluoric acid solution to obtain a TGV through hole 12 penetrating through the first glass substrate 11, referring to fig. 1;
s10c, forming first conductive pillars 13 in the TGV through holes 12 by electroplating, making two end surfaces of the first conductive pillars 13 respectively flush with two sides of the first glass substrate 11, and then removing the remaining first photosensitive dry film, referring to fig. 2;
s20, preparing a second sub-substrate:
s20a, providing a second glass substrate 21, designing an opening area of the circuit groove 22 and an opening position of the via hole 23 in the circuit groove 22 according to the circuit of the first redistribution layer 25 and the position of the first conductive pillar 13, then performing laser focusing modification, and etching the laser focusing modification area with a hydrofluoric acid solution after the modification, thereby forming the circuit groove 22 on one side of the second glass substrate 21 and forming the via hole 23 penetrating through the second glass substrate 21 in the circuit groove 22, with reference to fig. 3;
s20b, manufacturing a first seed layer in the line grooves 22 and on the surfaces of the via holes 23 through vacuum sputtering;
s20c, adhering a second photosensitive dry film on the surface of the first seed layer positioned on the circuit groove 22, and forming a first patterning hole at least exposing the via hole 23 after exposure and development; meanwhile, the region to be formed of the first redistribution layer 25 is also exposed to the first patterning hole;
s20d, fabricating second conductive pillars 24 within the vias 23 by electroplating, and fabricating first redistribution layers 25 within the first patterned holes, referring to fig. 4;
s20e, removing the residual second photosensitive dry film and the first seed layer exposed from the first redistribution layer 25;
s30, bonding the first sub-substrate and the second sub-substrate:
performing plasma cleaning treatment on the first sub-substrate and the second sub-substrate, then attaching the first sub-substrate and the second sub-substrate through electrostatic adsorption, and attaching and connecting one end of the first conductive pillar 13 to the surface of the first redistribution layer 25 to obtain the substrate structure shown in fig. 5;
s40, chip packaging:
s40a, manufacturing a second seed layer on the first glass substrate 11 of the substrate structure through vacuum sputtering;
s40b, attaching a third photosensitive dry film on the second seed layer, and carrying out exposure and development processing on the third photosensitive dry film to form a second patterning hole;
s40c, manufacturing a second rewiring layer 31 in the second patterned hole through electroplating;
s40d, removing the residual third photosensitive dry film and the exposed second seed layer, referring to fig. 6;
s40e, providing a plurality of chips 32, flip-chip mounting the chips 32 on the second redistribution layer 31 (refer to fig. 7) and performing plastic encapsulation to form a plastic encapsulation layer 33, refer to fig. 8;
s40f, fabricating the solder resist layer 34 on the second glass substrate 21 of the base plate structure and exposing the second conductive pillar 24, refer to fig. 9;
s40g, providing a plurality of metal bumps 35, and implanting the metal bumps 35 at the positions of the second conductive pillars 24, referring to fig. 10;
as shown in fig. 5, the substrate structure manufactured by the above method includes:
the first glass substrate 11 and the first conductive pillar 13 embedded in the first glass substrate 11, wherein two ends of the first conductive pillar 13 are respectively exposed out of the first glass substrate 11;
a second glass substrate 21 located on one side of the first glass substrate 11;
a first redistribution layer 25 embedded in the second glass substrate 21, a surface of the first redistribution layer 25 being flush with a surface of the second glass substrate 21 close to the first glass substrate 11 and electrically connected to the first conductive pillar 13;
the second conductive pillars 24 are embedded in the second glass substrate 21, the second conductive pillars 24 are located on one side of the first redistribution layer 25 away from the first glass substrate 11 and are electrically connected with the first redistribution layer 25, and one ends of the second conductive pillars 24 away from the first redistribution layer 25 are exposed out of the second glass substrate 21;
wherein, an end face of the first conductive pillar 13 is flush with the surface of the first glass substrate 11 and is electrically connected to the surface of the first redistribution layer 25.
The chip package structure manufactured by the method is shown in fig. 10 and comprises the following components:
a substrate structure as shown in FIG. 5;
a second rewiring layer 31 located on a side of the first glass substrate 11 away from the second glass substrate 21 and electrically connected to the first conductive pillars 13;
a plurality of chips 32 flip-chip mounted on the second rewiring layer 31;
a plastic sealing layer 33 which is positioned on one side of the first glass substrate 11 away from the second glass substrate 21 and covers the chip 32 and the second rewiring layer 31;
the solder mask layer 34 is positioned on one side of the second glass substrate 21 away from the first glass substrate 11, and the solder mask layer 34 is provided with a welding position for exposing the second conductive pillar 24;
and a plurality of metal bumps 35 located in the soldering locations and electrically connected to the second conductive pillars 24.
Example two
The chip packaging method of this embodiment is substantially the same as the first embodiment, except that the substrate manufacturing method specifically includes the following steps:
s10, preparing a first sub-substrate:
s10a, providing a first glass substrate 11, attaching a first photosensitive dry film on one side of the first glass substrate 11, and forming a plurality of windows after exposure and development;
s10b, performing laser focusing modification on the first glass substrate 11 exposed out of the window, and then etching the laser focusing modified area by adopting an ammonium bifluoride solution to obtain a TGV through hole 12 penetrating through the first glass substrate 11, referring to FIG. 1;
s10c, forming a first conductive pillar 13 in the TGV through hole 12 by electroplating, and making one end surface of the first conductive pillar 13 flush with one side of the first glass substrate 11, and making the other end surface protrude from the other side of the first glass substrate 11 to form a boss, referring to fig. 11;
s20, preparing a second sub-substrate:
s20a, providing a second glass substrate 21, designing an opening area of the circuit groove 22 and an opening position of the via hole 23 in the circuit groove 22 according to the circuit of the first redistribution layer 25 and the position of the first conductive pillar 13, then performing laser focusing modification, and etching the laser focusing modified area with an ammonium bifluoride solution after the modification, thereby forming the circuit groove 22 on one side of the second glass substrate 21 and forming the via hole 23 penetrating through the second glass substrate 21 in the circuit groove 22, with reference to fig. 12;
s20b, manufacturing a first seed layer in the line grooves 22 and on the surfaces of the via holes 23 through vacuum sputtering;
s20c, attaching a second photosensitive dry film on the surface of the first seed layer on the circuit groove 22, exposing and developing to form a first patterned hole exposing at least the via hole 23, so that the remaining second photosensitive dry film covers at least the area of the first seed layer corresponding to the first conductive pillar 13 and contacts the hole wall of the first patterned hole; meanwhile, the region of the first redistribution layer 25 to be formed is exposed out of the first patterning hole;
s20d, fabricating second conductive pillars 24 within the vias 23 by electroplating and fabricating first redistribution layers 25 within the first patterned holes;
s20e, removing the remaining second photosensitive dry film and the first seed layer exposed from the first redistribution layer 25, and forming a connection groove 26 corresponding to the position of the first conductive pillar 13, referring to fig. 13; the depth of the connecting groove 26 matches with the length of the protruding head of the first conductive pillar 13, or is slightly smaller than the length of the protruding head of the first conductive pillar 13;
s30, bonding the first sub-substrate and the second sub-substrate:
the first sub-substrate and/or the second sub-substrate are/is stained with nano metal powder, the first sub-substrate and the second sub-substrate are bonded by hot pressing, and the first conductive pillars 13 are inserted into the connecting grooves 26 and electrically connected with the side surfaces of the first redistribution layer 25, so as to obtain a substrate structure, referring to fig. 14;
s40, and performing chip packaging, which is described with reference to fig. 15-19 and will not be described again.
The substrate structure obtained by the substrate preparation method of this embodiment is shown in fig. 14, and includes:
the first glass substrate 11 and the first conductive pillars 13 embedded in the first glass substrate 11, both ends of the second conductive pillars 24 are respectively exposed out of the first glass substrate 11;
a second glass substrate 21 located on one side of the first glass substrate 11;
the first redistribution layer 25 is embedded in the second glass substrate 21, and the surface of the first redistribution layer 25 is flush with one surface, close to the first glass substrate 11, of the second glass substrate 21 and is electrically connected with the first conductive pillar 13;
the second conductive pillars 24 are embedded in the second glass substrate 21, the second conductive pillars 24 are located on one side of the first redistribution layer 25 away from the second glass substrate 21 and electrically connected to the first redistribution layer 25, and one ends of the second conductive pillars 24 away from the first redistribution layer 25 are exposed out of the second glass substrate 21;
one end of the first conductive pillar 13 close to the second glass substrate 21 protrudes out of the first glass substrate 11 to form a boss, the side surface of the first redistribution layer 25 has a plurality of connecting grooves 26, and the boss is inserted into the connecting grooves 26 and electrically connected to the first redistribution layer 25.
The chip package structure manufactured by the method of the embodiment is shown in fig. 19, and includes:
the substrate structure shown in fig. 14;
a second rewiring layer 31 located on a side of the first glass substrate 11 away from the second glass substrate 21 and electrically connected to the first conductive pillars 13;
a plurality of chips 32 flip-chip mounted on the second rewiring layer 31;
a plastic sealing layer 33 which is positioned on one side of the first glass substrate 11 away from the second glass substrate 21 and covers the chip 32 and the second rewiring layer 31;
the solder mask layer 34 is positioned on one side of the second glass substrate 21 away from the first glass substrate 11, and the solder mask layer 34 is provided with a welding position for exposing the second conductive pillar 24;
and a plurality of metal bumps 35 located in the soldering locations and electrically connected to the second conductive pillars 24.
In the above two embodiments, when the chip 32 is provided with copper pillars, the copper pillars of the chip 32 may be adhered with nano-metal powder and flip-chip mounted on the second redistribution layer 31, and laser sintering is performed from the side of the second glass substrate 21 away from the first glass substrate 11 by using laser, so that the copper pillars are fixedly connected to the second redistribution layer 31.
In the two embodiments, the preparation order of the first sub-substrate and the second sub-substrate is not limited, and the preparation of the first sub-substrate and the preparation of the second sub-substrate may be performed simultaneously, or the second sub-substrate may be prepared before the first sub-substrate.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (12)
1. A method for preparing a substrate is characterized in that,
providing a first glass substrate, embedding a plurality of first conductive columns in the first glass substrate, and respectively exposing two end surfaces of the first conductive columns to two sides of the first glass substrate along the thickness direction of the first glass substrate to obtain a first sub-base plate;
providing a second glass substrate, carrying out laser focusing modification on an area to be provided with a circuit groove on one side of the second glass substrate, then etching by using a liquid medicine to form the circuit groove, forming a plurality of via holes penetrating through the second glass substrate in the circuit groove, manufacturing a second conductive column in the via holes, and manufacturing a first rewiring layer connected with the second conductive column in the circuit groove to obtain a second sub-substrate;
and adhering the first sub-substrate and the second sub-substrate together, and electrically connecting the first conductive column with the first redistribution layer to obtain the substrate structure.
2. The method of claim 1, wherein the first sub-substrate is prepared by the steps of:
providing a first glass substrate, adhering a first photosensitive dry film on one side of the first glass substrate, and forming a plurality of windows after exposure and development;
forming a TGV through hole in the window for the first glass substrate;
manufacturing a first conductive column in the TGV through hole, enabling two end faces of the first conductive column to be flush with two sides of the first glass substrate respectively, and removing the residual first photosensitive dry film;
the second sub-substrate is prepared by the following steps:
providing a second glass substrate, forming a circuit groove on one side of the second glass substrate, and forming a through hole penetrating through the second glass substrate in the circuit groove;
manufacturing a first seed layer in the line groove and on the surface of the via hole;
adhering a second photosensitive dry film on the first seed layer positioned on the line groove, and forming a first patterning hole at least exposing the via hole after exposure and development;
manufacturing a second conductive pillar in the through hole and manufacturing a first redistribution layer in the first graphical hole;
removing the residual second photosensitive dry film and the first seed layer exposed out of the first redistribution layer to form a connecting groove corresponding to the position of the first conductive pillar;
and attaching the first sub-substrate and the second sub-substrate together, and attaching one end of the first conductive column to the surface of the first redistribution layer to obtain the substrate structure.
3. The method of claim 1, wherein the first sub-substrate is prepared by the steps of:
providing a first glass substrate, adhering a first photosensitive dry film on one side of the first glass substrate, and forming a plurality of windows after exposure and development;
forming a TGV through hole in the window for the first glass substrate;
manufacturing a first conductive column in the TGV through hole, enabling one end face of the first conductive column to be flush with one side of the first glass substrate, and enabling the other end face of the first conductive column to protrude out of the other side of the first glass substrate to form a boss;
the second sub-substrate is prepared by the following steps:
providing a second glass substrate, forming a circuit groove on one side of the second glass substrate, and forming a through hole penetrating through the second glass substrate in the circuit groove;
manufacturing a first seed layer in the line groove and on the surface of the via hole;
adhering a second photosensitive dry film on the first seed layer positioned on the circuit groove, exposing and developing to form a first patterned hole at least exposing the via hole, and enabling the residual second photosensitive dry film to at least cover the region of the first seed layer corresponding to the first conductive column and to be in contact with the hole wall of the first patterned hole;
manufacturing a second conductive pillar in the through hole and manufacturing a first redistribution layer in the first patterning hole;
removing the residual second photosensitive dry film and the first seed layer exposed out of the first redistribution layer to form a connecting groove corresponding to the position of the first conductive pillar;
and attaching the first sub-substrate and the second sub-substrate together, and inserting the first conductive columns into the connecting grooves to be electrically connected with the side face of the first redistribution layer to obtain the substrate structure.
4. The method for preparing a substrate according to claim 2 or 3, wherein the TGV through holes and the via holes are opened by: and carrying out laser focusing modification on the area to be perforated, and then etching by adopting liquid medicine.
5. The method for manufacturing a substrate according to claim 4, wherein the chemical solution is a hydrofluoric acid-based solution.
6. The method for manufacturing a substrate according to claim 4, wherein the chemical solution is a hydrofluoric acid solution or an ammonium bifluoride solution.
7. The method for manufacturing a substrate according to claim 1, wherein the first sub-substrate and/or the second sub-substrate are/is coated with nano metal powder, the first sub-substrate and the second sub-substrate are bonded by hot pressing, and the first conductive pillar is electrically connected to the first redistribution layer;
or, performing plasma cleaning treatment on the first sub-substrate and the second sub-substrate, and then bonding the first sub-substrate and the second sub-substrate by electrostatic adsorption, and electrically connecting the first conductive pillar and the first redistribution layer.
8. A substrate structure produced by the substrate production method according to any one of claims 1 to 7, comprising:
the first glass substrate and the first conductive column embedded into the first glass substrate are provided, and two ends of the first conductive column are respectively exposed out of the first glass substrate;
a second glass substrate located at one side of the first glass substrate;
a first redistribution layer embedded in the second glass substrate, wherein a surface of the first redistribution layer is flush with a surface of the second glass substrate close to the first glass substrate and is electrically connected with the first conductive pillar;
and the second conductive pillars are embedded into the second glass substrate, are positioned on one side, away from the first glass substrate, of the first redistribution layer and are electrically connected with the first redistribution layer, and one ends, away from the first redistribution layer, of the second conductive pillars are exposed out of the second glass substrate.
9. The substrate structure according to claim 8, wherein an end surface of the first conductive pillar is flush with a surface of the first glass substrate and electrically connected to a surface of the first redistribution layer;
or, one end of the first conductive column, which is close to the second glass substrate, protrudes out of the first glass substrate to form a boss, the side surface of the first redistribution layer is provided with a plurality of connecting grooves, and the boss is inserted into the connecting grooves and electrically connected with the first redistribution layer.
10. A chip packaging method is characterized by comprising the following steps:
s100, manufacturing a substrate structure according to the substrate preparation method of any one of claims 1 to 7, and manufacturing a second redistribution layer electrically connected with the first conductive pillars on a first glass substrate of the substrate structure;
s200, providing a plurality of chips, and inversely installing the chips on the second rewiring layer and carrying out plastic package;
s300, manufacturing a solder mask layer on a second glass substrate of the substrate structure and exposing the second conductive column;
s400, providing a plurality of metal bumps, and implanting the metal bumps at the positions of the second conductive pillars.
11. The chip packaging method according to claim 10, wherein step S100 specifically includes the steps of:
s100a, providing a substrate structure prepared by the substrate preparation method of any one of claims 1 to 7, and preparing a second seed layer on a first glass substrate of the substrate structure;
s100b, attaching a third photosensitive dry film on the second seed layer, and carrying out exposure and development processing on the third photosensitive dry film to form a second patterned hole;
s100c, manufacturing a second rewiring layer in the second patterning hole;
s100d, removing the residual third photosensitive dry film and the exposed second seed layer.
12. A chip packaging structure obtained by the chip packaging method according to claim 10 or 11, comprising:
a substrate structure;
the second rewiring layer is positioned on one side, away from the second glass substrate, of the first glass substrate of the base plate structure and is electrically connected with the first conductive columns;
a plurality of chips which are inversely arranged on the second rewiring layer;
the plastic packaging layer is positioned on one side, away from the second glass substrate, of the first glass substrate and covers the chip and the second rewiring layer;
the solder mask is positioned on one side, away from the first glass substrate, of the second glass substrate, and welding positions for exposing the second conductive columns are formed in the solder mask;
and the plurality of metal bumps are positioned in the welding positions and are electrically connected with the second conductive columns.
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| JP2002368420A (en) * | 2001-06-05 | 2002-12-20 | Murata Mfg Co Ltd | Method for manufacturing glass ceramic multilayer substrate and glass ceramic multilayer substrate |
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| JPWO2012049822A1 (en) * | 2010-10-14 | 2014-02-24 | パナソニック株式会社 | Hybrid substrate, method for manufacturing the same, and semiconductor integrated circuit package |
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| JP2002368420A (en) * | 2001-06-05 | 2002-12-20 | Murata Mfg Co Ltd | Method for manufacturing glass ceramic multilayer substrate and glass ceramic multilayer substrate |
| JP2010129650A (en) * | 2008-11-26 | 2010-06-10 | Kyocera Corp | Method for manufacturing complex circuit board |
| TW201349974A (en) * | 2012-05-28 | 2013-12-01 | Zhen Ding Technology Co Ltd | Multilayer printed circuit board and method for manufacturing same |
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Effective date of registration: 20230410 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |