JP2005064446A - Method of manufacturing laminating module - Google Patents

Method of manufacturing laminating module Download PDF

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JP2005064446A
JP2005064446A JP2003382108A JP2003382108A JP2005064446A JP 2005064446 A JP2005064446 A JP 2005064446A JP 2003382108 A JP2003382108 A JP 2003382108A JP 2003382108 A JP2003382108 A JP 2003382108A JP 2005064446 A JP2005064446 A JP 2005064446A
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core substrate
hole
electronic component
core
manufacturing
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Satoru Kuramochi
悟 倉持
Yoshitaka Fukuoka
義孝 福岡
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminating module which is equipped with a built-in electronic part and high in reliability. <P>SOLUTION: A core board is provided with a recess cut in its one side for keeping an electronic part inside and a through-hole through which its front and rear surfaces are connected together with a conductive material. The electronic part is provided inside the recess cut in the core board, and a wiring layer which is capable of ensuring necessary continuity through vias is formed on the core board where the electronic part is provided through the intermediary of an electrical insulating layer. Thus, the laminating module is equipped with the core board whose front and rear surface are connected together, and the built-in electronic part is provided and the wiring layer is provided on the core board through the intermediary of the electrical insulating layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、多層配線基板製造に使用する積層用モジュール、特にＬＳＩチップ等の電子部品を内蔵した積層用モジュールの製造方法に関する。   The present invention relates to a stacking module used for manufacturing a multilayer wiring board, and more particularly to a manufacturing method of a stacking module incorporating electronic components such as LSI chips.

従来の多層配線基板は、例えば、サブトラクティブ法等で作製した低密度配線を有する両面基板をコア基板とし、このコア基板の両面にビルドアップ法により高密度配線を形成して作製されたものである。また、最近では、ＬＳＩチップ等を多層配線基板上に直接実装するベアチップ実装法が提案されている。ベアチップ実装法では、予め多層配線基板上に形成された配線の接続パッド部に、ボンディング・ワイヤ、ハンダや金属球等からなるバンプ、異方性導電膜、導電性接着剤、光収縮性樹脂等の接続手段を用いて半導体チップが実装される。そして、作製する半導体装置にキャパシターやインダクター等のＬＣＲ回路部品が必要な場合は、半導体チップと同様に、多層配線基板に外付けで実装されている   A conventional multilayer wiring board is produced by, for example, using a double-sided board having low-density wiring produced by a subtractive method or the like as a core board, and forming high-density wiring on both sides of the core board by a build-up method. is there. Recently, a bare chip mounting method in which an LSI chip or the like is directly mounted on a multilayer wiring board has been proposed. In the bare chip mounting method, bonding pads, wiring bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc. are formed in advance on wiring connection pads formed on a multilayer wiring board. A semiconductor chip is mounted using the connecting means. If the semiconductor device to be manufactured requires an LCR circuit component such as a capacitor or an inductor, it is externally mounted on the multilayer wiring board in the same manner as the semiconductor chip.

しかし、多層配線基板上に形成された配線の接続パッド部は、半導体チップ等の電子部品の実装部位とは別の部位に設けられるため、多層配線基板の面方向の広がりが必要であった。したがって、多層配線基板の小型化には限界があり、実装される電子部品の数が増えることにより、小型化は更に困難となる傾向にあった。
これに対応するために、半導体チップを実装した薄い基板と、上下導通ビアを備えた穴明きの枠基板を、それぞれ複数個作製しておき、多層配線基板の作製時に、この実装基板と枠基板とを１つのモジュールとして一括で積層する方法が開示されている（特許文献１）。この方法によれば、複数のモジュールを積層しても、多層配線基板の面方向の広がりは必要がないため、多層配線基板の小型化が可能であった。
特開２００２−２７１０１５号公報 However, since the connection pad portion of the wiring formed on the multilayer wiring board is provided in a part different from the mounting part of the electronic component such as a semiconductor chip, it is necessary to expand the surface direction of the multilayer wiring board. Therefore, there is a limit to the miniaturization of the multilayer wiring board, and the miniaturization tends to become more difficult as the number of electronic components to be mounted increases.
In order to cope with this, a plurality of thin substrates on which semiconductor chips are mounted and a perforated frame substrate with vertical conduction vias are respectively prepared. A method of laminating a substrate as a single module is disclosed (Patent Document 1). According to this method, even if a plurality of modules are stacked, it is not necessary to expand the multilayer wiring board in the surface direction, so that the multilayer wiring board can be reduced in size.
JP 2002-271015 A

しかしながら、上述のような実装基板と枠基板とからなるモジュールでは、個々の半導体チップを基板の所定の部位に実装するための位置合わせを正確に行う必要があり、工程管理が煩雑であるとともに、実装位置のズレが生じた場合、多層配線基板の信頼性が低下するという問題があった。
本発明は、上記のような実情に鑑みてなされたものであり、電子部品を内蔵した信頼性の高い積層用モジュールの製造方法を提供することを目的とする。 However, in the module composed of the mounting substrate and the frame substrate as described above, it is necessary to accurately perform alignment for mounting each semiconductor chip on a predetermined portion of the substrate, and the process management is complicated. When the mounting position is shifted, there is a problem that the reliability of the multilayer wiring board is lowered.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a highly reliable stacking module incorporating an electronic component.

このような目的を達成するために、本発明は、コア基板と、該コア基板に内蔵された電子部品と、導電材料により前記コア基板の表裏の導通をとるためのスルーホールと、前記コア基板上に電気絶縁層を介して配設された配線層と、を備えた積層用モジュールの製造方法において、電子部品を内蔵するための凹部を一方の面に有し、導電材料によりスルーホールを介した表裏の導通がとられたコア基板を作製する工程と、該コア基板の前記凹部内に電子部品を配設する工程と、前記電子部品が配設された前記コア基板上に電気絶縁層を介し該電気絶縁層に形成されたビア部で必要な導通がとられた配線層を形成する工程と、を有するような構成とした。   In order to achieve such an object, the present invention provides a core substrate, an electronic component built in the core substrate, a through hole for conducting conduction between the front and back surfaces of the core substrate with a conductive material, and the core substrate. And a wiring layer disposed on an electrical insulating layer on the one side having a recess for containing an electronic component, and through the through hole with a conductive material. A step of producing a core substrate having electrical conduction between the front and back sides, a step of disposing an electronic component in the recess of the core substrate, and an electrical insulating layer on the core substrate on which the electronic component is disposed. And a step of forming a wiring layer in which necessary conduction is obtained in the via portion formed in the electrical insulating layer.

本発明の他の態様として、配設された電子部品がコア基板表面から突出しないように、電子部品の厚み、大きさに合わせて前記凹部を形成するような構成とした。
本発明の他の態様として、コア基板用のコア材の一方の面にＩＣＰ−ＲＩＥまたはサンドブラストにより孔部を穿設し、前記コア材の他方の面を研磨して前記孔部を露出させて前記スルーホールを形成するような構成、あるいは、コア基板用のコア材を研磨して所定の厚みとし、その後、一方の面、あるいは、両面から、ＩＣＰ−ＲＩＥまたはサンドブラストによりスルーホールを形成するような構成とした。 As another aspect of the present invention, the concave portion is formed in accordance with the thickness and size of the electronic component so that the arranged electronic component does not protrude from the core substrate surface.
As another aspect of the present invention, a hole is formed in one surface of the core material for the core substrate by ICP-RIE or sandblast, and the other surface of the core material is polished to expose the hole. The structure for forming the through hole, or the core material for the core substrate is polished to a predetermined thickness, and then the through hole is formed by ICP-RIE or sandblasting from one side or both sides. The configuration was

本発明の他の態様として、前記コア基板の厚みを５０〜３００μｍの範囲内で設定し、前記スルーホールの開口径を５〜３００μｍの範囲内で設定するような構成とした。
本発明の他の態様として、前記電子部品を前記凹部内に配設した後、コア基板の反対面を研磨して、コア基板の厚みを５０〜３００μｍの範囲内の所定の厚みにするような構成とした。 As another aspect of the present invention, the thickness of the core substrate is set within a range of 50 to 300 μm, and the opening diameter of the through hole is set within a range of 5 to 300 μm.
As another aspect of the present invention, after disposing the electronic component in the recess, the opposite surface of the core substrate is polished so that the thickness of the core substrate becomes a predetermined thickness in the range of 50 to 300 μm. The configuration.

本発明によれば、導電材料によりスルーホールを介した表裏の導通がとられたコア基板の凹部内に電子部品を配設するだけで複数の電子部品の位置合わせが完了し、個々の電子部品の精密な位置合わせが不要であり、このように複数の電子部品が所望の位置に配設されているコア基板上に電気絶縁層を介しビア部で必要な導通がとられた配線層を形成するので、配線の端子部上にバンプを介して個々の電子部品を搭載する従来の方法に比べて、電子部品の位置合わせが極めて容易であるとともに、配線層と各電子部品との接続信頼性が格段に向上する。   According to the present invention, alignment of a plurality of electronic components is completed simply by disposing the electronic components in the recesses of the core substrate in which conduction between the front and back sides is made through the through holes with the conductive material. In this way, a wiring layer that has the necessary electrical conduction at the via portion is formed on the core substrate on which a plurality of electronic components are arranged at a desired position via an electrical insulating layer. Therefore, compared with the conventional method in which individual electronic components are mounted on the terminal portions of the wiring via bumps, the positioning of the electronic components is extremely easy, and the connection reliability between the wiring layer and each electronic component is very high. Is significantly improved.

以下、本発明の実施の形態について図面を参照して説明する。
図１は、本発明の一実施形態を説明するための工程図である。本発明では、まず、コア基板１２を準備する（図１（Ａ））。コア基板１２は、コア材１２′に凹部１３とスルーホール１４が形成されたものであり、各スルーホール１４には導電材料１５が充填され、この導電材料１５によりスルーホール１４を介した表面１２ａと裏面１２ｂの導通がなされている。このようなコア基板１２の厚みは、５０〜３００μｍの範囲内で設定することが好ましい。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a process diagram for explaining an embodiment of the present invention. In the present invention, first, the core substrate 12 is prepared (FIG. 1A). The core substrate 12 is formed by forming a recess 13 and a through hole 14 in a core material 12 ′. Each through hole 14 is filled with a conductive material 15, and the surface 12 a through the through hole 14 is filled with the conductive material 15. And the back surface 12b are electrically connected. The thickness of the core substrate 12 is preferably set within a range of 50 to 300 μm.

コア基板１２に用いるコア材１２′は、ＸＹ方向（コア基板１２の表面１２ａ（あるいは裏面１２ｂ）に平行な平面）の熱膨張係数が２〜２０ｐｐｍ、好ましくは２．５〜１７ｐｐｍの範囲内であることが望ましい。このようなコア材１２′は、例えば、シリコン、セラミック、ガラス、ガラス−エポキシ複合材料等を用いることができる。尚、本発明では、熱膨張係数はＴＭＡ（サーマルメカニカルアナリシス）により測定するものである。
凹部１３は、配設する電子部品の厚み、大きさに合わせて形成することができる。例えば、配設された電子部品の表面とコア基板１２の表面１２ａが同一面をなすような深さで凹部１３を形成する。凹部１３の形成方法には特に制限はないが、例えば、コア材１２′の一方の面に、形成する凹部１３に対応する開口部を有するマスクパターンを形成し、このマスクパターンをマスクとして、プラズマを利用したドライエッチング法であるＩＣＰ−ＲＩＥ（Inductive Coupled Plasma - Reactive Ion Etching）またはサンドブラストによりコア材１２′を所定の深さまで掘り下げることにより、凹部１３を形成することができる。 The core material 12 'used for the core substrate 12 has a thermal expansion coefficient in the XY direction (a plane parallel to the front surface 12a (or the back surface 12b) of the core substrate 12) of 2 to 20 ppm, preferably 2.5 to 17 ppm. It is desirable to be. For example, silicon, ceramic, glass, glass-epoxy composite material, or the like can be used as the core material 12 '. In the present invention, the thermal expansion coefficient is measured by TMA (thermal mechanical analysis).
The recess 13 can be formed in accordance with the thickness and size of the electronic component to be disposed. For example, the recess 13 is formed with such a depth that the surface of the arranged electronic component and the surface 12a of the core substrate 12 are flush with each other. The method for forming the recess 13 is not particularly limited. For example, a mask pattern having an opening corresponding to the recess 13 to be formed is formed on one surface of the core material 12 ′, and the mask pattern is used as a mask for plasma. The concave portion 13 can be formed by digging the core material 12 'to a predetermined depth by ICP-RIE (Inductive Coupled Plasma-Reactive Ion Etching), which is a dry etching method utilizing the above, or by sandblasting.

スルーホール１４は内径が略同一であるストレート形状、一端の開口径が他端の開口径よりも大きいテーパー形状、中央部の内径が両端の開口径と異なる形状等、いずれであってもよい。図示例では、コア基板１２の表面１２ａ側のスルーホール１４の開口径が、反対側（コア基板１２の裏面１２ｂ側）の開口径よりも大きいテーパー形状となっている。このようなスルーホール１４の開口径は、５〜３００μｍの範囲内で設定することが好ましい。   The through hole 14 may have any one of a straight shape having substantially the same inner diameter, a tapered shape in which the opening diameter at one end is larger than the opening diameter at the other end, and a shape in which the inner diameter at the center is different from the opening diameters at both ends. In the illustrated example, the opening diameter of the through hole 14 on the front surface 12a side of the core substrate 12 has a tapered shape that is larger than the opening diameter on the opposite side (the back surface 12b side of the core substrate 12). The opening diameter of such a through hole 14 is preferably set within a range of 5 to 300 μm.

スルーホール１４に充填された導電材料１５としては、例えば、銅粒子、銀粒子等の導電性粒子を含有した公知の導電性ペーストを用いることができる。この場合、スルーホール１４の内壁面、コア材１２′の表面に、必要に応じて二酸化珪素、窒化珪素等の電気絶縁膜を形成してもよい。また、例えば、スルーホール１４の内壁に絶縁層と導電薄膜を積層して形成することにより表面１２ａと裏面１２ｂの導通をとってもよい。この場合、絶縁層は二酸化珪素、窒化珪素等の電気絶縁膜とすることができ、導電薄膜は銅、クロム、チタン、窒化チタン、ニッケル等の下地導電薄膜と、下地導電薄膜上に積層された銅、銀、金、ニッケル等の導電材料からなる薄膜とすることができる。尚、このような構成で表面１２ａと裏面１２ｂの導通をとった場合、スルーホール１４内には、導電性ペースト、絶縁性ペースト等の任意の充填材料を充填することができる。   As the conductive material 15 filled in the through hole 14, for example, a known conductive paste containing conductive particles such as copper particles and silver particles can be used. In this case, an electrical insulating film such as silicon dioxide or silicon nitride may be formed on the inner wall surface of the through hole 14 and the surface of the core material 12 'as necessary. Further, for example, the front surface 12a and the back surface 12b may be electrically connected by forming an insulating layer and a conductive thin film on the inner wall of the through hole 14. In this case, the insulating layer can be an electrical insulating film such as silicon dioxide or silicon nitride, and the conductive thin film is laminated on the base conductive thin film with a base conductive thin film such as copper, chromium, titanium, titanium nitride, or nickel. A thin film made of a conductive material such as copper, silver, gold, or nickel can be used. Note that when the front surface 12a and the back surface 12b are electrically connected in such a configuration, the through hole 14 can be filled with an arbitrary filling material such as a conductive paste or an insulating paste.

次に、コア基板１２の凹部１３に電子部品１６を配設する（図１（Ｂ））。電子部品１６は、ダイボンディングペースト等の接着剤を用いて凹部１３内に固着してもよい。電子部品１６としては、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上とすることができ、また、複数個の電子部品１６を内蔵してもよく、特に制限はない。
次いで、電子部品１６を内蔵したコア基板１２の表面１２ａ上に、ビア部１８を有する電気絶縁層１７を介して配線層１９を形成して、積層用モジュール１１を作製する（図１（Ｃ））。 Next, the electronic component 16 is disposed in the recess 13 of the core substrate 12 (FIG. 1B). The electronic component 16 may be fixed in the recess 13 using an adhesive such as a die bonding paste. The electronic component 16 can be any one or more of LSI chip, IC chip, LCR electronic component, and sensor component, and a plurality of electronic components 16 may be built in. There is no.
Next, a wiring layer 19 is formed on the surface 12a of the core substrate 12 in which the electronic component 16 is embedded via an electrical insulating layer 17 having a via portion 18, and the stacking module 11 is manufactured (FIG. 1C). ).

ビア部１８を有する電気絶縁層１７と配線層１９の形成は、例えば、以下のように行うことができる。まず、電子部品１６を内蔵したコア基板１２の表面１２ａを覆うように感光性の電気絶縁層１７を形成する。この電気絶縁層１７を所定のマスクを介して露光し、現像することにより、コア基板１２のスルーホール１４に充填された導電材料１５と、電子部品１６の端子部１６ａが露出するように小径の穴部を電気絶縁層１７の所定位置に形成する。そして、洗浄後、穴部内および電気絶縁層１７上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させてビア部１８と配線層１９を形成し、レジストパターンと導電層を除去する。
また、ビア部１８を有する電気絶縁層１７と配線層１９の形成は、以下のように行うこともできる。すなわち、電子部品１６を内蔵したコア基板１２の表面１２ａを覆うように電気絶縁層１７を形成する。次に、炭酸ガスレーザー、ＵＶ−ＹＡＧレーザー等を用いて小径の穴部を電気絶縁層１７の所定位置に形成する。この穴部は、コア基板１２のスルーホール１４に充填された導電材料１５と、電子部品１６の端子部１６ａが露出するように形成する。そして、洗浄後、穴部内および電気絶縁層１７に無電解めっきにより導電層を形成し、この導電層上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させてビア部１８と配線層１９を形成し、レジストパターンと導電層を除去する。
ビア部１８と配線層１９を形成する導電材料としては、銅、銀、金、アルミニウム等を使用することができる。 For example, the electrical insulating layer 17 and the wiring layer 19 having the via portion 18 can be formed as follows. First, a photosensitive electrical insulating layer 17 is formed so as to cover the surface 12a of the core substrate 12 in which the electronic component 16 is embedded. By exposing and developing this electrical insulating layer 17 through a predetermined mask, the conductive material 15 filled in the through hole 14 of the core substrate 12 and the terminal portion 16a of the electronic component 16 are exposed to have a small diameter. A hole is formed at a predetermined position of the electrical insulating layer 17. Then, after cleaning, a conductive layer is formed in the hole and on the electrical insulating layer 17 by a vacuum film forming method, a resist layer is formed on the conductive layer, and a resist pattern is formed by performing desired pattern exposure and development. To do. Thereafter, using this resist pattern as a mask, a conductive material is deposited on the exposed portion including the hole portion by electrolytic plating to form a via portion 18 and a wiring layer 19, and the resist pattern and the conductive layer are removed.
The formation of the electrical insulating layer 17 and the wiring layer 19 having the via portion 18 can also be performed as follows. That is, the electrical insulating layer 17 is formed so as to cover the surface 12a of the core substrate 12 in which the electronic component 16 is embedded. Next, a small-diameter hole is formed at a predetermined position of the electrical insulating layer 17 using a carbon dioxide gas laser, a UV-YAG laser, or the like. The hole is formed so that the conductive material 15 filled in the through hole 14 of the core substrate 12 and the terminal 16a of the electronic component 16 are exposed. Then, after cleaning, a conductive layer is formed in the hole and in the electrical insulating layer 17 by electroless plating, and a dry film resist is laminated on the conductive layer, and a desired pattern exposure and development are performed to form a resist pattern. . Thereafter, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed portion including the hole portion to form a via portion 18 and a wiring layer 19, and the resist pattern and the conductive layer are removed.
As the conductive material for forming the via portion 18 and the wiring layer 19, copper, silver, gold, aluminum, or the like can be used.

ここで、コア基板１２におけるスルーホール１４の形成方法について説明する。
スルーホール１４の形成方法としては、例えば、以下の方法が挙げられる。ます、コア基板用のコア材１２′の一方の面にマスクパターンを形成し、このマスクパターンを形成した面から、プラズマを利用したドライエッチング法であるＩＣＰ−ＲＩＥ（Inductive Coupled Plasma - Reactive Ion Etching）またはサンドブラストによりコア材１２′に微細孔を穿設する。次に、コア材１２′からマスクパターンを除去し、コア材１２′の他方の面を研磨して、上記の微細孔を露出させることによりスルーホール１４を形成することができる。 Here, a method of forming the through hole 14 in the core substrate 12 will be described.
Examples of a method for forming the through hole 14 include the following methods. First, a mask pattern is formed on one surface of the core material 12 'for the core substrate, and from the surface on which the mask pattern is formed, ICP-RIE (Inductive Coupled Plasma-Reactive Ion Etching) is a dry etching method using plasma. ) Or fine holes are drilled in the core material 12 'by sandblasting. Next, the through hole 14 can be formed by removing the mask pattern from the core material 12 ′ and polishing the other surface of the core material 12 ′ to expose the fine holes.

また、スルーホールの他の形成方法として、以下の方法が挙げられる。まず、コア基板用のコア材１２′の両面を研磨して所定の厚みとし、その後、コア材１２′の一方の面にマスクパターンを形成する。次に、このマスクパターンをマスクとして、ＩＣＰ−ＲＩＥまたはサンドブラストによりコア材１２′に微細な貫通孔を形成してスルーホール１４を形成する。尚、コア材１２′の両面を研磨して所定の厚みとした後、コア材１２′の両面にマスクパターンを形成し、コア材１２′の両面から微細孔を穿設してスルーホール１４を形成してもよい。   Moreover, the following method is mentioned as another formation method of a through hole. First, both surfaces of the core material 12 'for the core substrate are polished to a predetermined thickness, and then a mask pattern is formed on one surface of the core material 12'. Next, using this mask pattern as a mask, a fine through hole is formed in the core material 12 ′ by ICP-RIE or sandblasting to form a through hole 14. In addition, after polishing both surfaces of the core material 12 'to a predetermined thickness, a mask pattern is formed on both surfaces of the core material 12', and through holes 14 are formed by drilling fine holes from both surfaces of the core material 12 '. It may be formed.

上述の本発明の積層用モジュールの製造方法は例示であり、これに限定されるものではなく、例えば、電子部品１６を凹部１３内に配設した後、コア基板１２の反対面を研磨することにより、コア基板の厚みの最終的な調整を行ってもよい。また、内蔵する電子部品の数には制限はなく、内蔵される電子部品は同一種、あるいは、異種のものであってもよい。   The above-described method for manufacturing the stacking module of the present invention is an example, and is not limited thereto. For example, after the electronic component 16 is disposed in the recess 13, the opposite surface of the core substrate 12 is polished. Thus, the final adjustment of the thickness of the core substrate may be performed. Further, the number of built-in electronic components is not limited, and the built-in electronic components may be of the same type or different types.

次に、具体的実施例を挙げて本発明を更に詳細に説明する。
［実施例１］
コア材として、厚み６２５μｍのシリコンウエハを準備し、このコア材の一方の面に感光性ドライフィルムレジスト（旭化成（株）製ＡＰＲ）をラミネートし、スルーホール形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。上記のシリコンウエハのＸＹ方向（シリコンウエハの表面に平行な平面）の熱膨張係数は、２．５ｐｐｍであった。また、マスクパターンは、直径が１００μｍである円形開口が３００μｍピッチで２００００個形成されたものであった。次に、このマスクパターンをマスクとしてＩＣＰ−ＲＩＥによりドライエッチングを行い、コア材に２００００個の微細孔を穿設し、その後、アセトンを用いてマスクパターンをコア材から除去した。形成した微細孔は、開口径が１５０μｍ、深さが３００μｍの円筒形状の内壁面を有するものであった。 Next, the present invention will be described in more detail with specific examples.
[Example 1]
A silicon wafer having a thickness of 625 μm is prepared as a core material, a photosensitive dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) is laminated on one surface of the core material, and exposure is performed through a photomask for forming a through hole. A mask pattern was formed by development. The thermal expansion coefficient of the above silicon wafer in the XY direction (a plane parallel to the surface of the silicon wafer) was 2.5 ppm. Further, the mask pattern was formed by 20000 circular openings having a diameter of 100 μm at a pitch of 300 μm. Next, using this mask pattern as a mask, dry etching was performed by ICP-RIE to make 20000 fine holes in the core material, and then the mask pattern was removed from the core material using acetone. The formed micropores had a cylindrical inner wall surface with an opening diameter of 150 μm and a depth of 300 μm.

次に、コア材の微細孔を形成した面側に、再度、感光性ドライフィルムレジスト（旭化成（株）製ＡＰＲ）をラミネートし、凹部形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。このマスクパターンは、微細孔非形成部位に１０ｍｍ×１０ｍｍの長方形開口が１２ｍｍピッチで４９個形成されたものであった。次に、このマスクパターンをマスクとしてサンドブラストによりコア材に凹部を形成し、その後、アセトンを用いてマスクパターンをコア材から除去した。このように形成した凹部は、開口寸法が１０ｍｍ×１０ｍｍ、深さが５０μｍの長方体形状であった。   Next, a photosensitive dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) is laminated again on the side of the core material where the micropores are formed, and the mask is formed by exposing and developing through a photomask for forming recesses. A pattern was formed. This mask pattern was such that 49 rectangular openings of 10 mm × 10 mm were formed at 12 mm pitch in the non-micro-hole formation site. Next, a concave portion was formed in the core material by sand blasting using this mask pattern as a mask, and then the mask pattern was removed from the core material using acetone. The concave portion thus formed was a rectangular shape having an opening size of 10 mm × 10 mm and a depth of 50 μm.

次いで、上記の微細孔および凹部を形成していないコア材の面を研削装置により研磨してコア材の厚みを３００μｍとすることにより、この研磨面に微細孔を露出させてスルーホールを形成した。
次いで、コア材に熱酸化処理（１０５０℃、２０分間）を施して、コア材の表面（スルーホール内壁面、凹部内壁面を含む）に二酸化珪素からなる絶縁膜を形成した。次いで、銅粒子を含有する導電性ペーストを、コア材の凹部を形成していない面側からスクリーン印刷によりスルーホール内に充填し、硬化処理（１７０℃、２０分間）を施した。その後、コア材面から硬化突出した導電性ペーストを研磨して、スルーホール内に充填された導電性ペーストの表面とコア材の表面とが同一面となるようにしてコア基板を得た。 Next, the surface of the core material in which the fine holes and the recesses are not formed is polished by a grinding device so that the thickness of the core material is 300 μm, thereby exposing the fine holes on the polished surface to form a through hole. .
Next, the core material was subjected to thermal oxidation treatment (1050 ° C., 20 minutes) to form an insulating film made of silicon dioxide on the surface of the core material (including the inner wall surface of the through hole and the inner wall surface of the recess). Subsequently, the conductive paste containing copper particles was filled into the through hole by screen printing from the surface side where the concave portion of the core material was not formed, and subjected to curing treatment (170 ° C., 20 minutes). Thereafter, the conductive paste that hardened and protruded from the core material surface was polished to obtain a core substrate so that the surface of the conductive paste filled in the through hole and the surface of the core material were flush with each other.

次に、コア基板の複数の凹部にＬＳＩチップ（１０ｍｍ×１０ｍｍ、厚み５０μｍ）を、端子部が上面となるように、接着剤（エイブルスティック（株）製エイブルボンド３２３０）を用いて配設した。このＬＳＩチップの配設では、従来の配線端子上へのＬＳＩチップ搭載に要求されるような精密な位置合わせ管理は不要であった。
次に、上記のようにＬＳＩチップを配設したコア基板上にベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して厚み１０μｍの電気絶縁層を形成した。 Next, LSI chips (10 mm × 10 mm, thickness 50 μm) were disposed in the plurality of recesses of the core substrate using an adhesive (Able Bond 3230 manufactured by Able Stick Co., Ltd.) so that the terminal portion was on the upper surface. . In the arrangement of the LSI chip, the precise alignment management required for mounting the LSI chip on the conventional wiring terminal is unnecessary.
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is applied to the core substrate on which the LSI chip is disposed as described above by a spin coater and dried to form an electrical insulating layer having a thickness of 10 μm. did.

次に、炭酸ガスレーザーを用いて、スルーホールに充填した導電性ペーストとＬＳＩチップの端子部が露出するように小径の穴部（内径２５μｍ）を電気絶縁層の所定位置に形成した。そして、洗浄後、穴部内および電気絶縁層上にスパッタリング法によりクロムと銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、配線層形成用のフォトマスクを介し露光、現像して配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき（厚み４μｍ）を行い、その後、レジストパターンと導電層を除去した。これにより、スルーホールに充填した導電性ペーストやＬＳＩチップの端子部の所定部位とビア部によって接続された配線層を、電気絶縁層を介してコア基板上に形成し、積層用モジュール（実施例１）を得た。
このように作製した積層用モジュールでは、コア基板に内蔵された４９個のＬＳＩチップの全てが、配線層と良好な接続状態であることが確認された。 Next, a carbon dioxide laser was used to form a small-diameter hole (inner diameter 25 μm) at a predetermined position of the electrical insulating layer so that the conductive paste filled in the through hole and the terminal portion of the LSI chip were exposed. After cleaning, a conductive layer made of chromium and copper was formed by sputtering in the hole and on the electrical insulating layer, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Next, a resist pattern for wiring formation was formed by exposure and development through a photomask for wiring layer formation. Electrolytic copper plating (thickness: 4 μm) was performed using this resist pattern as a mask, and then the resist pattern and the conductive layer were removed. As a result, a conductive paste filled in the through hole and a wiring layer connected by a predetermined portion of the terminal portion of the LSI chip and the via portion are formed on the core substrate via the electric insulating layer, and the module for stacking (Example) 1) was obtained.
In the laminated module thus fabricated, it was confirmed that all 49 LSI chips built in the core substrate were in good connection with the wiring layer.

小型で高信頼性が要求される半導体装置や各種電子機器への用途にも適用できる。   It can also be applied to small semiconductor devices and various electronic devices that require high reliability.

本発明の積層用モジュールの製造方法の一実施形態を示す工程図である。It is process drawing which shows one Embodiment of the manufacturing method of the module for lamination | stacking of this invention.

符号の説明Explanation of symbols

１１…積層用モジュール
１２……コア基板
１２′…コア材
１３…凹部
１４…スルーホール
１５…導電材料
１６…電子部品内蔵層
１７…絶縁樹脂層
１８…ビア部
１９…配線層 DESCRIPTION OF SYMBOLS 11 ... Module for lamination | stacking 12 ... Core board | substrate 12 '... Core material 13 ... Recessed part 14 ... Through-hole 15 ... Conductive material 16 ... Electronic component built-in layer 17 ... Insulating resin layer 18 ... Via part 19 ... Wiring layer

Claims (6)

コア基板と、該コア基板に内蔵された電子部品と、導電材料により前記コア基板の表裏の導通をとるためのスルーホールと、前記コア基板上に電気絶縁層を介して配設された配線層と、を備えた積層用モジュールの製造方法において、
電子部品を内蔵するための凹部を一方の面に有し、導電材料によりスルーホールを介した表裏の導通がとられたコア基板を作製する工程と、
該コア基板の前記凹部内に電子部品を配設する工程と、
前記電子部品が配設された前記コア基板上に電気絶縁層を介し該電気絶縁層に形成されたビア部で必要な導通がとられた配線層を形成する工程と、を有することを特徴とする積層用モジュールの製造方法。 A core substrate, an electronic component embedded in the core substrate, a through hole for conducting conduction between the front and back surfaces of the core substrate by a conductive material, and a wiring layer disposed on the core substrate via an electrical insulating layer In a manufacturing method of a module for lamination comprising
A step of producing a core substrate having a recess for incorporating an electronic component on one side and conducting conduction between the front and back through a through hole with a conductive material;
Disposing an electronic component in the recess of the core substrate;
Forming a wiring layer having a necessary electrical connection at a via portion formed in the electrical insulating layer via the electrical insulating layer on the core substrate on which the electronic component is disposed. A method for manufacturing a stacking module. 配設された電子部品がコア基板表面から突出しないように、電子部品の厚み、大きさに合わせて前記凹部を形成することを特徴とする請求項１に記載の積層用モジュールの製造方法。   The method for manufacturing a stacking module according to claim 1, wherein the concave portion is formed in accordance with the thickness and size of the electronic component so that the arranged electronic component does not protrude from the surface of the core substrate. コア基板用のコア材の一方の面にＩＣＰ−ＲＩＥまたはサンドブラストにより孔部を穿設し、前記コア材の他方の面を研磨して前記孔部を露出させて前記スルーホールを形成することを特徴とする請求項１または請求項２に記載の積層用モジュールの製造方法。   Forming a hole in one surface of the core material for the core substrate by ICP-RIE or sandblasting, polishing the other surface of the core material to expose the hole, and forming the through hole. The manufacturing method of the module for lamination | stacking of Claim 1 or Claim 2 characterized by the above-mentioned. コア基板用のコア材を研磨して所定の厚みとし、その後、一方の面、あるいは、両面から、ＩＣＰ−ＲＩＥまたはサンドブラストによりスルーホールを形成することを特徴とする請求項１または請求項２に記載の積層用モジュールの製造方法。   The core material for the core substrate is polished to a predetermined thickness, and then a through hole is formed from one side or both sides by ICP-RIE or sandblasting. The manufacturing method of the module for lamination | stacking of description. 前記コア基板の厚みを５０〜３００μｍの範囲内で設定し、前記スルーホールの開口径を５〜３００μｍの範囲内で設定することを特徴とする請求項１乃至請求項４のいずれかに記載の積層用モジュールの製造方法。   5. The thickness of the core substrate is set within a range of 50 to 300 [mu] m, and the opening diameter of the through hole is set within a range of 5 to 300 [mu] m. A method for manufacturing a module for stacking. 前記電子部品を前記凹部内に配設した後、コア基板の反対面を研磨して、コア基板の厚みを５０〜３００μｍの範囲内の所定の厚みにすることを特徴とする請求項１乃至請求項５のいずれかに記載の積層用モジュールの製造方法。   2. The electronic device according to claim 1, wherein after disposing the electronic component in the recess, the opposite surface of the core substrate is polished so that the thickness of the core substrate is a predetermined thickness within a range of 50 to 300 [mu] m. Item 6. A method for manufacturing a stacking module according to any one of Items 5 to 6.
JP2003382108A 2003-07-25 2003-11-12 Method of manufacturing laminating module Pending JP2005064446A (en)

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