CN111106013B - Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof - Google Patents

Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof Download PDF

Info

Publication number
CN111106013B
CN111106013B CN201911050901.0A CN201911050901A CN111106013B CN 111106013 B CN111106013 B CN 111106013B CN 201911050901 A CN201911050901 A CN 201911050901A CN 111106013 B CN111106013 B CN 111106013B
Authority
CN
China
Prior art keywords
chip
sealing plate
plastic sealing
filling
tmv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911050901.0A
Other languages
Chinese (zh)
Other versions
CN111106013A (en
Inventor
崔成强
李潮
杨斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Fozhixin Microelectronics Technology Research Co ltd
Original Assignee
Guangdong Xinhua Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Xinhua Microelectronics Technology Co ltd filed Critical Guangdong Xinhua Microelectronics Technology Co ltd
Priority to CN201911050901.0A priority Critical patent/CN111106013B/en
Publication of CN111106013A publication Critical patent/CN111106013A/en
Application granted granted Critical
Publication of CN111106013B publication Critical patent/CN111106013B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a preparation method of a TMV structure, which comprises the following steps: providing a chip plastic sealing plate, and forming blind holes in a non-chip area of the chip plastic sealing plate along the thickness direction of the chip plastic sealing plate; filling metal filling columns in the blind holes; and grinding and polishing one side surface of the chip plastic sealing plate, which is far away from the blind hole opening, so that one end of the metal filling column, which is far away from the side surface, is flush with the surface of the chip plastic sealing plate, and a TMV structure is formed. Compared with the traditional TMV structure adopting a through hole deposition preparation method, the blind hole filling cost is low, the problem of filling gaps of the TMV structure through holes can be solved, the dummy filling probability is reduced, the packaging quality and reliability are improved, and the production cost is reduced; the invention also discloses a preparation method of the large-board fan-out heterogeneous integrated packaging structure, and the large-board fan-out heterogeneous integrated packaging structure with low cost, miniaturization and high integration can be prepared by adopting the method, so that the reliability of the vertical interconnection structure can be improved.

Description

Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof
Technical Field
The invention belongs to the technical field of integrated circuit packaging, relates to a packaging structure and a preparation method thereof, and particularly relates to a manufacturing method of a TMV structure, a preparation method of a large-board fan-out heterogeneous integrated packaging structure comprising the manufacturing method of the TMV structure, and the large-board fan-out heterogeneous integrated packaging structure prepared by the preparation method.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. In order to comply with the development of the new generation of electronic products, especially the development of mobile phones, notebooks and other products, the chip is developed in the direction of higher density, faster speed, smaller size, lower cost and the like. The appearance of a Fan-out Package (Fan-out Wafer Level Package, FOPLP) technology has a wider development prospect as an upgrading technology of the Fan-out Wafer Level Package (FOWLP). Compared with the traditional lead bonding chip, the fan-out type packaging greatly increases the pin number of the chip, reduces the packaging size, simplifies the packaging steps, shortens the distance between the chip and the substrate, and improves the chip function. The chip has the advantages of supporting a chip with a process of less than 10nm, short interconnection path, high integration level, ultrathin thickness, high reliability, high heat dissipation capability and the like. In addition, the technology is one of the best solutions for implementing SiP (system in package) or three-dimensional heterogeneous integrated package, and has the advantages of low cost, high reliability, high heat dissipation, and the like.
The basic process for realizing three-dimensional heterogeneous integrated packaging or system packaging by using the board-level fan-out type packaging technology comprises the following steps: pasting temporary bonding glue on the carrier plate, mounting a chip, carrying out plastic package, removing the temporary bonding glue and the carrier plate, covering the dielectric layer (ABF), punching a TMV (through moving Via) through hole, and filling the TMV and the re-wiring layer (RDL). In the three-dimensional heterogeneous packaging and system integration packaging process, due to the edge effect of the TMV structure, the TMV structure is manufactured through the long TMV through hole, virtual filling is easily formed on the TMV, and the reliability of a packaged product is greatly reduced. In order to solve the problem, the method usually optimizes the liquid medicine components or sticks adhesive tapes at the bottom of the TMV to form false blind holes, and the methods either cannot fundamentally solve the problem of virtual filling or greatly increase the cost.
Disclosure of Invention
The invention aims to provide a preparation method of a TMV structure, which can improve the gap filling problem of the TMV, reduce the dummy filling probability and improve the packaging quality and reliability.
The invention also aims to provide a preparation method of the large-board fan-out heterogeneous integrated packaging structure, which can be used for preparing the large-board fan-out heterogeneous integrated packaging structure with low cost, miniaturization and high integration degree and improving the reliability of the vertical interconnection structure.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a method for preparing a TMV structure is provided, comprising the steps of:
s1, providing a chip plastic sealing plate, and forming blind holes in a non-chip area of the chip plastic sealing plate along the thickness direction of the chip plastic sealing plate;
s2, filling metal filling columns in the blind holes;
and S3, grinding and polishing one side face of the chip plastic sealing plate, which is far away from the opening of the blind hole, so that one end, which is far away from the side face, of the metal filling column is flush with the surface of the chip plastic sealing plate, and a TMV structure is formed.
As a preferable scheme of the method for preparing the TMV structure, in step S1, the blind holes are opened by mechanical drilling or laser drilling.
As a preferable scheme of the method for preparing the TMV structure, in step S1, after the blind hole is opened, the blind hole needs to be cleaned by plasma or solution to remove residues.
As a preferable scheme of the method for preparing the TMV structure, in step S2, the blind via is filled by using a physical vapor deposition, electroplating filling, chemical filling or mechanical filling method to form the metal filled column.
On the other hand, the preparation method of the large-board fan-out heterogeneous integrated packaging structure comprises the following steps:
s10, manufacturing a chip plastic sealing plate by using a plate-level technology;
s20, preparing the TMV structure by adopting the preparation method of the TMV structure;
s30, providing an antenna and an IPD, manufacturing a connecting line connected with the TMV structure on one side surface of the chip plastic sealing plate far away from a chip I/O interface inside the chip plastic sealing plate through electroplating, and connecting the antenna and the IPD with the connecting line;
s40, manufacturing a rewiring layer on one side surface of the chip plastic sealing plate close to the chip I/O interface inside the chip plastic sealing plate;
and S50, providing a metal bump, and implanting the metal bump into the pad area of the rewiring layer.
As a preferable scheme of the preparation method of the large-board fan-out heterogeneous integrated package structure, the step S10 specifically includes the following steps:
s10a, providing a carrier plate and a chip, wherein the front surface of the chip faces the carrier plate, and the chip is attached to one side of the carrier plate along the thickness direction of the carrier plate through temporary bonding glue;
s10b, carrying out plastic package on the chip by adopting a plastic package material, and forming a plastic package layer after the plastic package material is solidified;
s10c, removing the carrier plate and the temporary bonding glue to obtain the chip plastic sealing plate.
As a preferable scheme of the manufacturing method of the large-board fan-out type heterogeneous integrated package structure, in step S30, the antenna is tightly attached to the surface of the chip plastic sealing plate and electrically connected to the connection line, and the IPD is attached to a side of the connection line away from the chip plastic sealing plate.
As a preferable scheme of the preparation method of the large-board fan-out heterogeneous integrated package structure, the step S40 specifically includes the following steps:
s40a, manufacturing a seed layer on one side of the chip plastic sealing plate, which is flush with the I/O interface of the chip, through a vacuum sputtering method;
s40b, manufacturing the rewiring layer on the seed layer through a pattern electroplating method;
s40c, manufacturing a solder mask layer on the rewiring layer, and opening the solder mask layer to expose the pad area of the rewiring layer.
The invention also provides a large-board fan-out heterogeneous integrated packaging structure which is manufactured by the manufacturing method of the large-board fan-out heterogeneous integrated packaging structure.
The invention has the beneficial effects that:
the method has the advantages that the blind holes are formed in the chip plastic sealing plate, and the blind holes are filled, ground and polished, so that the filled metal filling columns are flush with the surface of the chip plastic sealing plate, and a high-quality and high-reliability TMV structure can be manufactured;
secondly, the chip plastic sealing plate is prepared by adopting a plate-level technology, and the antenna and the IPD are pasted on the basis of the TMV structure preparation method, so that a large-plate fan-out heterogeneous integrated packaging structure with low cost, miniaturization and high integration can be prepared, and the reliability of the vertical interconnection structure is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic cross-sectional view of a chip molding plate according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of an intermediate product obtained after blind holes are formed in a chip molding plate according to a first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of an intermediate product obtained after filling the blind holes according to the first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of an intermediate product obtained after grinding the first surface of the chip molding plate according to the first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a large board fan-out heterogeneous integrated package structure according to a first embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of an intermediate product obtained by forming blind holes in a chip molding plate according to the second embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view of an intermediate product obtained after filling the blind holes according to the second embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of an intermediate product obtained after grinding the first surface of the chip molding plate according to the second embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a large board fan-out heterogeneous integrated package structure according to a second embodiment of the present invention.
In the figure:
1. a chip plastic sealing plate; 11. a chip; 12. a plastic packaging layer; 13. blind holes;
2. a TMV structure;
3. an antenna;
4、IPD；
5. connecting a line;
6. a wiring layer is arranged;
7. and a metal bump.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example one
As shown in fig. 1 to 4, this embodiment provides a method for preparing a TMV structure, which includes the following steps:
s1, providing the chip molding sealing plate 1 shown in fig. 1, where the chip molding sealing plate 1 has a first surface adjacent to the I/O interface of the chip 11 therein and a second surface opposite to the first surface, a blind hole 13 is formed in a non-chip region of the chip molding sealing plate 1 along a thickness direction of the chip molding sealing plate 1, and an open end of the blind hole 13 is located on the second surface of the chip molding sealing plate 1, as shown in fig. 2;
s2, filling metal filling columns in the blind holes 13, as shown in FIG. 3;
s3, grinding and polishing the first surface of the chip molding sealing plate 1 to make one end of the metal filling column adjacent to the side surface flush with the surface of the chip molding sealing plate 1, so as to form the TMV structure 2, as shown in fig. 4.
This embodiment is through opening blind hole 13 on shrouding 1 is moulded to the chip to fill and grinding and polishing blind hole 13, make the metal packed column after filling and the surperficial parallel and level of shrouding 1 is moulded to the chip, can make high quality, high reliability's TMV structure 2, compare with traditional TMV structure preparation method, improve TMV and fill the gap problem, reduce virtual probability of filling, improved encapsulation quality and reliability, and reduced manufacturing cost.
The chip plastic sealing plate 1 is manufactured by adopting a plate-level packaging technology, and the plastic sealing layer 12 of the chip plastic sealing plate 1 can be of a single-layer structure or a multi-layer structure, and can be provided with blind holes 13.
The metal filling column is made of a metal copper material and has good conductivity.
In step S1 of this embodiment, the blind hole 13 is drilled by mechanical drilling or laser drilling. Wherein, mechanical drilling means that the adopted drilling equipment is in direct contact with the chip plastic sealing plate 1 to be drilled. The shape of the blind hole 13 is not limited, and may be a conical, cylindrical or rectangular column structure, for example, when the blind hole 13 is a conical structure, the specific depth-diameter ratio thereof may be designed and processed according to the thickness-diameter ratio of the TMV.
In step S1 of this embodiment, after the blind via 13 is opened, the blind via 13 needs to be cleaned by plasma or solution to remove the residue. Wherein, the solution adopted for cleaning is any one of potassium permanganate, hydrogen peroxide and other strong oxidants, and can effectively remove the residue generated after the blind hole is opened.
Optionally, in step S2 of the present embodiment, the blind via 13 is filled by using a physical vapor deposition, an electroplating filling, a chemical filling, or a mechanical filling method to form a metal filled pillar. The specific method for opening blind holes is the prior art, and is not described in detail.
The embodiment also provides a preparation method of the large-board fan-out heterogeneous integrated packaging structure, which comprises the following steps:
s10, manufacturing a chip plastic sealing plate 1 by using a plate-level technology;
s20, preparing a TMV structure 2 by adopting the preparation method of the TMV structure of the embodiment;
s30, providing an antenna 3 and an IPD4, manufacturing a connecting line 5 connected with the TMV structure 2 on the second surface of the chip plastic sealing plate 1, and connecting the antenna 3 and the IPD4 with the connecting line 5;
s40, manufacturing a rewiring layer 6 on the first surface of the chip plastic sealing plate 1;
and S50, providing a metal bump 7, and implanting the metal bump 7 into the pad area of the rewiring layer 6 to obtain the large-board fan-out heterogeneous integrated package structure shown in FIG. 5.
Optionally, the metal bump 7 is a solder, a silver solder, or a gold-tin alloy solder, the metal bump 7 of this embodiment is a metal ball structure, and the metal ball is implanted into the pad region of the redistribution layer 6 by soldering, so as to achieve electrical leading-out of the redistribution layer 6.
In the embodiment, the chip plastic sealing plate 1 is prepared by adopting a plate-level technology, then the blind holes 13 and the filling blind holes 13 are formed, the blind hole filling columns are ground and polished, and then the rewiring layer 6, the surface-mounted antenna 3 and the IPD4 are prepared, so that the large-board fan-out heterogeneous integrated packaging structure with low cost, miniaturization and high integration is prepared, and the reliability of the vertical interconnection structure is improved.
Further, step S10 specifically includes the following steps:
s10a, providing a carrier plate and a chip 11, enabling the front surface of the chip 11 to face the carrier plate, and attaching the chip 11 to one side of the carrier plate along the thickness direction of the carrier plate through temporary bonding glue;
s10b, carrying out plastic package on the chip 11 by adopting a plastic package material, and forming a plastic package layer 12 after the plastic package material is solidified;
and S10c, removing the carrier plate and the temporary bonding glue to obtain the chip plastic sealing plate 1.
Wherein the carrier plate is made of BT, FR4, FR5, PP, EMC, ABF or PI materials; the Molding Compound is any one of polyimide, silicone and EMC (Epoxy Molding Compound), and the embodiment is preferably EMC, so that the chip 11 can be stably attached to the carrier, and the chip 11 can be protected.
Further, in step S30, the antenna 3 is tightly attached to the second surface of the chip molding plate 1 and electrically connected to the connection line 5, and the IPD4 is attached to the connection line 5 at a side away from the chip molding plate 1, so that the antenna 3 and the IPD4 are electrically connected to the chip 11 through the TMV structure 2. The structural layout of the antenna 3 in this embodiment makes the large board fan-out heterogeneous integrated package structure thinner and lighter, can realize high-density and multi-element embedded integration of the chip 11, the antenna 3 and the IPD4 in a smaller volume, and can meet the development requirement of volume miniaturization.
Further, step S40 specifically includes the following steps:
s40a, manufacturing a seed layer on the first surface of the chip plastic sealing plate 1 through a vacuum sputtering method;
s40b, manufacturing a rewiring layer 6 on the seed layer through a pattern electroplating method;
s40c, manufacturing a solder mask layer on the rewiring layer 6, and opening the solder mask layer to expose the pad area of the rewiring layer 6.
The seed layer comprises a titanium metal layer positioned on the first surface of the chip plastic sealing plate 1 and a copper metal layer positioned on the titanium metal layer. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the dielectric layer through the titanium metal layer.
Of course, the seed layer in this embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single-layer structure, a two-layer structure, or a multilayer structure having two or more layers. The material of the seed layer is not limited to the laminated combination of two single metal materials, and may also be a single metal material, or an alloy material, and it is sufficient that the rewiring layer 6 is stably attached to the chip plastic sealing plate 1, which is not described in detail. In this embodiment, the seed layer is not shown in the figure.
The solder mask is made of photosensitive ink materials, the photosensitive ink materials cover the surface of the rewiring layer 6 and the patterned holes of the rewiring layer 6, and the solder mask is formed after curing; and the solder mask layer is provided with a through hole along the thickness direction for exposing the pad area of the rewiring layer 6, and the metal lug 7 is welded with the pad area. The photosensitive ink is used as a solder mask, so that the rewiring layer 6 can be protected, the pad area of the rewiring layer 6 can be exposed through exposure, development and etching, and the process is simplified. In the present embodiment, the solder resist layer is not shown in any of the drawings.
As shown in fig. 5, this embodiment further provides a large board fan-out heterogeneous integrated package structure, which is manufactured by the method for manufacturing the large board fan-out heterogeneous integrated package structure described in the foregoing embodiment.
Example two
The method for manufacturing the TMV structure in this embodiment is substantially the same as that in the first embodiment, except for the opening direction of the blind hole 13.
The preparation method of the TMV structure of this example includes the following steps:
s1, providing the chip molding sealing plate 1 shown in fig. 1, where the chip molding sealing plate 1 has a first surface adjacent to the I/O interface of the chip 11 therein and a second surface opposite to the first surface, a blind hole 13 is formed in a non-chip region of the chip molding sealing plate 1 along a thickness direction of the chip molding sealing plate 1, and an open end of the blind hole 13 is located on the first surface of the chip molding sealing plate 1, as shown in fig. 6;
s2, filling metal filling columns in the blind holes 13, as shown in FIG. 7;
s3, grinding and polishing the second surface of the chip molding sealing plate 1 to make the end of the metal filling pillar away from the side surface flush with the surface of the chip molding sealing plate 1, so as to form the TMV structure 2, as shown in fig. 8.
According to the invention, the TMV structure 2 is prepared by forming the blind hole 13, filling the blind hole 13 and grinding and polishing the blind hole filling column on the chip plastic sealing plate 1, so that the problem of filling gaps of the TMV structure 2 is solved, the virtual filling probability is reduced, and the packaging quality and reliability are improved.
The preparation method of the large-board fan-out heterogeneous integrated package structure based on the preparation method of the TMV structure of this embodiment is substantially the same as that of the first embodiment, and details are not repeated, and the structure of the prepared large-board fan-out heterogeneous integrated package structure is shown in fig. 9.
The method can be used for preparing a large-board fan-out heterogeneous integrated packaging structure with low cost, miniaturization and high integration level, and can improve the reliability of the vertical interconnection structure of the antenna 3 and the IPD4 with the chip 11 through the TMV structure 2.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (7)

1. A preparation method of a large-board fan-out heterogeneous integrated packaging structure is characterized by comprising the following steps:
s10, manufacturing a chip plastic sealing plate by using a plate-level technology;
s20, preparing a TMV structure by adopting the following steps S1-S3,
s1, providing a chip plastic sealing plate, and forming blind holes in a non-chip area of the chip plastic sealing plate along the thickness direction of the chip plastic sealing plate;
s2, filling metal filling columns in the blind holes;
s3, grinding and polishing one side surface of the chip plastic sealing plate far away from the opening of the blind hole to enable one end of the metal filling column far away from the side surface to be flush with the surface of the chip plastic sealing plate to form a TMV structure,
s30, providing an antenna and an IPD, manufacturing a connecting line connected with the TMV structure on one side surface of the chip plastic sealing plate far away from a chip I/O interface inside the chip plastic sealing plate through electroplating, and connecting the antenna and the IPD with the connecting line;
s40, manufacturing a rewiring layer on one side surface of the chip plastic sealing plate close to the chip I/O interface inside the chip plastic sealing plate, and specifically comprising the following steps:
s40a, manufacturing a seed layer on one side of the chip plastic sealing plate, which is flush with the I/O interface of the chip, through a vacuum sputtering method;
s40b, manufacturing the rewiring layer on the seed layer through a pattern electroplating method;
s40c, manufacturing a solder mask layer on the rewiring layer, and opening the solder mask layer to expose a pad area of the rewiring layer;
and S50, providing a metal bump, and implanting the metal bump into the pad area of the rewiring layer.
2. The method for manufacturing the large board fan-out type heterogeneous integrated package structure according to claim 1, wherein in step S1, the blind holes are formed by mechanical drilling or laser drilling.
3. The method for manufacturing a large board fan-out type heterogeneous integrated package structure according to claim 1, wherein in step S1, after the blind holes are opened, the blind holes are further cleaned by plasma or solution to remove residues.
4. The method as claimed in claim 1, wherein in step S2, the blind via holes are filled by physical vapor deposition, electroplating filling, chemical filling or mechanical filling to form the metal filling pillars.
5. The method for manufacturing the large board fan-out heterogeneous integrated package structure according to claim 1, wherein the step S10 specifically includes the following steps:
s10a, providing a carrier plate and a chip, wherein the front surface of the chip faces the carrier plate, and the chip is attached to one side of the carrier plate along the thickness direction of the carrier plate through temporary bonding glue;
s10b, carrying out plastic package on the chip by adopting a plastic package material, and forming a plastic package layer after the plastic package material is solidified;
s10c, removing the carrier plate and the temporary bonding glue to obtain the chip plastic sealing plate.
6. The method as claimed in claim 1, wherein in step S30, the antenna is tightly attached to the surface of the chip molding plate and electrically connected to the connection lines, and the IPD is attached to a side of the connection lines away from the chip molding plate.
7. A large-board fan-out heterogeneous integrated package structure, which is prepared by the preparation method of the large-board fan-out heterogeneous integrated package structure as claimed in any one of claims 1 to 6.
CN201911050901.0A 2019-10-31 2019-10-31 Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof Active CN111106013B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911050901.0A CN111106013B (en) 2019-10-31 2019-10-31 Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911050901.0A CN111106013B (en) 2019-10-31 2019-10-31 Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111106013A CN111106013A (en) 2020-05-05
CN111106013B true CN111106013B (en) 2022-03-15

Family

ID=70420454

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911050901.0A Active CN111106013B (en) 2019-10-31 2019-10-31 Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111106013B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115497931B (en) * 2022-11-17 2023-02-17 广东省大湾区集成电路与***应用研究院 TMV and Fanout-based integrated power module and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683309A (en) * 2011-03-15 2012-09-19 中国科学院微电子研究所 Adapter plate for filling through holes by wafer-level re-balling printing and manufacturing method thereof
CN106997875A (en) * 2016-01-23 2017-08-01 重庆三峡学院 A kind of PoP stack package structures and its manufacture method
CN107818956A (en) * 2016-09-12 2018-03-20 联发科技股份有限公司 Semiconductor packages, package on package and its manufacture method
CN110349944A (en) * 2018-04-04 2019-10-18 英特尔Ip公司 It is fanned out to encapsulation POP mechanical attachment method field

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8476770B2 (en) * 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
TWI571185B (en) * 2014-10-15 2017-02-11 矽品精密工業股份有限公司 Electronic package and method of manufacture
CN108321117A (en) * 2017-12-15 2018-07-24 西安科技大学 TSV pinboards based on metal-oxide-semiconductor and preparation method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683309A (en) * 2011-03-15 2012-09-19 中国科学院微电子研究所 Adapter plate for filling through holes by wafer-level re-balling printing and manufacturing method thereof
CN106997875A (en) * 2016-01-23 2017-08-01 重庆三峡学院 A kind of PoP stack package structures and its manufacture method
CN107818956A (en) * 2016-09-12 2018-03-20 联发科技股份有限公司 Semiconductor packages, package on package and its manufacture method
CN110349944A (en) * 2018-04-04 2019-10-18 英特尔Ip公司 It is fanned out to encapsulation POP mechanical attachment method field

Also Published As

Publication number Publication date
CN111106013A (en) 2020-05-05

Similar Documents

Publication Publication Date Title
US8859912B2 (en) Coreless package substrate and fabrication method thereof
US10957654B2 (en) Semiconductor package and method of manufacturing the same
JP2592038B2 (en) Semiconductor chip mounting method and substrate structure
JP5460388B2 (en) Semiconductor device and manufacturing method thereof
KR101678052B1 (en) Printed circuit board(PCB) comprising one-layer wire pattern, semiconductor package comprising the PCB, electrical and electronic apparatus comprising the package, method for fabricating the PCB, and method for fabricating the package
JP2019512168A (en) Fan-out 3D package structure embedded in silicon substrate
CN110600438A (en) Embedded multi-chip and element SIP fan-out type packaging structure and manufacturing method thereof
JP2010186847A (en) Semiconductor device, method of manufacturing the same, and electronic apparatus
TW201041105A (en) Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
JP2010245259A (en) Electronic device and method of manufacturing the same
JP5147755B2 (en) Semiconductor device and manufacturing method thereof
US10002825B2 (en) Method of fabricating package structure with an embedded electronic component
TW201524283A (en) Printed circuit board and manufacturing method thereof and semiconductor pacakage using the same
JP2017515314A (en) Substrate block for PoP package
TWI781735B (en) Semiconductor package and method for producing same
TW200903763A (en) Inter-connecting structure for semiconductor device package and method of the same
CN110571201A (en) high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof
CN110970397A (en) Stack packaging structure and preparation method thereof
JP4963879B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN111106013B (en) Preparation method of TMV structure, large-board fan-out heterogeneous integrated packaging structure and preparation method thereof
CN112928035B (en) Board-level flip chip packaging structure with electromagnetic shielding function and preparation method thereof
CN211150550U (en) TMV fan-out type packaging structure based on rigid frame
CN112768364A (en) Board-level three-dimensional chip packaging structure and preparation method thereof
KR20160004158A (en) Package substrate
CN210575902U (en) High-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230413

Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225

Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd.

Address before: 528225 room a208-1, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province

Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd.

TR01 Transfer of patent right