CN112751537B - Linear amplifying circuit and analog-to-digital conversion device comprising same - Google Patents

Linear amplifying circuit and analog-to-digital conversion device comprising same Download PDF

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CN112751537B
CN112751537B CN202010453901.1A CN202010453901A CN112751537B CN 112751537 B CN112751537 B CN 112751537B CN 202010453901 A CN202010453901 A CN 202010453901A CN 112751537 B CN112751537 B CN 112751537B
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pair
differential
analog
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outputs
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CN112751537A (en
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付凯
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Shanghai Taorun Semiconductor Co ltd
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Shanghai Taorun Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence

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  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Amplifiers (AREA)

Abstract

The present invention relates to analog electronic circuit technology, and more particularly, to a linear amplifying circuit and an analog-to-digital conversion device including the same. A linear amplification circuit (10) according to one embodiment of the present invention includes: a first differential operational amplification unit (510) comprising a first pair of differential inputs (V IN,VIP) and a first pair of differential outputs (V XN1,VXP1) as inputs to the linear amplification circuit (10); a second differential operational amplification unit (520) comprising a second pair of differential inputs (V XN2,VXP2) and a second pair of differential outputs (V OUTN,VOUTP) as outputs of the linear amplification circuit (10), wherein the first pair of differential outputs (V XN1,VXP1) is coupled to the second pair of differential inputs (V XN2,VXP2); and a feedback unit (530) coupled between the second pair of differential inputs (V XN2,VXP2) and the second pair of differential outputs (V OUTN,VOUTP) to cause the differential voltage swing of the first pair of differential outputs (V XN1,VXP1) to tend to zero.

Description

Linear amplifying circuit and analog-to-digital conversion device comprising same
Technical Field
The present invention relates to analog electronic circuit technology, and more particularly, to a linear amplifying circuit and an analog-to-digital conversion device including the same.
Background
Pipeline analog-to-digital converters (ADCs) are a common analog-to-digital conversion architecture that has the advantages of high conversion rate, small chip area, low power consumption, etc., and are therefore used in a variety of applications including, but not limited to, CCD imaging, ultrasound imaging, digital reception, base stations, digital video, xDSL, cable modems, etc.
Fig. 1 shows a typical pipelined analog-to-digital converter architecture. The pipelined analog-to-digital converter 1 shown in fig. 1 comprises n analog-to-digital conversion stages 11-1 n. At the 1 i-th analog-to-digital conversion stage, a digital signal having m bits is generated by performing a comparison operation on an analog signal from the previous stage (1 i-1-th stage) with a reference signal; on the other hand, the generated digital signal of m bits is digital-to-analog converted to obtain a corresponding analog signal, the corresponding analog signal is subtracted from the analog signal from the previous stage to obtain a residual signal, and the residual signal is amplified and then output to the next (1i+1) th analog-to-digital conversion stage. When the analog signal is sequentially converted by n analog-to-digital conversion stages, a digital signal with m×n bits can be generated.
Fig. 2 is a block diagram of the architecture of one of the analog-to-digital conversion stages of fig. 1. The analog-to-digital conversion stage 20 shown in fig. 2 includes an analog-to-digital converter 210, a digital-to-analog converter 220, an adder 230, and a linear amplification circuit 240. Referring to fig. 2, an input terminal of the analog-to-digital converter 210 is connected to an input terminal of the analog-to-digital conversion stage, an output terminal is connected to an input terminal of the digital-to-analog converter 220, an input terminal of the adder 230 is connected to an input terminal of the analog-to-digital conversion stage and an output terminal of the digital-to-analog converter 220, and an output terminal is connected to an input terminal of the linear amplification circuit 240. In the operating state, the analog signal output by the previous analog-to-digital conversion stage is converted into an m-bit digital signal by the analog-to-digital converter 210, which is output to the digital-to-analog converter 220 on the one hand and to a digital error correction circuit (not shown) on the other hand. At the digital-to-analog converter 220, the m-bit digital signal is digital-to-analog converted to a corresponding analog signal and output to the adder 230. At the adder 230, the analog signal output from the previous analog-to-digital conversion stage is subtracted from the analog signal output from the digital-to-analog converter 220, thereby obtaining a residual signal. The linear amplification circuit 240 amplifies the residual signal to be suitable for signal processing by the next analog-to-digital conversion stage.
The linearity amplifying circuit is an important component in the analog-to-digital conversion stage, and its linearity has a significant influence on the linearity of the whole pipelined ADC. Therefore, improving the linearity of the linear amplification circuit is one of the key factors for improving the performance of the pipelined ADC.
Disclosure of Invention
An object of the present invention is to provide a linear amplifying circuit for an analog-to-digital conversion apparatus, which has advantages of high linearity and the like.
A linear amplification circuit for an analog-to-digital conversion apparatus according to one aspect of the present invention includes:
A first differential operational amplification unit including a first pair of differential inputs and a first pair of differential outputs as inputs of the linear amplification circuit;
A second differential operational amplification unit including a second pair of differential inputs and a second pair of differential outputs as outputs of the linear amplification circuit, wherein the first pair of differential outputs is coupled to the second pair of differential inputs; and
A feedback unit coupled between the second pair of differential inputs and the second pair of differential outputs to cause the differential voltage swing of the first pair of differential outputs to approach zero.
Optionally, in the linear amplifying circuit, the first differential operational amplifying unit includes a first MOS transistor and a second MOS transistor connected in parallel between a power supply and a ground, gates of the first MOS transistor and the second MOS transistor are used as the first pair of differential input ends, and sources of the first MOS transistor and the second MOS transistor are used as the first pair of differential output ends.
Optionally, in the linear amplifying circuit, the first MOS transistor and the second MOS transistor have the same electrical performance parameter.
Optionally, in the linear amplifying circuit, the feedback unit includes:
A first capacitor coupled between one of the second pair of differential outputs and one of the second pair of differential inputs; and
A second capacitor coupled between the other of the second pair of differential outputs and the other of the second pair of differential inputs.
Optionally, in the linear amplifying circuit, the first capacitor and the second capacitor have the same capacitance value.
Optionally, the linear amplifying circuit further comprises an electronic switch disposed between: the sources of the first MOS tube and the second MOS tube are connected with the power supply; the first pair of differential inputs, the first pair of differential outputs, the second pair of differential inputs, and the second pair of differential outputs are between the power supply; and between the second pair of differential inputs and the second pair of differential outputs.
Optionally, the linear amplifying circuit is configured to control the on-off state of the electronic switch under the action of an external signal so as to realize a reset operation, a signal amplifying operation and a signal holding operation.
Optionally, in the linear amplifying circuit, when the reset operation is performed, the first pair of differential input terminals is in a low level state, and the first pair of differential output terminals, the second pair of differential input terminals, and the second pair of differential output terminals are coupled with the power supply to be in a high level state.
Optionally, in the linear amplifying circuit, when the signal amplifying operation is performed, an input signal to be amplified is applied to the first pair of differential output terminals, the second pair of differential input terminals, and the second pair of differential output terminals are coupled to and decoupled from the power supply, and the second pair of differential output terminals are coupled to the second pair of differential input terminals via the feedback unit.
Optionally, in the linear amplifying circuit, when the signal holding operation is performed, the first pair of differential input terminals is in a low level state, the first pair of differential output terminals, the second pair of differential input terminals, and the second pair of differential output terminals are disconnected from the power supply, and the second pair of differential input terminals are disconnected from the second pair of differential output terminals.
It is still another object of the present invention to provide an analog-to-digital conversion apparatus, which has the advantages of high linearity.
An analog-to-digital conversion apparatus according to another aspect of the present invention comprises at least two analog-to-digital conversion stages connected in a cascade, each analog-to-digital conversion stage comprising:
An analog-to-digital converter configured to convert an input analog signal into a digital signal of a set number of bits;
a digital-to-analog converter coupled to the analog-to-digital converter, configured to convert the converted digital signal to an analog signal;
an adder coupled to the analog-to-digital converter and the digital-to-analog converter, configured to subtract the analog signal generated by the conversion of the digital-to-analog converter from the input analog signal to obtain a residual signal; and
A linear amplification circuit as described above having a first pair of differential inputs coupled to the adder and a second pair of differential outputs coupled to inputs of a next analog to digital conversion stage to amplify the residual signal and output the amplified residual signal to the next analog to digital conversion stage.
In one or more embodiments according to the present invention, the linear amplification circuit adopts a structure of a front-back differential operational amplification unit, differential output terminals of the front-stage differential operational amplification unit constitute differential input terminals of a rear-stage differential operational amplification unit, and a feedback unit is provided between the differential input terminals and the differential output terminals of the rear-stage differential operational amplification unit so that the rear-stage differential operational amplification unit is in a closed-loop operational amplification state at the time of signal amplification. This enables the swing of the differential output voltage of the preceding differential operational amplification unit to approach zero, thereby improving the overall linearity of the linear amplification circuit. In addition, the linearity of the electronic switch connected with the differential output terminal is improved due to the lower voltage swing of the electronic switch, and the overall linearity of the linear operational amplifier circuit is further improved. Furthermore, in one or more embodiments according to the present invention, the differential operational amplifying unit of the front and rear stages may have a general circuit structure, so the linear amplifying circuit of the present invention has an advantage of simple structure.
Drawings
To facilitate understanding, identical or similar reference numerals have been used, where possible, to designate identical or similar elements that are common to the figures. The drawings provided are not to be understood as being drawn to scale unless otherwise noted. Furthermore, some details or components may be omitted from the figures for the sake of simplicity.
Fig. 1 shows a typical pipelined analog-to-digital converter architecture.
Fig. 2 is a block diagram of the architecture of one of the analog-to-digital conversion stages of fig. 1.
Fig. 3 shows a typical linear amplifying circuit structure.
Fig. 4 is a signal timing diagram of the linear amplifying unit 30 shown in fig. 3 when a reset operation, a signal amplifying operation, and a signal holding operation are performed.
Fig. 5 is a circuit diagram of a linear amplifying circuit according to a preferred embodiment of the present invention.
Fig. 6 is a signal timing diagram of the linear operational amplifying unit 50 shown in fig. 5 when a reset operation, a signal amplifying operation, and a signal holding operation are performed.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The above-described embodiments are provided to fully convey the disclosure herein and to more fully convey the scope of the invention to those skilled in the art.
In this specification, terms such as "comprising" and "including" mean that there are other elements and steps not directly or explicitly recited in the description and claims, nor does the inventive solution exclude the presence of other elements or steps.
The terms such as "first" and "second" do not denote the order of units in terms of time, space, size, etc. but rather are merely used to distinguish one unit from another.
Fig. 3 shows a typical linear amplifying circuit structure.
The linear operational amplification unit 30 shown in fig. 3 includes a first MOS transistor M 1, a second MOS transistor M 2, a first capacitor C 1, and a second capacitor C 2. As shown in fig. 3, the first MOS transistor M 1, the second MOS transistor M 2, the first capacitor C 1, and the second capacitor C 2 are connected between the power source V REF and the ground. Specifically, the sources of the first MOS transistor M 1 and the second MOS transistor M 2 are connected to the power supply V REF via respective corresponding electronic switches CKR, and are connected to the respective capacitors C 1 and C 2 via respective corresponding electronic switches CKS. The drains of the first MOS transistor M 1 and the second MOS transistor M 2 are connected to the ground. In the linear operational amplification unit 30 shown in fig. 3, the gates of the first MOS transistor M 1 and the second MOS transistor M 2 are used as differential input terminals V IN and V IP, respectively, and the sources are used as differential output terminals V OUTN、VOUTP, respectively.
Fig. 4 is a signal timing diagram of the linear operational amplifying unit 30 shown in fig. 3 when a reset operation, a signal amplifying operation, and a signal holding operation are performed. The operation principle of the linear operational amplification unit 30 is described below with reference to fig. 3 and 4.
Referring to fig. 4, in the reset operation phase, the control signals of the electronic switches CKR and CKS are in a high level state, and thus the electronic switches CKR and CKS are in a closed state. At this time, no signal is input to the gates or the differential input terminals V IN and V IP of the first MOS transistor M 1 and the second MOS transistor M 2, so that the first MOS transistor M 1 and the second MOS transistor M 2 are in the off state. In addition, the source or differential output terminals V OUTN、VOUTP of the first MOS transistor M 1 and the second MOS transistor M 2 are connected to the power source V REF, and thus are pulled up to a high level or reset to a high level state.
Then, the signal amplifying operation stage is entered, the control signal of the electronic switch CKR is in a low level state and the control signal of the electronic switch CKR is in a high level state, so that the electronic switch CKR is in an open state and the electronic switch CKS continues to be in a closed state. At this time, the signals applied to the differential input terminals V IN and V IP change the first MOS transistor M 1 and the second MOS transistor M 2 from the off state to the on state, and the differential output terminal V OUTN、VOUTP is disconnected from the power source V REF. Thus, differential output V OUTN、VOUTP begins to discharge through respective capacitors C 1 and C 2, causing the voltage on differential output V OUTN、VOUTP to begin to drop until the end of the signal amplification phase of operation. When a pair of differential signals is applied to the gates or differential inputs V IN and V IP of the first MOS transistor M 1 and the second MOS transistor M 2, the voltage at the differential output V OUTN、VOUTP drops at different rates or slopes as shown in fig. 4.
The differential output voltage at the end of the signal amplification operation (i.e., the difference between the voltages at the differential output terminals V OUTP and V OUTN) can be calculated based on the parameters of the MOS transistor and the capacitor. Although not required, for convenience, it is assumed here that the first MOS transistor M 1 and the second MOS transistor M 2 have the same electrical performance parameters and the first capacitor C 1 and the second capacitor C 2, and thus the differential output voltage can be determined by:
Vout＝gm×Vi×t/c (1)
Here, V out is a differential output voltage (i.e., V OUTP-VOUTN),gm is a transconductance of the first MOS transistor M 1 and the second MOS transistor M 2), V i is a differential input signal (i.e., a difference V IP-VIN between voltages at differential input terminals), t is a duration of the signal amplifying operation, and C is a capacitance value of the first capacitor C 1 or the second capacitor C 2.
Further, the gain G of the linear operational amplification unit 30 shown in fig. 3 may be determined by:
G＝Vout/Vi＝gm×t/c (2)
After the signal amplifying operation is finished, the signal holding stage is entered. At this stage, the control signals of the electronic switches CKR and CKS are in a low level state, and the electronic switches CKR and CKS are both in an off state. At this time, the signal input is stopped at the gates of the first MOS transistor M 1 and the second MOS transistor M 2 or at the differential input terminals V IN and V IP, and the differential output terminal V OUTN、VOUTP stops discharging via the capacitors C1 and C2, so that the voltage at the differential output terminal V OUTN、VOUTP is not changed any more until the signal holding operation phase is ended.
As shown in fig. 4, from the signal hold operation phase to the reset operation phase, the voltage on the differential output V OUTN、VOUTP is pulled up quickly to a high level.
In the linear operational amplification unit 30 shown in fig. 3, the dynamic operational linearity is inversely related to the swing of the differential output voltage V out. That is, the larger the swing of the differential output voltage V out, the worse the dynamic op-amp linearity and vice versa. This often makes it impossible to achieve both linearity and swing performance requirements of the differential output voltage in the design of the operational amplifier.
In addition, as shown in fig. 3, the source or differential output terminals V OUTN、VOUTP of the first MOS transistor M 1 and the second MOS transistor M 2 are connected to the corresponding capacitor C 1 and capacitor C 2 via respective electronic switches CKS. Since the linearity of the electronic switch CKS is inversely related to the swing of the differential output voltage, the linearity of the linear differential amplifying unit is further deteriorated in case of a large swing, which certainly presents more challenges for the design of the operational amplifier.
In one or more embodiments of the present invention, the linear amplification circuit includes two differential operational amplification units, wherein the differential output terminal of one differential operational amplification unit forms the differential input terminal of the other differential operational amplification unit, and a feedback unit is disposed between the differential input terminal and the differential output terminal of the next differential operational amplification unit so that the swing of the differential output voltage of the previous differential operational amplification unit tends to zero, thereby improving the overall linearity of the linear amplification circuit. Alternatively, each of the above two-stage differential operational amplifying units may employ the circuit configuration shown in fig. 3. Since a differential operational amplification unit of a general structure can be employed, the linear amplification circuit according to one or more embodiments of the present invention has an advantage of simple structure.
Fig. 5 is a circuit diagram of a linear amplifying circuit according to a preferred embodiment of the present invention.
The linear differential amplifying unit 50 shown in fig. 5 adopts a two-stage differential operational amplifying structure including a first differential operational amplifying unit 510, a second differential operational amplifying unit 520, and a feedback unit 530.
Referring to fig. 5, the first differential operational amplification unit 510 as a preceding differential operational amplification stage includes a first MOS transistor M 1 and a second MOS transistor M 2 connected between a power supply V REF and ground. Specifically, the sources of the first MOS transistor M 1 and the second MOS transistor M 2 are connected to the power V REF through the electronic switch CKR, and the drains are connected to the ground. In the linear amplification circuit 50 shown in fig. 5, the gates of the first MOS transistor M 1 and the second MOS transistor M 2 are used as the differential input terminals V IN and V IP, respectively, and the sources are used as the differential output terminals V XN1、VXP1 of the preceding differential operational amplifier stage, respectively.
With continued reference to fig. 5, the second differential operational amplification unit 520, which is a subsequent differential operational amplification stage, includes differential inputs V XN2、VXP2, which are respectively connected to the differential outputs V XP1、VXN1 of the previous differential operational amplification stage. In addition, the differential input terminal V XN2、VXP2 is grounded through the electronic switch CKS (which has the opposite polarity to the electronic switch CKS).
In the linear differential amplifying unit 50 shown in fig. 5, the feedback unit 530 includes a first capacitor C 1 and a second capacitor C 2, wherein the first capacitor C 1 is connected in a feedback loop between the differential input terminal V XN2 and the differential output terminal V OUTP, and the second capacitor C 2 is connected in a feedback loop between the differential input terminal V XP2 and the differential output terminal V OUTN. As shown in fig. 5, an electronic switch CKS is also connected in the feedback loop to control the operation state of the feedback unit 530, and both ends of the first capacitor C 1 and the second capacitor C 2 are connected to the power source V REF via the switch CKR.
Alternatively, but not necessarily, the second differential operational amplifying unit 520 in fig. 5 may also employ the same internal structure as the first differential operational amplifying unit 510.
Fig. 6 is a signal timing diagram of the linear operational amplifying unit 50 shown in fig. 5 when a reset operation, a signal amplifying operation, and a signal holding operation are performed. The operation principle of the linear operational amplification unit 50 is described below with reference to fig. 5 and 6.
Referring to fig. 5, in the reset operation phase, the control signals of the electronic switches CKR and CKS are in a high level state, so the electronic switches CKR and CKS are in a closed state and the electronic switches CKS are in an open state. At this time, the first MOS transistor M 1 and the second MOS transistor M 2 are in the off state due to no signal input on the gate or the differential input terminals V IN and V IP, and the source or the differential output terminal V XN1、VXP1 of the first MOS transistor M1 and the second MOS transistor M2 is connected to the power source V REF, and thus pulled up to the high level or reset to the high level state. Similarly, the differential input terminal V XN2、VXP2 and the differential output terminal V OUTN、VOUTP of the second differential operational amplifier 520 are connected to the power source V REF, and are thus reset to the high state. On the other hand, in the reset operation phase, since both ends of the first capacitor C 1 and the second capacitor C 2 are connected to the power supply V REF, the stored charge is zero.
Then, the signal amplifying operation stage is entered, the control signal of the electronic switch CKR is in a low level state while the control signal of the electronic switch CKR is still in a high level state, the electronic switch CKR and the electronic switches CKS are in an open state and the electronic switch CKS are kept in a closed state. At this stage, a differential signal is applied to the differential input terminals V IN and V IP, thereby causing the first MOS transistor M 1 and the second MOS transistor M 2 to change from the off state to the on state. At the same time, both ends of the differential output terminal V OUTN、VOUTP and the capacitors C 1 and C 2 are disconnected from the power supply V REF, so that the differential output terminal V OUTN、VOUTP starts to charge the respective corresponding capacitors C 1 and C 2, so that the voltage on the differential output terminal V OUTN、VOUTP starts to drop until the end of the signal amplifying operation phase. Similarly, when a pair of differential signals is applied to the gates or differential inputs V IN and V IP of the first MOS transistor M 1 and the second MOS transistor M 2, the voltage at the differential input V OUTN、VOUTP drops at different rates or slopes as shown in fig. 6.
It should be noted that, in the signal amplifying operation stage, the latter differential operational amplifier stage operates in a closed loop operational amplifier state due to the presence of the first capacitor C 1 and the second capacitor C 2 as feedback elements, which causes the differential input terminal V XN2、VXP2 to be clamped around a common initial value as shown in fig. 6, so that the voltage swing of the former differential operational amplifier stage (the difference between the voltages of the differential output terminals V XN1、VXP1) will tend to be zero, thereby obtaining a better dynamic operational linearity. In addition, the electronic switch CKS connected to the differential output V XN1、VXP1 also increases the linearity of the latter due to the lower voltage swing of the former. Thus, the overall linearity of the linear operational amplifier unit shown in fig. 5 is greatly improved.
The charges stored in the first capacitor C 1 and the second capacitor C 2 at the end of the signal amplifying operation, and the differential output voltage of the post differential operational amplifier stage (i.e. the difference between the voltages of the differential output terminals V OUTN and V OUTP) can be calculated according to the parameters of the MOS transistor and the capacitor. Although not required, for convenience, it is assumed here that first MOS transistor M 1 and second MOS transistor M 2 have the same electrical performance parameters, first capacitor C 1 and second capacitor C 2, and thus the stored charge can be determined by:
Q＝(Vout-Vx)×c＝gm×Vi×t (3)
Where Q is the charge stored in the first capacitor C 1 and the second capacitor C 2, V out is the differential output voltage of the post-stage differential operational amplifier stage (i.e., V OUTP-VOUTN),gm is the transconductance of the first MOS transistor M 1 and the second MOS transistor M 2 of the pre-stage differential operational amplifier stage, V x is the differential input signal of the post-stage differential operational amplifier stage (i.e., the difference between the differential input voltages V XP2-VXN2),Vi is the differential input signal of the pre-stage differential operational amplifier stage (i.e., the difference between the differential input voltages V IP-VIN), t is the duration of the signal amplifying operation, and C is the capacitance of the first capacitor C 1 or the second capacitor C 2.
As described above, the differential input signal V x of the post-stage differential operational amplifier stage tends to zero, and thus the differential output voltage of the post-stage differential operational amplifier stage can be determined by:
Vout＝gm×Vi×t/c (4)
further, the gain G of the linear operational amplification unit 50 shown in fig. 5 may be determined by:
G＝Vout/Vi＝gm×t/c (5)
After the signal amplifying operation is finished, the signal holding stage is entered. At this stage, the control signals of the electronic switches CKR and CKS are in a low level state, so that both the electronic switches CKR and CKS are in an open state and the electronic switches CKS are in a closed state. At this time, the signal input is stopped at the gates of the first MOS transistor M 1 and the second MOS transistor M 2 or at the differential input terminals V IN and V IP, and the voltage at the differential output terminal V OUTN、VOUTP is no longer changed until the signal holding operation phase is ended. In addition, the charges Q stored on the first capacitor C 1 and the second capacitor C 2 can be read.
As shown in fig. 6, from the signal hold operation phase to the reset operation phase, the voltage on the differential output V OUTN、VOUTP is pulled up quickly to a high level.
The embodiments described above with reference to the figures can be applied to various pipelined analog-to-digital converters. For example, for the pipelined analog-to-digital converters shown in fig. 1 and 2, the linear amplification circuitry within each analog-to-digital conversion stage may be implemented with the linear amplification circuitry shown in fig. 5. Specifically, when the linear amplification circuit 50 shown in fig. 5 is applied to the pipeline ADC shown in fig. 1 and 2, the differential input terminal V IN、VIP of the preceding stage differential operational amplification stage is coupled to the adder 230 and the differential output terminal V OUTN、VOUTP of the following stage differential operational amplification stage is coupled to the input terminal of the next analog-to-digital conversion stage, thereby amplifying the residual signal output from the adder 230 and outputting the amplified residual signal to the next analog-to-digital conversion stage.
The foregoing has described the principles and preferred embodiments of the present invention. However, the invention should not be construed as being limited to the particular embodiments discussed. The preferred embodiments described above should be regarded as illustrative rather than restrictive, and it should be appreciated that variations may be made in those embodiments by workers skilled in the art without departing from the scope of the present invention as defined by the following claims.

Claims (8)

1. A linear amplification circuit (50) for an analog-to-digital conversion apparatus, comprising:
A first differential operational amplification unit (510) comprising a first pair of differential inputs (V IN,VIP) and a first pair of differential outputs (V XN1,VXP1) as inputs to the linear amplification circuit (50);
A second differential operational amplification unit (520) comprising a second pair of differential inputs (V XN2,VXP2) and a second pair of differential outputs (V OUTN,VOUTP) as outputs of the linear amplification circuit (50), wherein the first pair of differential outputs (V XN1,VXP1) is coupled to the second pair of differential inputs (V XN2,VXP2); and
A feedback unit (530) coupled between the second pair of differential inputs (V XN2,VXP2) and the second pair of differential outputs (V OUTN,VOUTP) to cause the differential voltage swing of the first pair of differential outputs (V XN1,VXP1) to tend to be zero,
Wherein the first differential operational amplification unit (510) comprises a first MOS tube (M 1) and a second MOS tube (M 2) which are connected in parallel between a power supply (V REF) and the ground, the grid electrodes of the first MOS tube (M 1) and the second MOS tube (M 2) are used as the first pair of differential input ends (V IN,VIP), the source electrodes of the first MOS tube (M 1) and the second MOS tube (M 2) are used as the first pair of differential output ends (V XN1,VXP1),
Wherein the electronic switch (CKR, CKS) is further comprised between: the sources of the first MOS tube (M 1) and the second MOS tube (M 2) are arranged between the power supply (V REF); -between the first pair of differential inputs (V IN,VIP), the first pair of differential outputs (V XN1,VXP1), the second pair of differential inputs (V XN2,VXP2) and the second pair of differential outputs (V OUTN,VOUTP) and the power supply (V REF); and between the second pair of differential inputs (V XN2,VXP2) and the second pair of differential outputs (V OUTN,VOUTP),
Wherein the linear amplification circuit (50) is configured to control the on-off state of the electronic switch (CKR, CKS) under the action of an external signal to realize a reset operation, a signal amplification operation and a signal holding operation.
2. The linear amplification circuit (50) of claim 1, wherein the first MOS transistor (M 1) and the second MOS transistor (M 2) have the same electrical performance parameters.
3. The linear amplification circuit (50) of claim 1, wherein the feedback unit (530) comprises:
A first capacitor (C 1) coupled between one of the second pair of differential outputs (V OUTN) and one of the second pair of differential inputs (V XP2); and
A second capacitor (C 2) coupled between the other of the second pair of differential outputs (V OUTP) and the other of the second pair of differential inputs (V XN2).
4. A linear amplification circuit (50) according to claim 3, wherein the first capacitor (C 1) and the second capacitor (C 2) have the same capacitance value.
5. The linear amplification circuit (50) of claim 1, wherein the first pair of differential inputs (V IN,VIP) are in a low state, the first pair of differential outputs (V XN1,VXP1), the second pair of differential inputs (V XN2,VXP2), and the second pair of differential outputs (V OUTN,VOUTP) are coupled to the power supply (V REF) to be in a high state when the reset operation is performed.
6. The linear amplification circuit (50) of claim 1, wherein, in performing the signal amplification operation, the first pair of differential outputs (V XN1,VXP1) are applied with an input signal to be amplified, the first pair of differential outputs (V XN1,VXP1), the second pair of differential inputs (V XN2,VXP2), and the second pair of differential outputs (V OUTN,VOUTP) are coupled to the power supply (V REF) and decoupled from the power supply (V REF), and the second pair of differential outputs (V OUTN,VOUTP) are coupled to the second pair of differential inputs (V XN2,VXP2) via the feedback unit.
7. The linear amplification circuit (50) of claim 1, wherein the first pair of differential inputs (V IN,VIP) are in a low state, the first pair of differential outputs (V XN1,VXP1), the second pair of differential inputs (V XN2,VXP2), and the second pair of differential outputs (V OUTN,VOUTP) are disconnected from the power supply (V REF), and the second pair of differential inputs (V XN2,VXP2) are disconnected from the second pair of differential outputs (V OUTN,VOUTP) when the signal hold operation is performed.
8. An analog to digital conversion apparatus comprising at least two analog to digital conversion stages connected in a cascade, each analog to digital conversion stage comprising:
An analog-to-digital converter configured to convert an input analog signal into a digital signal of a set number of bits;
a digital-to-analog converter coupled to the analog-to-digital converter, configured to convert the converted digital signal to an analog signal;
an adder coupled to the analog-to-digital converter and the digital-to-analog converter, configured to subtract the analog signal generated by the conversion of the digital-to-analog converter from the input analog signal to obtain a residual signal; and
A linear amplification circuit as claimed in any one of claims 1 to 7, in which a first pair of differential inputs (V IN,VIP) is coupled to the adder and a second pair of differential outputs (V OUTN,VOUTP) is coupled to an input of a next analogue to digital conversion stage to amplify the residual signal and output the amplified residual signal to the next analogue to digital conversion stage.
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