CN117978111A - Dynamic amplifier, analog integrator and modulator - Google Patents

Abstract

The invention discloses a dynamic amplifier, an analog integrator and a Sigma-Delta modulator, wherein a dynamic comparator is introduced into the dynamic amplifier, and a common mode is stably output through the connection arrangement of devices of a pre-amplifier and a dynamic latch in the dynamic comparator. Furthermore, a switched capacitor integrator based on the dynamic amplifier is further arranged to realize an analog integrator, and the analog integrator is applied to a Sigma-Delta modulator, so that the power consumption of the whole circuit can be remarkably reduced.

Description

Dynamic amplifier, analog integrator and modulator

Technical Field

The present invention relates to the field of electronic technology, and in particular, to a dynamic amplifier, an analog integrator, and a modulator.

Background

With the continuous development of the mobile internet and the internet of things, the requirements of modern electronic equipment on low power consumption are higher and higher, and the design of integrated circuits is more challenging. The Sigma-Delta analog-to-digital converter (ADC) adopts the over-sampling and noise shaping technology, so that in-band quantization noise is greatly reduced, and the analog-to-digital converter has higher signal-to-noise ratio and better robustness and is widely applied to the fields of sensor signal readout, audio frequency and the like.

In the application field of the internet of things, various sensor devices need battery power supply, so that the sensor devices have longer standby time and prolonged battery life, and there is a strong demand for low-power-consumption high-precision analog-digital converters. Sigma-Delta analog-to-digital converters typically require an operational amplifier (OTA) -based high performance active integrator, most of the power is consumed by the OTA-based switched capacitor integrator, and are poorly compatible with advanced processes. In the nano CMOS era, the design challenges of high performance operational amplifiers are increasing due to voltage degradation, transistor intrinsic gain degradation, and matching characteristics degradation. The switched capacitor integrator is the most important component unit of the Sigma-Delta analog-to-digital converter, and the OTA performance directly affects the overall circuit performance and is also the most important power consumption source of the whole Sigma-Delta analog-to-digital converter.

In order to achieve lower power consumption and to ensure high accuracy of the system, various low power consumption techniques for switched capacitor integrators have been developed in recent years and applied to Sigma-Delta modulators. Common low power technologies are comparator-based switched capacitor circuits, inverter-based integrators, passive integrators, dynamic amplifier-based switched capacitor integrators, and the like. The simple structure of the comparator in combination with the open loop implementation reduces the power consumption of the whole integrator. However, the integrator based on the comparator is limited by noise and mismatch of the comparator, nonideal of a current source and other factors, so that high precision is difficult to realize; by using an inverter as the OTA, a Sigma-Delta modulator with low supply voltage and high power efficiency can be designed. However, this design is relatively sensitive to supply voltage, process, temperature (PVT), requires additional bias circuitry and common mode feedback circuitry, and increases the complexity and power consumption of the circuit design.

Disclosure of Invention

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a dynamic amplifier, an analog integrator and a Sigma-Delta modulator which overcome or at least partially solve the above problems.

In a first aspect, there is provided a dynamic amplifier comprising:

The amplifying circuit and the common mode detection circuit comprise a dynamic comparator;

The amplifying circuit includes: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first current source, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, three first switches and three second switches; the grid electrodes of the first MOS tube and the second MOS tube are respectively a positive phase input end and a negative phase input end of the dynamic amplifier; the first MOS tube is connected with the source electrode of the second MOS tube and is connected with the first current source through a first switch; the other end of the first current source is connected with a reference ground voltage; the drains of the first MOS tube and the second MOS tube are connected with the sources of the third MOS tube and the fourth MOS tube; the grid electrodes of the third MOS tube and the fourth MOS tube are connected with an amplified clock signal; the drains of the third MOS tube and the fourth MOS tube are respectively connected with the negative phase output end and the positive phase output end of the dynamic amplifier through a first switch; the negative phase output end of the dynamic amplifier is connected with a reference ground voltage through the third capacitor; the non-inverting output end of the dynamic amplifier is connected with a reference ground voltage through the fourth capacitor; the negative phase output end and the positive phase output end of the dynamic amplifier are also connected with a reference high voltage through a second switch respectively; the first capacitor is connected in series with the second capacitor, one end of the first capacitor is connected with the negative phase output end of the dynamic amplifier, one end of the second capacitor is connected with the positive phase output end of the dynamic amplifier, and one end of the first capacitor connected with the second capacitor is connected with a reference high voltage through a second switch; the common mode detection circuit further includes: the first AND gate, the second AND gate, the first inverter and the second inverter; the negative phase input end of the dynamic comparator is connected with a first reference level, the positive phase input end of the dynamic comparator is connected with a second reference level, and the second reference level is the level of the connection end of the first capacitor and the second capacitor; the output end of the dynamic comparator and the amplified clock signal pass through the first AND gate phase and then output the clock signal of the first switch; the amplified clock signal is generated by the first inverter and the first switch signal is generated by the second inverter, and the amplified clock signal and the first switch signal are output by the second AND gate and the third switch signal.

Optionally, the pre-amplifier includes a second current source, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the dynamic latch comprises a ninth MOS tube, a tenth MOS tube, a first switching tube, a third inverter, a fourth inverter, a fifth inverter, a third switch and a fourth switch; the gates of the fifth MOS tube and the sixth MOS tube are respectively a positive phase input end and a negative phase input end of the dynamic comparator; the fifth MOS transistor is connected with the source electrode of the sixth MOS transistor and is connected with a reference ground voltage through the second current source; the drains of the fifth MOS tube and the sixth MOS tube are respectively connected with the drains of the seventh MOS tube and the eighth MOS tube; the seventh MOS transistor is connected with the source electrode of the eighth MOS transistor and is connected with a power supply voltage through the first switching transistor; the seventh MOS tube is connected with the grid electrode of the eighth MOS tube, and the grid electrode of the seventh MOS tube is connected with the drain electrode; the ninth MOS transistor is connected with the source electrode of the tenth MOS transistor and is connected with the reference high voltage through the fourth switch; the ninth MOS transistor is connected with the drain electrode of the tenth MOS transistor, is connected with the input end of the third inverter, and is connected with a reference ground voltage through the third switch; the output end of the third inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the fifth inverter, and the output end of the fifth inverter is used as the output end of the dynamic comparator; the grid electrode of the ninth MOS tube is connected with the drain electrode of the sixth MOS tube and is used as the output end of the preamplifier; the fourth switch is in phase opposition to the timing signal of the third switch; the grid electrode of the tenth MOS tube is connected with the output end of the third inverter; and the grid electrode of the first switching tube is connected with the output end of the fourth inverter.

Optionally, the first capacitor and the second capacitor are equal in size; the third capacitor and the fourth capacitor are equal in size.

In a second aspect, there is provided an analog integrator comprising the dynamic amplifier of any one of the first aspects, further comprising: two sampling capacitors, two integrating capacitors, two fifth switches, two sixth switches, two seventh switches and two eighth switches;

The positive phase input end of the analog integrator is connected with the first end of the sampling capacitor through a sixth switch, and the second end of the sampling capacitor is connected with the positive phase input end of the dynamic amplifier through a seventh switch; the first end of the sampling capacitor is also connected with a first common-mode input voltage through one eighth switch, and the second end of the sampling capacitor is also connected with a second common-mode input voltage through the fifth switch; the negative phase input end of the analog integrator is connected with the first end of the sampling capacitor through a sixth switch, and the second end of the sampling capacitor is connected with the negative phase input end of the dynamic amplifier through a seventh switch; the first end of the sampling capacitor is also connected with the first common-mode input voltage through one eighth switch, and the second end of the sampling capacitor is also connected with the second common-mode input voltage through the fifth switch; the two integrating capacitors are respectively connected between the positive phase input end and the negative phase output end of the dynamic amplifier in a bridging mode, and between the negative phase input end and the positive phase output end of the dynamic amplifier.

Optionally, the first common-mode input voltage and the second common-mode input voltage are each one half of the power supply voltage.

Optionally, the analog integrator further includes: an external clock for generating clock signals of the fifth switch, the sixth switch, the seventh switch, and the eighth switch, and generating a reset clock signal and the amplification clock signal of the second switch of the dynamic amplifier; wherein the clock signal of the sixth switch lags the clock signal of the fifth switch, and the clock signal of the eighth switch lags the clock signal of the seventh switch; after the amplified clock signal continuously works on the reset clock signal, the total working interval of the amplified clock signal and the reset clock signal is the same as the working interval of the clock signals of the seventh switch and the eighth switch.

In a third aspect, there is provided a Sigma-Delta modulator comprising:

the signal input end, the signal output end, the first analog adder, the first analog integrator, the second analog adder, the second analog integrator, the third analog adder and the comparator are sequentially connected in series along the direction from the signal input end to the signal output end;

A first input amplifier is arranged between the signal input end and the first analog adder; a second input amplifier is arranged between the signal input end and the second analog adder; a third input amplifier is arranged between the signal input end and the third analog adder; the signal output end is connected with the input end of the digital-to-analog converter; a first feedback amplifier is arranged between the output end of the digital-to-analog converter and the first analog adder; a second feedback amplifier is arranged between the output end of the digital-to-analog converter and the second analog adder; a first output amplifier is arranged between the first analog integrator and the second analog adder; a second output amplifier is arranged between the second analog integrator and the third analog adder;

Wherein the first analog integrator and the second analog integrator are the analog integrator of any one of the second aspects.

Optionally, the amplification factors of the first input amplifier and the first feedback amplifier are opposite numbers; the amplification factors of the second input amplifier and the second feedback amplifier are opposite.

In a fourth aspect, there is provided a Sigma-Delta modulator comprising:

The signal input end, the signal output end, the first analog adder, the first analog integrator, the second analog adder and the comparator are sequentially connected in series along the direction from the signal input end to the signal output end;

A first input amplifier is arranged between the signal input end and the first analog adder; a second input amplifier is arranged between the signal input end and the second analog adder; the signal output end is connected with the input end of the digital-to-analog converter; a first feedback amplifier is arranged between the output end of the digital-to-analog converter and the first analog adder; a first output amplifier is arranged between the first analog integrator and the second analog integrator; a first feedforward amplifier is arranged between the first analog integrator and the second analog adder; a second feedforward amplifier is arranged between the second analog integrator and the second analog adder;

Wherein the first analog integrator and the second analog integrator are the analog integrator of any one of the second aspects.

Optionally, the amplification factors of the first input amplifier and the first feedback amplifier are opposite numbers.

The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:

The dynamic amplifier, the analog integrator and the Sigma-Delta modulator provided by the embodiment of the invention have the advantages that the dynamic comparator is introduced into the dynamic amplifier, and the common mode is stably output through the pre-amplifier and the dynamic latch in the dynamic comparator, compared with the traditional amplifier, the circuit design is simple and convenient, the power consumption can be reduced by about 10 times, the high precision and the low power consumption are realized well, and the performance of the whole chip is improved. Furthermore, a switched capacitor integrator based on the dynamic amplifier is further arranged to realize an analog integrator, and the analog integrator is applied to a Sigma-Delta modulator, so that the power consumption of the whole circuit can be remarkably reduced.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a dynamic amplifier according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a dynamic comparator according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of an analog integrator according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the operation timing of an analog integrator according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a Sigma-Delta modulator according to an embodiment of the present invention;

FIG. 6 is a second circuit diagram of a Sigma-Delta modulator according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

The Sigma-Delta modulator is a key module of a Sigma-Delta analog-to-digital converter (ADC), and the in-band quantization noise is greatly reduced by adopting the over-sampling and noise shaping technology, so that the precision of the analog-to-digital converter is effectively improved. The switched capacitor integrator is the most important component unit of the Sigma-Delta ADC, and the OTA performance directly affects the overall circuit performance and is also the most important power consumption source of the whole Sigma-Delta ADC. In contrast, the dynamic operational amplifier well solves the problems of realizing lower power consumption and ensuring high precision of the system. In a mixed signal circuit, the working mode of the circuit often presents the characteristic of phase dependence, a dynamic circuit is introduced, and the time-varying characteristic of the working point is utilized to optimize the system design. The dynamic amplifier is a dynamic variation of the conventional amplifier, and the operation of the circuit is controlled by a clock circuit and does not always operate. The concrete point of view is as follows: the circuit is turned on in the amplifying stage, and the circuit is turned off after the amplifying is finished, so that static power consumption is not generated. However, the characteristic of the output common mode variation of the dynamic amplifier reduces the linearity thereof, so that it is difficult to well realize high precision and low power consumption, thereby affecting the performance of the whole chip.

The dynamic amplifier provided by the embodiment of the application can effectively reduce the power consumption and improve the linearity, and can be applied to a switched capacitor integrator, so that a Sigma-Delta modulator with better performance and high precision and low power consumption can be realized.

It should be noted that the reference high voltage in the present application may be the power supply voltage VDD, or may be a reference voltage provided after the power supply voltage is converted, which is not limited herein. The reference ground voltage may be the ground GND, or a preset reference voltage provided in the present application, which is not limited herein.

Referring to fig. 1 and 2, the present invention provides a dynamic amplifier, comprising:

An amplifying circuit and a common mode detection circuit, the common mode detection circuit comprising a dynamic comparator 1, the dynamic comparator 1 comprising a pre-amplifier 11 and a dynamic latch 12 as shown in fig. 2.

In an embodiment of the present application, an amplifying circuit of a dynamic amplifier, as shown in (a) in fig. 1, includes:

the MOS transistor comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a first current source I1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, three first switches K1 and three second switches K2; the first capacitor C1 and the second capacitor C2 are used for detecting a common mode level, and the third capacitor C3 and the fourth capacitor C4 are load capacitors. The timing signals controlling the second switch K2 are Φrst, the timing signals controlling the first switch K1 are Φpre, and the timing signals controlling the gates of the third MOS transistor M3 and the fourth MOS transistor M4 are amplified clock signals Φen.

The gates of the first MOS transistor M1 and the second MOS transistor M2 are respectively a positive phase input terminal VIP and a negative phase input terminal VIN of the dynamic amplifier; the sources of the first MOS tube M1 and the second MOS tube M2 are connected, and are connected with the first current source I1 through a first switch K1; the other end of the first current source I1 is connected with the reference ground voltage GND; the drains of the first MOS tube M1 and the second MOS tube M2 are connected with the sources of the third MOS tube M3 and the fourth MOS tube M4;

The gates of the third MOS tube M3 and the fourth MOS tube M4 are connected with an amplified clock signal phi EN; the drains of the third MOS transistor M3 and the fourth MOS transistor M4 are respectively connected with the negative phase output terminal VON and the positive phase output terminal VOP of the dynamic amplifier through a first switch K1;

The negative phase output end VON of the dynamic amplifier is connected with the reference ground voltage GND through the third capacitor C3; the non-inverting output terminal VOP of the dynamic amplifier is connected with the reference ground voltage GND through the fourth capacitor C4; the negative phase output end VON and the positive phase output end VOP of the dynamic amplifier are also respectively connected with a power supply voltage VDD through a second switch K2;

the first capacitor C1 is connected in series with the second capacitor C2, one end of the first capacitor C1 is connected with the negative phase output terminal VON of the dynamic amplifier, one end of the second capacitor C2 is connected with the positive phase output terminal VOP of the dynamic amplifier, and one end of the first capacitor C1 connected with the second capacitor C2 is connected with the power supply voltage VDD through one second switch K2.

In an embodiment of the present application, a common mode detection circuit of a dynamic amplifier, as shown in (b) of fig. 1, includes:

a first AND gate AND1, a second AND gate AND2, a first inverter INV1, AND a second inverter INV2;

The negative phase input end of the dynamic comparator 1 is connected with a first reference level VCM, the positive phase input end of the dynamic comparator is connected with a second reference level VCMP, and the second reference level VCMP is the level of the connection end of the first capacitor C1 and the second capacitor C2; the output end VCMO of the dynamic comparator 1 AND the amplified clock signal Φen are subjected to phase-to-phase connection through the first AND gate AND1 to output a clock signal Φpre of the first switch K1;

the amplified clock signal Φen passes through the clock signal generated by the first inverter INV1 AND the clock signal Φpre of the first switch K1 passes through the clock signal generated by the second inverter INV2, AND the two pass through the second AND gate AND2 AND then output the clock signal Φx of the third switch K3.

In an embodiment of the present application, the dynamic comparator 1 is shown in fig. 2, and includes a pre-amplifier 11 and a dynamic latch 12. The pre-amplifier 11 comprises a second current source I2, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7 and an eighth MOS tube M8; the dynamic latch 12 includes a ninth MOS transistor M9, a tenth MOS transistor M10, a first switching transistor M11, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a third switch K3, and a fourth switch K4;

the gates of the fifth MOS transistor M5 and the sixth MOS transistor M6 are respectively a positive phase input end and a negative phase input end of the dynamic comparator; the fifth MOS tube M5 is connected with the source electrode of the sixth MOS tube M6 and is connected with a reference ground voltage through the second current source; the drains of the fifth MOS transistor M5 and the sixth MOS transistor M6 are respectively connected with the drains of the seventh MOS transistor M7 and the eighth MOS transistor M8;

The seventh MOS tube M7 is connected with the source electrode of the eighth MOS tube M8 and is connected with the power supply voltage through the first switching tube M11; the seventh MOS tube M7 is connected with the grid electrode of the eighth MOS tube M8, and the grid electrode of the seventh MOS tube M7 is connected with the drain electrode, so that the effect of mirror current is realized.

The ninth MOS transistor M9 is connected to the source of the tenth MOS transistor M10, and is connected to the power supply voltage VDD through the fourth switch K4; the drain electrodes of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the input end of the third inverter INV3, and are connected to the reference ground voltage GND through the third switch K3; the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is used as the signal output end of the dynamic comparator 1 to output an output signal VCMO;

The grid electrode of the ninth MOS tube M9 is connected with the drain electrode of the sixth MOS tube M6 and is used as the output end of the pre-amplifier 11; the time sequence signal phiX of the third switch K3 is in phase opposition with the time sequence signal phiX_of the fourth switch K4; the grid electrode of the tenth MOS tube M10 is connected with the output end of the third inverter INV 3; the gate of the first switching tube M11 is connected to the output end of the fourth inverter INV 4.

In particular, compared with the traditional amplifier, the dynamic amplifier can reduce the power consumption by about 10 times, thereby realizing high precision and low power consumption well and improving the performance of the whole chip.

With reference to fig. 1, the working principle of the dynamic amplifier provided by the embodiment of the application is as follows:

in order to reduce power consumption, dynamic amplifiers rely on phase-periodic operation rather than amplifying the input signal constantly. It subdivides the integrating phase of the switched capacitor integrator further into a resetting phase and an amplifying phase, the correlation timing being shown in fig. 4. During resetting, the second switch K2 is turned on under the control of the timing signal Φrst, and the rest of the switches are turned off, so that the circuit is in a reset state, the positive phase output terminal voltage VOP, the negative phase output terminal voltage VON and the voltage VCMP at the common mode detection point are charged to the power supply voltage VDD, and the load capacitors (the third capacitor C3 and the fourth capacitor C4) at the positive phase output terminal and the negative phase output terminal are pulled up to the power supply voltage VDD. During the amplification phase, the second switch K2 is opened under the control of the timing signal Φrst, the other switches are closed, and the third capacitor C3 and the fourth capacitor C4 start to discharge from the power supply voltage VDD to the reference ground voltage GND, but since the input pair of transistors inputs differential signals, the discharge speeds of the third capacitor C3 and the fourth capacitor C4 of the load capacitors at the positive and negative output ends are different, and a voltage difference is generated at the output ends. At this time, the level of the output common mode is continuously reduced, the low-frequency small signal gain of the circuit is started to be established until the first switch K1 is disconnected under the control of the clock signal PhiPRE, the establishment of the output common mode and the differential mode is completed, and the amplifier circuit stops working. Because the discharging speeds of the third capacitor C3 and the fourth capacitor C4 are different, the voltage difference is generated at the output end, and the amplifying function is realized.

In addition, the gates of the third MOS transistor M3 and the fourth MOS transistor M4 continuously operate after the timing signal Φrst of the second switch K2 under the control of the timing signal Φen, wherein when the dynamic amplifier is applied to the analog integrator shown in fig. 3, the total operation interval of the timing signal Φen and the timing signal Φrst coincides with the operation interval of the timing signal Φ2 of the seventh switch K7 or the timing signal Φ2d of the eighth switch K8. Therefore, the reset operation is carried out in the integral phase, and the phenomenon that the transient voltage drops at the output node due to charge sharing can be avoided when the sampling capacitor and the integral capacitor are switched on can be ensured.

The capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are equal, so that the common mode detection can be performed, and the node voltage between the first capacitor C1 and the second capacitor C2, namely the output common mode level VCMP, can be set. As shown in fig. 1 (b), the node voltage is connected to the positive input of the dynamic comparator 1, and the negative input of the dynamic comparator is connected to the preset reference level VCM. When the output common mode level VCMP is greater than the reference level VCM and Φen is high, the generated timing signal Φpre controls all the first switches K1 to be turned on, and the circuit amplifies. When the output common mode level VCMP is lower than the reference level VCM, the generated timing signal PhiPRE controls all the first switches K1 to be disconnected, and the output common mode level VCMP is stabilized near the reference level VCM, so that the linearity of the dynamic amplifier is effectively enhanced, and the performance of the whole chip is improved.

Preferably, the reference level VCM is typically selected to be half of the supply voltage VDD, which maximizes the output signal swing of the dynamic amplifier. Preferably, the third capacitor and the fourth capacitor are equal in size so as to balance the output of the dynamic amplifier, thereby realizing the function of load.

In addition, in order to obtain a higher direct-current voltage gain, four NMOS field effect transistors (a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a fourth MOS transistor M4) form a common-source common-gate structure, so that a gain of about 50dB can be realized. The first current source I1 is used to provide a bias current for the dynamic amplifier to determine the static operating point of the circuit.

As shown in fig. 2, which is a schematic circuit diagram of the dynamic comparator 1 in the common mode detection circuit, the working principle of the dynamic comparator 1 is as follows:

The first stage is a differential to single ended pre-amplifier 11 and the second stage is a dynamic latch 12. The positive phase input end is connected with the output common mode level VCMP, and the negative phase input end is connected with the reference level VCM. In the precharge phase, the third switch K3 is turned on to a high level under the control of the timing signal Φx, which is converted to Φx_ by the inverter INV6, and the drain of the ninth MOS transistor M9 is pulled to Ground (GND) and output to a high level. At this time, the first switching transistor M11 is turned on, and the tail current source of the preamplifier 11 is turned on. When the third switch K3 is turned off to a low level under the control of the timing signal Φx, the gate of the ninth MOS transistor M9 is at a high level, and the ninth MOS transistor M9 and the tenth MOS transistor M10 are turned off, and the output signal VCMO continues to maintain the high level. As the load capacitances (the third capacitance C3 and the fourth capacitance C4) in the amplifying circuit start to discharge, the dynamic amplifier starts to amplify, and the output common mode level VCMP starts to drop. When the output common mode level VCMP is detected to be lower than the reference level VCM, the output signal VCMO is low, so that the gate of the ninth MOS transistor M9 is low, the ninth MOS transistor M9 is turned on, the drain of the ninth MOS transistor M9 is pulled to high, the positive feedback loop formed by the ninth MOS transistor M9, the tenth MOS transistor M10 and the third inverter INV3 makes the gate voltage of the tenth MOS transistor M10 quickly become low, and the gate of the first switching transistor M11 becomes high through the fourth inverter INV4, so that the first switching transistor M11 is turned off, the dynamic comparator 1 does not consume any static power after the turning is completed, which greatly saves power consumption loss. The output signal VCMO of the dynamic comparator 1 also goes low.

In a mixed signal circuit, the working mode of the circuit often presents the characteristic of phase dependence, a dynamic circuit is introduced, and the time-varying characteristic of the working point is utilized to optimize the system design. The dynamic amplifier is a dynamic variation of the conventional amplifier, and the operation of the circuit is controlled by a clock circuit and does not always operate. The concrete point of view is as follows: the circuit is turned on in the amplifying stage, and the circuit is turned off after the amplifying is finished, so that static power consumption is not generated. However, the characteristic of the output common mode variation of the dynamic amplifier reduces the linearity thereof, so that it is difficult to well realize high precision and low power consumption, thereby affecting the performance of the whole chip.

Based on the same inventive concept, referring to fig. 3, the present invention also provides an analog integrator, which includes the dynamic amplifier 301 provided in the foregoing embodiment. The analog integrator further includes:

Two sampling capacitors CS, two integrating capacitors CI, two fifth switches K5, two sixth switches K6, two seventh switches K7 and two eighth switches K8; the timing signal of the fifth switch K5 is controlled to Φ1, the timing signal of the sixth switch K6 is controlled to Φ1d, the timing signal of the seventh switch K7 is controlled to Φ2, and the timing signal of the eighth switch K8 is controlled to Φ2d.

The non-inverting input terminal VIP of the analog integrator is connected with the first terminal of the sampling capacitor CS through a sixth switch K6, and the second terminal of the sampling capacitor CS is connected with the non-inverting input terminal of the dynamic amplifier through a seventh switch K7; the first end of the sampling capacitor CS is further connected to a first common-mode input voltage VCM1 through one eighth switch K8, and the second end of the sampling capacitor CS is further connected to a second common-mode input voltage VCM2 through the fifth switch K5;

the negative phase input end VIN of the analog integrator is connected with the first end of the sampling capacitor CS through a sixth switch K6, and the second end of the sampling capacitor CS is connected with the negative phase input end of the dynamic amplifier through a seventh switch K7; the first end of the sampling capacitor CS is further connected to the first common-mode input voltage VCM1 through one eighth switch K8, and the second end of the sampling capacitor CS is further connected to the second common-mode input voltage VCM2 through the fifth switch K5;

The two integrating capacitors CI are respectively connected across the positive phase input terminal and the negative phase output terminal VON of the dynamic amplifier, and between the negative phase input terminal and the positive phase output terminal VOP of the dynamic amplifier.

With reference to fig. 3 and 4, the working principle of the analog integrator provided by the embodiment of the present application is as follows:

as shown in fig. 4 (fig. 4, abscissa t is time, and ordinate is signal level), the analog integrator further includes:

An external clock Fclk for generating a timing signal Φ1 of the fifth switch K5, a timing signal Φ1d of the sixth switch K6, a timing signal Φ2 of the seventh switch K7, and a timing signal Φ2d of the eighth switch K8, and generating a reset clock signal (i.e., a timing signal Φrst of the second switch K2) and an amplification clock signal (i.e., a timing signal Φen to which gates of the third MOS transistor M3 and the fourth MOS transistor M4 are connected) of the dynamic amplifier;

Wherein the clock signal Φ1d of the sixth switch K6 lags the clock signal Φ1 of the fifth switch K5, and the clock signal Φ2d of the eighth switch K8 lags the clock signal Φ2 of the seventh switch K7; after the amplified clock signal continuously works on the reset clock signal, the total working interval of the amplified clock signal and the reset clock signal phiEN is the same as the working interval of the clock signals of the seventh switch and the eighth switch. Wherein, the first common-mode input voltage VCM1 and the second common-mode input voltage VCM2 are both half of the power supply voltage VDD.

The analog integrator is a switched capacitor integrator, the working state of the analog integrator is divided into a sampling phase and an integrating phase, the sampling phase and the integrating phase are controlled by a group of two-phase non-overlapping clocks (phi 1 and phi 2), wherein a time sequence signal phi 1 controls a fifth switch K5, and a time sequence signal phi 2 controls a seventh switch K7. The sampling phase is controlled by a time sequence signal phi 1, the integrating phase is controlled by a time sequence signal phi 2, and the corresponding phase controls the corresponding switch. The time sequence signal phi 1d lags behind the time sequence signal phi 1, so that the influence of non-ideal factors of the switch on the linearity of the system can be effectively reduced (the time sequence signal phi 2d lags behind the time sequence signal phi 2), wherein the time sequence signal phi 1d controls the sixth switch K6, and the time sequence signal phi 2d controls the eighth switch K8. In the sampling phase, the input signal is stored in the sampling capacitor CS, and the output signal from the previous time is stored in the integrating capacitor CI. During integration, the charge on the sampling capacitor CS is transferred to the integration capacitor CI through the high small-signal low-frequency gain of the dynamic amplifier, so that the integration function is completed.

Based on the same inventive concept, please refer to fig. 5, the present invention further provides a Sigma-Delta modulator, which is a feedback type, comprising:

The signal input end VIN, the signal output end VOUT, the first analog adder A1, the first analog integrator J1, the second analog adder A2, the second analog integrator J2, the third analog adder A3 and the comparator B are sequentially connected in series along the direction from the signal input end to the signal output end;

A first input amplifier b1 is arranged between the signal input end and the first analog adder A1; a second input amplifier b2 is arranged between the signal input end and the second analog adder A2; a third input amplifier b3 is arranged between the signal input end and the third analog adder A3; the signal output end is connected with the input end of the digital-to-analog converter DAC; a first feedback amplifier A1 is arranged between the output end of the digital-to-analog converter DAC and the first analog adder A1; a second feedback amplifier A2 is arranged between the output end of the digital-to-analog converter DAC and the second analog adder A2; a first output amplifier c1 is arranged between the first analog integrator J1 and the second analog adder A2; a second output amplifier c2 is arranged between the second analog integrator J2 and the third analog adder A3;

The first analog integrator J1 and the second analog integrator J2 are analog integrators provided in the foregoing embodiments of the present application.

Preferably, the amplification factors of the first input amplifier b1 and the first feedback amplifier a1 are opposite; the amplification factors of the second input amplifier b2 and the second feedback amplifier a2 are opposite numbers.

The operating principle of the Sigma-Delta modulator shown in fig. 5 is:

After entering from the signal input terminal VIN, the signal is amplified by the first, second and third input amplifiers B1, B2 and B3, and then transmitted to the first analog integrator J1, the second analog integrator J2 and the comparator B, respectively. Meanwhile, the digital signal output at the previous moment is converted into an analog signal corresponding to the digital signal through a digital-to-analog converter DAC, amplified by a first feedback amplifier a1 and a second feedback amplifier a2, and fed back to the first analog integrator J1 and the second analog integrator J2. That is, the input signal VIN and the output signal at the previous moment are subjected to a certain signal processing, and then are superimposed on the first analog adder A1 and the second analog adder A2, and are transmitted to the first analog integrator J1 and the second analog integrator J2 for integration. The integration result of the first analog integrator J1 is amplified by the first output amplifier c1 and then superimposed on the second analog adder A2; the integration result of the second analog integrator J2 is amplified by the second output amplifier c2 and then superimposed on the third analog adder A3. The final output signal will be output from the signal output terminal VOUT.

In the z-domain, the output signal V (z) of the Sigma-Delta modulator can be expressed as:

V(z)＝STF(z)U(z)+NTF(z)E(z)

Where STF (z) is the signal transfer function and NTF (z) is the noise transfer function. For a first order Sigma-Delta modulator, there are:

for an ideal first order Sigma-Delta modulator, the transfer function of its integrator is:

the signal transfer function STF (z) =z ^-1 and the noise transfer function NTF (z) =1-z ^-1.

Thus, the output signal V (z) =z ^-1U(z)+(1-z^-1) E (z) of the Sigma-Delta modulator.

Thus, from fig. 5, the signal transfer function STF (z) of the feedback system can be derived, wherein:

the noise transfer function NTF (z) of the system is:

By setting the proper coefficients [ a, b, c ], the STF (z) can be close to 1, and the NTF (z) is close to 0, so that the high-precision low-power-consumption Sigma-Delta modulator provided by the invention has an excellent noise shaping effect.

Assuming that the input signal of the first analog integrator is X1 and the quantization noise is Q, the result is shown in fig. 5:

X1＝b1VIN-a1VOUT＝b1VIN-a1[STF(z)VIN+NTF(z)Q]＝[b1-a1STF(z)]VIN-a1NTF(z)Q

When a1=b1 (a 1 represents the amplification factor of the first feedback amplifier a1, b1 represents the amplification factor of the first input amplifier b 1):

X1＝a1[1-STF(z)]VIN-b1NTF(z)Q

Because STF (z) is close to 1, NTF (z) is close to 0. Therefore, as long as a1=b1 is made, X1 can be made close to 0, which effectively reduces the requirement for the input-output signal swing of the analog integrator, thereby reducing the design difficulty of the integrator.

Similarly, the amplification factors of the second input amplifier b2 and the second feedback amplifier a2 are equal in size and are opposite in number.

Based on the same inventive concept, please refer to fig. 6, the present invention also provides a Sigma-Delta modulator, which is a feedforward type, comprising:

The signal input end VIN, the signal output end VOUT, the first analog adder A1, the first analog integrator J1, the second analog integrator J2, the second analog adder A2 and the comparator B are sequentially connected in series along the direction from the signal input end to the signal output end;

A first input amplifier b1 is arranged between the signal input end and the first analog adder A1; a second input amplifier b2 is arranged between the signal input end and the second analog adder A2; the signal output end is connected with the input end of the digital-to-analog converter DAC; a first feedback amplifier c1 is arranged between the output end of the digital-to-analog converter DAC and the first analog adder A1; a first output amplifier c2 is arranged between the first analog integrator J1 and the second analog integrator J2; a first feedforward amplifier a1 is arranged between the first analog integrator J1 and the second analog adder A2; a second feedforward amplifier A2 is arranged between the second analog integrator J2 and the second analog adder A2;

The first analog integrator J1 and the second analog integrator J2 are analog integrators provided in the foregoing embodiments of the present application.

Preferably, the amplification factors of the first input amplifier b1 and the first feedback amplifier a1 are opposite to each other.

The operating principle of the Sigma-Delta modulator shown in fig. 6 is:

After entering from the signal input terminal VIN, the signal is amplified by the first and second input amplifiers B1 and B2, and then transmitted to the first analog integrator J1 and the comparator B, respectively. Meanwhile, the output digital signal at the previous moment is converted into an analog signal corresponding to the digital signal through a digital-to-analog converter DAC, amplified by a first feedback amplifier c1 and fed back to the first analog integrator J1. That is, the input signal and the output signal at the previous time are subjected to a certain signal processing, and then are superimposed on the first analog adder A1, and are transmitted to the first analog integrator J1 for integration. The integration result of the first analog integrator J1 is amplified by the first output amplifier and then transmitted to the second analog integrator. In addition, the integration result of the first analog integrator is amplified by the first feedforward amplifier a1 and then superimposed on the second analog adder A2; the integration result of the second analog integrator J2 is amplified by the second feed forward amplifier A2 and then superimposed on the second analog adder A2. The final output signal will be output from the signal output terminal VOUT.

From fig. 6, the Sigma-Delta modulator can be deduced as follows:

/>

a1x1(z)+a2x2(z)+b2VIN＝y(z)

y(z)+E(z)＝VOUT

from b ₂ =1:

The z-domain transfer function of the feed forward system can be derived as:

the modulator of the circuit configuration shown in fig. 6 processes only quantization noise and does not process an input signal, so that the configuration not only reduces the output swing of each integrator, but also reduces harmonic distortion caused by op-amps and switches.

The application adopts the switched capacitor integrator based on the dynamic amplifier to realize the analog integrator, and can obviously reduce the power consumption of the whole circuit.

The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:

The dynamic amplifier, the analog integrator and the Sigma-Delta modulator provided by the embodiment of the invention have the advantages that the dynamic comparator is introduced into the dynamic amplifier, and the common mode is stably output through the connection arrangement of the pre-amplifier and the dynamic latch in the dynamic comparator, compared with the traditional amplifier, the circuit design is simple and convenient, the power consumption can be reduced by about 10 times, the high precision and the low power consumption are realized well, and the performance of the whole chip is improved. Furthermore, a switched capacitor integrator based on the dynamic amplifier is further arranged to realize an analog integrator, and the analog integrator is applied to a Sigma-Delta modulator, so that the power consumption of the whole circuit can be remarkably reduced.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

Claims (10)

1. A dynamic amplifier, comprising:

The amplifying circuit and the common mode detection circuit comprise a dynamic comparator;

The amplifying circuit includes:

the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first current source, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, three first switches and three second switches;

the grid electrodes of the first MOS tube and the second MOS tube are respectively a positive phase input end and a negative phase input end of the dynamic amplifier; the first MOS tube is connected with the source electrode of the second MOS tube and is connected with the first current source through a first switch; the other end of the first current source is connected with a reference ground voltage; the drains of the first MOS tube and the second MOS tube are connected with the sources of the third MOS tube and the fourth MOS tube;

the grid electrodes of the third MOS tube and the fourth MOS tube are connected with an amplified clock signal; the drains of the third MOS tube and the fourth MOS tube are respectively connected with the negative phase output end and the positive phase output end of the dynamic amplifier through a first switch;

the negative phase output end of the dynamic amplifier is connected with a reference ground voltage through the third capacitor; the non-inverting output end of the dynamic amplifier is connected with a reference ground voltage through the fourth capacitor; the negative phase output end and the positive phase output end of the dynamic amplifier are also connected with a reference high voltage through a second switch respectively;

the first capacitor is connected in series with the second capacitor, one end of the first capacitor is connected with the negative phase output end of the dynamic amplifier, one end of the second capacitor is connected with the positive phase output end of the dynamic amplifier, and one end of the first capacitor connected with the second capacitor is connected with a reference high voltage through a second switch;

The common mode detection circuit further includes:

the first AND gate, the second AND gate, the first inverter and the second inverter;

the negative phase input end of the dynamic comparator is connected with a first reference level, the positive phase input end of the dynamic comparator is connected with a second reference level, and the second reference level is the level of the connection end of the first capacitor and the second capacitor; the output end of the dynamic comparator and the amplified clock signal pass through the first AND gate phase and then output the clock signal of the first switch;

the amplified clock signal is generated by the first inverter and the first switch signal is generated by the second inverter, and the amplified clock signal and the first switch signal are output by the second AND gate and the clock signal of the third switch of the dynamic comparator.

2. The dynamic amplifier of claim 1, wherein the dynamic comparator comprises a pre-amplifier and a dynamic latch, the pre-amplifier comprising a second current source, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the dynamic latch comprises a ninth MOS tube, a tenth MOS tube, a first switching tube, a third inverter, a fourth inverter, a fifth inverter, a third switch and a fourth switch;

The gates of the fifth MOS tube and the sixth MOS tube are respectively a positive phase input end and a negative phase input end of the dynamic comparator; the fifth MOS transistor is connected with the source electrode of the sixth MOS transistor and is connected with a reference ground voltage through the second current source; the drains of the fifth MOS tube and the sixth MOS tube are respectively connected with the drains of the seventh MOS tube and the eighth MOS tube;

The seventh MOS transistor is connected with the source electrode of the eighth MOS transistor and is connected with a power supply voltage through the first switching transistor; the seventh MOS tube is connected with the grid electrode of the eighth MOS tube, and the grid electrode of the seventh MOS tube is connected with the drain electrode;

The ninth MOS transistor is connected with the source electrode of the tenth MOS transistor and is connected with the power supply voltage through the fourth switch; the ninth MOS transistor is connected with the drain electrode of the tenth MOS transistor, is connected with the input end of the third inverter, and is connected with a reference ground voltage through the third switch; the output end of the third inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the fifth inverter, and the output end of the fifth inverter is used as the output end of the dynamic comparator;

The grid electrode of the ninth MOS tube is connected with the drain electrode of the sixth MOS tube and is used as the output end of the preamplifier; the fourth switch is in phase opposition to the timing signal of the third switch; the grid electrode of the tenth MOS tube is connected with the output end of the third inverter; and the grid electrode of the first switching tube is connected with the output end of the fourth inverter.

3. The dynamic amplifier of claim 1, wherein:

the first capacitor and the second capacitor are equal in size; the third capacitor and the fourth capacitor are equal in size.

4. An analog integrator comprising the dynamic amplifier of any one of claims 1 to 3, further comprising:

two sampling capacitors, two integrating capacitors, two fifth switches, two sixth switches, two seventh switches and two eighth switches;

The positive phase input end of the analog integrator is connected with the first end of the sampling capacitor through a sixth switch, and the second end of the sampling capacitor is connected with the positive phase input end of the dynamic amplifier through a seventh switch; the first end of the sampling capacitor is also connected with a first common-mode input voltage through one eighth switch, and the second end of the sampling capacitor is also connected with a second common-mode input voltage through the fifth switch;

The negative phase input end of the analog integrator is connected with the first end of the sampling capacitor through a sixth switch, and the second end of the sampling capacitor is connected with the negative phase input end of the dynamic amplifier through a seventh switch; the first end of the sampling capacitor is also connected with the first common-mode input voltage through one eighth switch, and the second end of the sampling capacitor is also connected with the second common-mode input voltage through the fifth switch;

The two integrating capacitors are respectively connected between the positive phase input end and the negative phase output end of the dynamic amplifier in a bridging mode, and between the negative phase input end and the positive phase output end of the dynamic amplifier.

5. An analog integrator as in claim 4, wherein:

the first common-mode input voltage and the second common-mode input voltage are each one-half of the power supply voltage.

6. The analog integrator of claim 4, further comprising:

An external clock for generating clock signals of the fifth switch, the sixth switch, the seventh switch, and the eighth switch, and generating a reset clock signal and the amplification clock signal of the second switch of the dynamic amplifier;

Wherein the clock signal of the sixth switch lags the clock signal of the fifth switch, and the clock signal of the eighth switch lags the clock signal of the seventh switch; after the amplified clock signal continuously works on the reset clock signal, the total working interval of the amplified clock signal and the reset clock signal is the same as the working interval of the clock signals of the seventh switch and the eighth switch.

7. A Sigma-Delta modulator, comprising:

the signal input end, the signal output end, the first analog adder, the first analog integrator, the second analog adder, the second analog integrator, the third analog adder and the comparator are sequentially connected in series along the direction from the signal input end to the signal output end;

A first input amplifier is arranged between the signal input end and the first analog adder; a second input amplifier is arranged between the signal input end and the second analog adder; a third input amplifier is arranged between the signal input end and the third analog adder; the signal output end is connected with the input end of the digital-to-analog converter; a first feedback amplifier is arranged between the output end of the digital-to-analog converter and the first analog adder; a second feedback amplifier is arranged between the output end of the digital-to-analog converter and the second analog adder; a first output amplifier is arranged between the first analog integrator and the second analog adder; a second output amplifier is arranged between the second analog integrator and the third analog adder;

Wherein the first analog integrator and the second analog integrator are the analog integrator of any one of claims 4 to 6.

8. The Sigma-Delta modulator of claim 7, wherein:

The amplification factors of the first input amplifier and the first feedback amplifier are opposite; the amplification factors of the second input amplifier and the second feedback amplifier are opposite.

9. A Sigma-Delta modulator, comprising:

The signal input end, the signal output end, the first analog adder, the first analog integrator, the second analog adder and the comparator are sequentially connected in series along the direction from the signal input end to the signal output end;

A first input amplifier is arranged between the signal input end and the first analog adder; a second input amplifier is arranged between the signal input end and the second analog adder; the signal output end is connected with the input end of the digital-to-analog converter; a first feedback amplifier is arranged between the output end of the digital-to-analog converter and the first analog adder; a first output amplifier is arranged between the first analog integrator and the second analog integrator; a first feedforward amplifier is arranged between the first analog integrator and the second analog adder; a second feedforward amplifier is arranged between the second analog integrator and the second analog adder;

Wherein the first analog integrator and the second analog integrator are the analog integrator of any one of claims 4 to 6.

10. The Sigma-Delta modulator of claim 9, wherein:

The amplification factors of the first input amplifier and the first feedback amplifier are opposite.