CN112751537A - Linear amplifying circuit and analog-to-digital conversion device comprising same - Google Patents

Linear amplifying circuit and analog-to-digital conversion device comprising same Download PDF

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CN112751537A
CN112751537A CN202010453901.1A CN202010453901A CN112751537A CN 112751537 A CN112751537 A CN 112751537A CN 202010453901 A CN202010453901 A CN 202010453901A CN 112751537 A CN112751537 A CN 112751537A
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pair
differential
analog
signal
mos transistor
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CN112751537B (en
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付凯
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Shanghai Taorun Semiconductor Co ltd
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Shanghai Taorun Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence

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  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

The present invention relates to analog electronic circuit technology, and more particularly, to a linear amplifier circuit and an analog-to-digital conversion apparatus including the same. A linear amplification circuit (10) according to an embodiment of the present invention includes: a first differential operational amplification unit (510) comprising a first pair of differential inputs (V) as inputs of the linear amplification circuit (10)IN，VIP) And a first pair of differential outputs (V)XN1，VXP1) (ii) a A second differential operational amplifier unit (520) comprising a second pair of differential inputs (V)XN2，VXP2) And a second pair of differential outputs (V) as outputs of the linear amplification circuit (10)OUTN，VOUTP) Wherein the first pair of differential outputs (V)XN1，VXP1) Coupled to the second pair of differential inputs (V)XN2，VXP2) (ii) a And a feedback unit (530) coupled toAt the second pair of differential inputs (V)XN2，VXP2) And a second pair of differential output terminals (V)OUTN，VOUTP) Such that the first pair of differential outputs (V)XN1，VXP1) Tends towards zero.

Description

Linear amplifying circuit and analog-to-digital conversion device comprising same
Technical Field
The present invention relates to analog electronic circuit technology, and more particularly, to a linear amplifier circuit and an analog-to-digital conversion apparatus including the same.
Background
A pipeline analog-to-digital converter (ADC) is a common analog-to-digital conversion structure, which has the advantages of high conversion rate, small occupied chip area, and low power consumption, and thus is applied to various fields, such as but not limited to CCD imaging, ultrasonic imaging, digital reception, base stations, digital video, xDSL, cable modem, and the like.
Fig. 1 shows a typical pipelined analog-to-digital converter architecture. The pipeline ADC 1 shown in FIG. 1 includes n ADC stages 11-1 n. At the 1 i-th stage analog-to-digital conversion stage, generating a digital signal having m bits by performing a comparison operation on an analog signal from the upper stage (1i-1 st stage) and a reference signal; on the other hand, the generated digital signal with m bits is subjected to digital-to-analog conversion to obtain a corresponding analog signal, the corresponding analog signal is subtracted from the analog signal from the previous stage to obtain a residual signal, and the residual signal is amplified and output to the next (1i +1) th) analog-to-digital conversion stage. When the analog signal is sequentially converted by n analog-to-digital conversion stages, a digital signal with m × n bits can be generated.
Fig. 2 is a block diagram of one of the analog-to-digital conversion stages of fig. 1. The analog-to-digital conversion stage 20 shown in fig. 2 comprises an analog-to-digital converter 210, a digital-to-analog converter 220, an adder 230 and a linear amplification circuit 240. Referring to fig. 2, an input of the analog-to-digital converter 210 is connected to an input of the analog-to-digital conversion stage, an output is connected to an input of the digital-to-analog converter 220, an input of the adder 230 is connected to an input of the analog-to-digital conversion stage and an output of the digital-to-analog converter 220, and an output thereof is connected to an input of the linear amplification circuit 240. In operation, the analog signal output from the previous analog-to-digital conversion stage is converted into an m-bit digital signal by the analog-to-digital converter 210, which is output to the digital-to-analog converter 220 and a digital error correction circuit (not shown). At the digital-to-analog converter 220, the m-bit digital signal is converted into a corresponding analog signal by digital-to-analog conversion and output to the adder 230. At adder 230, the analog signal output from the previous analog-to-digital conversion stage is subtracted from the analog signal output from digital-to-analog converter 220, so as to obtain a residual signal. The linear amplification circuit 240 amplifies the residual signal to be suitable for the next analog-to-digital conversion stage for signal processing.
The linear amplification circuit is an important component in the analog-to-digital conversion stage, and the linearity of the linear amplification circuit has an important influence on the linearity of the whole pipeline ADC. Therefore, improving the linearity of the linear amplifying circuit is one of the key factors for improving the performance of the pipelined ADC.
Disclosure of Invention
An object of the present invention is to provide a linear amplifying circuit for an analog-to-digital conversion apparatus, which has advantages of high linearity and the like.
A linear amplifying circuit for an analog-to-digital conversion apparatus according to an aspect of the present invention comprises:
a first differential operational amplification unit including a first pair of differential input terminals and a first pair of differential output terminals as input terminals of the linear amplification circuit;
a second differential operational amplification unit including a second pair of differential input terminals and a second pair of differential output terminals as output terminals of the linear amplification circuit, wherein the first pair of differential output terminals is coupled to the second pair of differential input terminals; and
a feedback unit coupled between the second pair of differential inputs and the second pair of differential outputs to drive the differential voltage swing of the first pair of differential outputs towards zero.
Optionally, in the linear amplification circuit, the first differential operational amplification unit includes a first MOS transistor and a second MOS transistor connected in parallel between a power supply and a ground, gates of the first MOS transistor and the second MOS transistor serve as the first pair of differential input terminals, and sources of the first MOS transistor and the second MOS transistor serve as the first pair of differential output terminals.
Optionally, in the linear amplification circuit, the first MOS transistor and the second MOS transistor have the same electrical performance parameters.
Optionally, in the linear amplifying circuit, the feedback unit includes:
a first capacitor coupled between one of the second pair of differential outputs and one of the second pair of differential inputs; and
a second capacitor coupled between the other output of the second pair of differential outputs and the other input of the second pair of differential inputs.
Optionally, in the linear amplification circuit, the first capacitor and the second capacitor have the same capacitance value.
Optionally, in the linear amplifying circuit, an electronic switch is further included, which is disposed between: the source electrodes of the first MOS tube and the second MOS tube are connected with the power supply; the first pair of differential inputs, the first pair of differential outputs, the second pair of differential inputs, and the second pair of differential outputs are between the power supply; and between the second pair of differential inputs and the second pair of differential outputs.
Optionally, the linear amplification circuit is configured to control an on-off state of the electronic switch under the action of an external signal to realize a reset operation, a signal amplification operation, and a signal holding operation.
Optionally, in the linear amplification circuit, when the reset operation is performed, the first pair of differential input terminals is in a low level state, and the first pair of differential output terminals, the second pair of differential input terminals, and the second pair of differential output terminals are coupled to the power supply to be in a high level state.
Optionally, in the linear amplification circuit, when the signal amplification operation is performed, the input signal to be amplified is applied to the first pair of differential output terminals, the second pair of differential input terminals, and the second pair of differential output terminals are coupled to the power supply and disconnected from the power supply, and the second pair of differential output terminals are coupled to the second pair of differential input terminals via the feedback unit.
Optionally, in the linear amplification circuit, when the signal hold operation is performed, the first pair of differential input terminals is in a low level state, the first pair of differential output terminals, the second pair of differential input terminals, and the second pair of differential output terminals are disconnected from the power supply, and the second pair of differential input terminals is disconnected from the second pair of differential output terminals.
It is still another object of the present invention to provide an analog-to-digital conversion apparatus having advantages of high linearity, etc.
An analog-to-digital conversion apparatus according to another aspect of the present invention includes at least two analog-to-digital conversion stages connected in a cascade, each analog-to-digital conversion stage including:
an analog-to-digital converter configured to convert an input analog signal into a digital signal of a set bit number;
a digital-to-analog converter coupled to the analog-to-digital converter and configured to convert the converted digital signal to an analog signal;
an adder coupled to the analog-to-digital converter and the digital-to-analog converter, configured to subtract the analog signal generated by the digital-to-analog converter from the input analog signal to obtain a residual signal; and
a linear amplification circuit as described above, having a first pair of differential inputs coupled to the adder and a second pair of differential outputs coupled to inputs of a next analog-to-digital conversion stage to amplify the residue signal and output the amplified residue signal to the next analog-to-digital conversion stage.
In one or more embodiments according to the present invention, the linear amplification circuit adopts a structure of two stages of front and rear differential operational amplification units, a differential output terminal of the front stage differential operational amplification unit constitutes a differential input terminal of the rear stage differential operational amplification unit, and a feedback unit is provided between the differential input terminal and the differential output terminal of the rear stage differential operational amplification unit to make the rear stage differential operational amplification unit in a closed-loop operational amplification state during signal amplification. This enables the swing of the differential output voltage of the preceding stage differential operational amplification unit to approach zero, thereby improving the overall linearity of the linear amplification circuit. In addition, the linearity of the electronic switch connected with the differential output end is improved due to the lower voltage swing of the electronic switch, and the overall linearity of the linear operational amplifier circuit is further improved. Furthermore, in one or more embodiments of the present invention, the differential operational amplifier units in the two stages before and after may adopt a common circuit structure, so the linear amplifier circuit of the present invention has an advantage of simple structure.
Drawings
To facilitate understanding, identical or similar reference numerals have been used, where possible, to designate identical or similar elements that are common to the figures. The drawings provided are not to be understood as being drawn to scale unless otherwise noted. Furthermore, some details or components may be omitted from the drawings for the sake of simplicity.
Fig. 1 shows a typical pipelined analog-to-digital converter architecture.
Fig. 2 is a block diagram of one of the analog-to-digital conversion stages of fig. 1.
Fig. 3 shows a typical linear amplifier circuit configuration.
Fig. 4 is a signal timing diagram of the linear amplification unit 30 shown in fig. 3 when a reset operation, a signal amplification operation, and a signal holding operation are performed.
Fig. 5 is a circuit diagram of a linear amplifying circuit according to a preferred embodiment of the present invention.
Fig. 6 is a signal timing chart of the linear operation amplifying unit 50 shown in fig. 5 when a reset operation, a signal amplifying operation, and a signal holding operation are performed.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The embodiments described above are intended to provide a full and complete disclosure of the present invention to more fully convey the scope of the invention to those skilled in the art.
In the present specification, words such as "comprise" and "comprises" mean that, in addition to elements and steps directly and unequivocally stated in the specification and claims, the technical solution of the present invention does not exclude other elements and steps not directly or unequivocally stated.
Terms such as "first" and "second" do not denote an order of the elements in time, space, size, etc., but rather are used to distinguish one element from another.
Fig. 3 shows a typical linear amplifier circuit configuration.
The linear operational amplifier unit 30 shown in fig. 3 includes a first MOS transistor M1A second MOS transistor M2A first capacitor C1And a second capacitor C2. As shown in fig. 3, the first MOS transistor M1A second MOS transistor M2A first capacitor C1And a second capacitor C2Is connected to a power supply VREFAnd ground. Specifically, the first MOS transistor M1And a second MOS transistor M2Is connected to a power supply V via respective corresponding electronic switches CKRREFAnd connected to the respective capacitor C via the respective electronic switch CKS1And a capacitor C2. First MOS transistor M1And a second MOS transistor M2The drain of the transistor is connected to ground. In the linear operational amplifier unit 30 shown in fig. 3, the first MOS transistor M1And a second MOS transistor M2Are used as differential inputs V, respectivelyINAnd VIPAnd the sources are used as differential output terminals V, respectivelyOUTN、VOUTP。
Fig. 4 is a signal timing chart of the linear operation amplifying unit 30 shown in fig. 3 when a reset operation, a signal amplifying operation, and a signal holding operation are performed. The operation principle of the linear operation amplifying unit 30 is described below with reference to fig. 3 and 4.
Referring to fig. 4, in the reset operation stage, the control signals of the electronic switches CKR and CKS are in a high state, and thus the electronic switches CKR and CKS are in a closed state. At this time, the first MOS transistor M1And a second MOS transistor M2Of the gate or differential input VINAnd VIPHas no signal input, so the first MOS transistor M1And a second MOS transistor M2In the off state. In addition, the first MOS transistor M1And a second MOS transistor M2Source or differential output terminal VOUTN、VOUTPIs connected to a power supply VREFAnd is therefore pulled up or reset to a high state.
Then enter intoIn the signal amplifying operation stage, the control signal of the electronic switch CKR is in a low level state and the control signal of the electronic switch CKR is in a high level state, so that the electronic switch CKR is in an open state and the electronic switch CKS continues to maintain a closed state. At this time, the voltage is applied to the differential input terminal VINAnd VIPThe signal on makes the first MOS transistor M1And a second MOS transistor M2Is changed from off state to on state, and the differential output end VOUTN、VOUTPAnd a power supply VREFAnd (5) disconnecting. Thus, the differential output terminal VOUTN、VOUTPStarting through the respective capacitor C1And C2Discharge is performed, resulting in a differential output VOUTN、VOUTPThe voltage on starts to drop until the end of the signal amplification phase of operation. When in the first MOS transistor M1And a second MOS transistor M2Of the gate or differential input VINAnd VIPWhen a pair of differential signals is applied, as shown in FIG. 4, the differential output terminal VOUTN、VOUTPThe voltage across the capacitor decreases at a different rate or slope.
Differential output voltage at the end of signal amplification operation (i.e., differential output V)OUTPAnd VOUTNThe difference between the voltages) can be calculated according to the parameters of the MOS transistor and the capacitor. Although not necessary, for convenience, it is assumed here that the first MOS transistor M1And a second MOS transistor M2Having the same electrical performance parameters and a first capacitor C1And a second capacitor C2Thus, the differential output voltage may be determined by:
Vout＝gm×Vi×t/c (1)
here VoutIs a differential output voltage (i.e. V)OUTP-VOUTN)，gmIs a first MOS transistor M1And a second MOS transistor M2Transconductance of, ViIs a differential input signal (i.e. the difference V between the voltages at the differential inputs)IP-VIN) T is the duration of the signal amplification operation, C is the first capacitor C1Or a second capacitor C2The capacitance value of (2).
Further, the gain G of the linear operation amplification unit 30 shown in fig. 3 can be determined by the following equation:
G＝Vout/Vi＝gm×t/c (2)
and entering a signal holding phase after the signal amplification operation is finished. At this stage, the control signals of the electronic switches CKR and CKS are in a low level state, and both the electronic switches CKR and CKS are in an off state. At this time, the first MOS transistor M1And a second MOS transistor M2Of the gate or differential input VINAnd VIPUpper stop signal input, differential output VOUTN、VOUTPStops discharging through the capacitors C1 and C2, so that the differential output VOUTN、VOUTPThe voltage on does not change until the end of the signal hold phase of operation.
As shown in fig. 4, the differential output terminal V shifts from the signal holding operation stage to the reset operation stageOUTN、VOUTPThe voltage on is pulled up quickly to a high level.
In the linear operational amplifier unit 30 shown in FIG. 3, the dynamic operational amplifier linearity and the differential output voltage VoutThe swing of (c) is in a negative correlation. That is, the differential output voltage VoutThe larger the swing of (c), the worse the dynamic op-amp linearity and vice versa. This often makes it impossible to compromise the performance requirements of both linearity and swing of the differential output voltage in the design of the operational amplifier.
In addition, as shown in fig. 3, the first MOS transistor M1And a second MOS transistor M2Source or differential output terminal VOUTN、VOUTPConnected to the corresponding capacitor C via a respective electronic switch CKS1And a capacitor C2. Since the linearity of the electronic switch CKS is inversely related to the swing of the differential output voltage, the linearity of the linear differential amplifying unit is further deteriorated when the swing is large, which undoubtedly brings more challenges to the design of the operational amplifier.
In one or more embodiments of the present invention, the linear amplification circuit includes two differential operational amplification units, wherein the differential output terminal of one differential operational amplification unit constitutes the differential input terminal of another differential operational amplification unit, and a feedback unit is disposed between the differential input terminal and the differential output terminal of the next differential operational amplification unit so that the swing of the differential output voltage of the previous differential operational amplification unit tends to zero, thereby improving the overall linearity of the linear amplification circuit. Alternatively, each of the two stages of differential operational amplification units described above may employ the circuit configuration shown in fig. 3. The linear amplification circuit according to one or more embodiments of the present invention has an advantage of simple structure since a differential operational amplification unit of a general structure can be adopted.
Fig. 5 is a circuit diagram of a linear amplifying circuit according to a preferred embodiment of the present invention.
The linear differential amplifying unit 50 shown in fig. 5 employs a two-stage differential operational amplifying structure including a first differential operational amplifying unit 510, a second differential operational amplifying unit 520, and a feedback unit 530.
Referring to fig. 5, the first differential operational amplification unit 510 as a previous stage differential operational amplification stage includes a first differential operational amplification unit connected to a power supply VREFThe first MOS transistor M between the first MOS transistor M and the ground1And a second MOS transistor M2. Specifically, the first MOS transistor M1And a second MOS transistor M2Is connected to a power supply V via an electronic switch CKRREFThe drain is connected to ground. In the linear amplifier circuit 50 shown in fig. 5, the first MOS transistor M1And a second MOS transistor M2Are used as differential inputs V, respectivelyINAnd VIPAnd the sources are respectively used as the differential output ends V of the preceding differential operational amplifier stageXN1、VXP1。
With continued reference to fig. 5, the second differential operational amplification unit 520 as a subsequent differential operational amplification stage includes a differential input terminal VXN2、VXP2Respectively with the differential output terminals V of the preceding differential operational amplifier stageXP1、VXN1Are connected. In addition, a differential input terminal VXN2、VXP2Through electronic switch CKS (the polarity is opposite to that of electronic switch CKS).
In the linear differential amplifying unit 50 shown in fig. 5, the feedback unit 530 includes a first capacitor C1And a second electricityContainer C2Wherein the first capacitor C1Is connected to the differential input end VXN2And a differential output terminal VOUTPIn a feedback loop therebetween, a second capacitor C2Is connected to the differential input end VXP2And a differential output terminal VOUTNIn a feedback loop therebetween. As shown in fig. 5, an electronic switch CKS is further connected to the feedback loop to control the working state of the feedback unit 530, and the first capacitor C1And a second capacitor C2Are connected to a power supply V via a switch CKRREF。
Alternatively, but not necessarily, the second differential operational amplification unit 520 in fig. 5 may also adopt the same internal structure as the first differential operational amplification unit 510.
Fig. 6 is a signal timing chart of the linear operation amplifying unit 50 shown in fig. 5 when a reset operation, a signal amplifying operation, and a signal holding operation are performed. The operation principle of the linear operation amplifying unit 50 is described below with reference to fig. 5 and 6.
Referring to fig. 5, in the reset operation stage, the control signals of the electronic switches CKR and CKS are in a high state, so that the electronic switches CKR and CKS are in a closed state and the electronic switches CKS are in an open state. At this time, the first MOS transistor M1And a second MOS transistor M2Due to the gate or differential input VINAnd VIPNo signal input and in the cut-off state, the sources of the first MOS transistor M1 and the second MOS transistor M2 or the differential output end VXN1、VXP1Is connected to a power supply VREFAnd is therefore pulled up or reset to a high state. Likewise, the differential input terminal V of the second differential operational amplifier unit 520XN2、VXP2And a differential output terminal VOUTN、VOUTPIs connected to a power supply VREFAnd is therefore also reset to a high state. On the other hand, in the reset operation phase, due to the first capacitor C1And a second capacitor C2Are connected to a power supply VREFAnd thus the stored charge is zero.
Then entering a signal amplification operation stage, the control signal of the electronic switch CKR is in a low level state and is in an electronic stateThe control signal of the switch CKR is still in a high level state, the electronic switch CKR and the electronic switches CKS are in an off state and the electronic switches CKS are continuously kept in a closed state. At this stage, a differential signal is applied to the differential input terminals VINAnd VIPThereby resulting in a first MOS transistor M1And a second MOS transistor M2From the off state to the on state. At the same time, the differential output terminal VOUTN、VOUTPAnd a capacitor C1And C2Both ends of which are connected with a power supply VREFDisconnected, thus differentiating the output terminals VOUTN、VOUTPStarting to each corresponding capacitor C1And C2Charging is carried out so that the differential output end VOUTN、VOUTPThe voltage on starts to drop until the end of the signal amplification phase of operation. Similarly, when in the first MOS transistor M1And a second MOS transistor M2Of the gate or differential input VINAnd VIPWhen a pair of differential signals is applied, as shown in FIG. 6, the differential inputs VOUTN、VOUTPThe voltage across the capacitor decreases at a different rate or slope.
It is noted that during the signal amplification phase of operation, the first capacitor C acts as a feedback element1And a second capacitor C2The latter differential operational amplifier stage operates in a closed-loop operational amplifier state, which makes the differential input terminal VXN2、VXP2As shown in fig. 6, are clamped near a common initial value, so that the voltage swing of the pre-stage differential operational amplifier stage (differential output V)XN1、VXP1The difference in voltage) will tend to zero, resulting in better dynamic op-amp linearity. And, in addition, a differential output terminal VXN1、VXP1The connected electronic switch CKS also increases the linearity of the latter due to the lower voltage swing of the former. This significantly improves the overall linearity of the linear operational amplifier shown in fig. 5.
First capacitor C at the end of signal amplification operation1And a second capacitor C2Stored charge, differential output voltage of a subsequent differential operational amplifier stage (i.e. differential output V)OUTNAnd VOUTPThe difference between the voltages) can be calculated according to the parameters of the MOS transistor and the capacitor. Although not necessary, for convenience, it is assumed here that the first MOS transistor M1And a second MOS transistor M2Having the same electrical performance parameters, a first capacitor C1And a second capacitor C2The stored charge can therefore be determined by:
Q＝(Vout-Vx)×c＝gm×Vi×t (3)
where Q is the first capacitor C1And a second capacitor C2Stored charge, VoutDifferential output voltage (i.e. V) of amplifier stage for differential operation of subsequent stageOUTP-VOUTN)，gmThe first MOS transistor M is a preceding differential operational amplifier stage1And a second MOS transistor M2Transconductance of, VxDifferential input signals of amplifier stages for subsequent differential operation (i.e. difference V between voltages at differential inputs)XP2-VXN2)，ViFor differential input signals of preceding differential operational amplifier stages (i.e. difference V between voltages at differential inputs)IP-VIN) T is the duration of the signal amplification operation, C is the first capacitor C1Or a second capacitor C2The capacitance value of (2).
As described above, the differential input signal V of the subsequent differential operational amplifier stagexTending towards zero, the differential output voltage of the subsequent differential operational amplifier stage can therefore be determined by:
Vout＝gm×Vi×t/c (4)
further, the gain G of the linear operation amplification unit 50 shown in fig. 5 can be determined by the following equation:
G＝Vout/Vi＝gm×t/c (5)
and entering a signal holding phase after the signal amplification operation is finished. At this stage, the control signals of the electronic switches CKR and CKS are in a low level state, so that the electronic switches CKR and CKS are both in an open state and the electronic switches-CKS are in a closed state. At this time, the first MOS transistor M1And a second MOS transistor M2Of the gate or differential input VINAnd VIPGo up and stop letterNumber input, differential output VOUTN、VOUTPThe voltage on does not change until the end of the signal hold phase of operation. In addition, the energy is stored in the first capacitor C1And a second capacitor C2The charge Q on can be read.
As shown in fig. 6, the differential output terminal V shifts from the signal holding operation stage to the reset operation stageOUTN、VOUTPThe voltage on is pulled up quickly to a high level.
The embodiments described above with the aid of the figures can be applied to various pipeline analog-to-digital converters. For example for the pipelined analog-to-digital converters shown in fig. 1 and 2, the linear amplification circuit within each analog-to-digital conversion stage may be implemented with the linear amplification circuit shown in fig. 5. Specifically, when the linear amplification circuit 50 shown in fig. 5 is applied to the pipeline ADC shown in fig. 1 and 2, the differential input terminal V of the preceding stage differential operational amplification stageIN、VIPA differential output terminal V coupled to the adder 230 and downstream of the differential operational amplifier stageOUTN、VOUTPCoupled to an input terminal of the next analog-to-digital conversion stage to amplify the margin signal output from the adder 230 and output the amplified margin signal to the next analog-to-digital conversion stage.
The foregoing has described the principles and preferred embodiments of the present invention. However, the invention should not be construed as being limited to the particular embodiments discussed. The preferred embodiments described above should be considered as illustrative and not restrictive, and it should be understood that variations may be made in those embodiments by workers skilled in the art without departing from the scope of the present invention as defined by the following claims.

Claims (11)

1. A linear amplification circuit (10) for an analog-to-digital conversion apparatus, comprising:
a first differential operational amplification unit (510) comprising a first pair of differential inputs (V) as inputs of the linear amplification circuit (10)IN，VIP) And a first pair of differential outputs (V)XN1，VXP1)；
Second difference operationAn amplifying unit (520) comprising a second pair of differential inputs (V)XN2，VXP2) And a second pair of differential outputs (V) as outputs of the linear amplification circuit (10)OUTN，VOUTP) Wherein the first pair of differential outputs (V)XN1，VXP1) Coupled to the second pair of differential inputs (V)XN2，VXP2) (ii) a And
a feedback unit (530) coupled at the second pair of differential inputs (V)XN2，VXP2) And a second pair of differential output terminals (V)OUTN，VOUTP) Such that the first pair of differential outputs (V)XN1，VXP1) Tends towards zero.
2. The linear amplification circuit (10) of claim 1, wherein the first differential operational amplification unit (510) comprises a power supply (V) connected in parallelREF) The first MOS transistor (M) between the first MOS transistor and the ground1) And a second MOS transistor (M)2) The first MOS transistor (M)1) And a second MOS transistor (M)2) As the first pair of differential inputs (V)IN，VIP) The first MOS transistor (M)1) And a second MOS transistor (M)2) As said first pair of differential output terminals (V)XN1，VXP1)。
3. Linear amplification circuit (10) according to claim 2, wherein the first MOS transistor (M) is a MOS transistor1) And the second MOS transistor (M)2) With the same electrical performance parameters.
4. The linear amplification circuit (10) of claim 1, wherein the feedback unit (530) comprises:
a first capacitor (C)1) Coupled to one of the outputs (V) of the second pair of differential outputsOUTN) And one of the inputs (V) of the second pair of differential inputsXP2) To (c) to (d); and
second capacitor (C)2) Coupled to said second pair of differential outputsIs connected to the other output terminal (V)OUTP) And the other input (V) of said second pair of differential inputsXN2) In the meantime.
5. Linear amplification circuit (10) according to claim 4, wherein the first capacitor (C)1) And a second capacitor (C)2) With the same capacitance value.
6. A linear amplification circuit (10) as claimed in claim 2, further comprising an electronic switch (CKR, CKS) arranged between: the first MOS transistor (M)1) And the second MOS transistor (M)2) And the source of (V) and the power supply (V)REF) To (c) to (d); the first pair of differential inputs (V)IN，VIP) The first pair of differential outputs (V)XN1，VXP1) Said second pair of differential inputs (V)XN2，VXP2) And said second pair of differential outputs (V)OUTN，VOUTP) And the power supply (V)REF) To (c) to (d); and said second pair of differential inputs (V)XN2，VXP2) And said second pair of differential outputs (V)OUTN，VOUTP) In the meantime.
7. The linear amplification circuit (10) of claim 6, wherein the linear amplification circuit (10) is configured to control the on-off state of the electronic switches (CKR, CKS) under the action of an external signal to achieve a reset operation, a signal amplification operation and a signal hold operation.
8. Linear amplification circuit (10) according to claim 7, wherein the first pair of differential inputs (V) is arranged to be coupled to the first input of the first pair of differential inputs (V) when performing the reset operationIN，VIP) In a low state, said first pair of differential outputs (V)XN1，VXP1) Said second pair of differential inputs (V)XN2，VXP2) And said second pair of differential outputs (V)OUTN，VOUTP) And the power supply (V)REF) Coupled to be in a high state.
9. Linear amplification circuit (10) according to claim 7, wherein the first pair of differential outputs (V) is arranged to perform the signal amplification operationXN1，VXP1) To which an input signal to be amplified is applied, said first pair of differential outputs (V)XN1，VXP1) Said second pair of differential inputs (V)XN2，VXP2) And said second pair of differential outputs (V)OUTN，VOUTP) And the power supply (V)REF) Is coupled to the power supply (V)REF) Is open and the second pair of differential outputs (V)OUTN，VOUTP) Coupled to the second pair of differential inputs (V) via the feedback unitXN2，VXP2)。
10. Linear amplification circuit (10) according to claim 7, wherein the first pair of differential inputs (V) is such that in performing the signal hold operationIN，VIP) In a low state, said first pair of differential outputs (V)XN1，VXP1) Said second pair of differential inputs (V)XN2，VXP2) And said second pair of differential outputs (V)OUTN，VOUTP) And the power supply (V)REF) Is open, and the second pair of differential inputs (V)XN2，VXP2) And said second pair of differential outputs (V)OUTN，VOUTP) And (5) disconnecting.
11. An analog-to-digital conversion arrangement comprising at least two analog-to-digital conversion stages connected in a cascade, each analog-to-digital conversion stage comprising:
an analog-to-digital converter configured to convert an input analog signal into a digital signal of a set bit number;
a digital-to-analog converter coupled to the analog-to-digital converter and configured to convert the converted digital signal to an analog signal;
an adder coupled to the analog-to-digital converter and the digital-to-analog converter, configured to subtract the analog signal generated by the digital-to-analog converter from the input analog signal to obtain a residual signal; and
a linear amplifying circuit according to any of claims 1-10, wherein the first pair of differential inputs (V) isIN，VIP) A second pair of differential outputs (V) coupled to the adderOUTN，VOUTP) Coupled to an input of a next analog-to-digital conversion stage to amplify the residue signal and output the amplified residue signal to the next analog-to-digital conversion stage.
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