CN112737672B

CN112737672B - Receiving power intensity detection circuit for burst optical receiver

Info

Publication number: CN112737672B
Application number: CN202011516409.0A
Authority: CN
Inventors: 贺诗东; 罗震
Original assignee: Chengdu Tsuhan Science & Technology Co ltd
Current assignee: Chengdu Tsuhan Science & Technology Co ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2023-06-09
Anticipated expiration: 2040-12-21
Also published as: CN112737672A

Abstract

The RSSI Trigger signal sequential logic processing circuit is used for processing an external RSSI Trigger signal into a pulse signal with a fixed width; the image current source circuit is used for realizing APD load current image; the sample hold circuit is used for guaranteeing the stability of the analog signal when converting the analog signal into the digital signal; the analog-to-digital conversion circuit is used for converting an analog signal into a digital signal. The invention can process the RSSI trigger signal provided by the PON MAC chip into the fixed pulse width required by the OLT module, so that the time point of the optical power sampling received by the OLT is not influenced by the external RSSI trigger width and the uplink optical packet length, each sampling is ensured to be the same time, the RSSI sampling precision is improved, no additional circuit is added, the cost is low, the efficiency is high, and the invention is suitable for mass production.

Description

Receiving power intensity detection circuit for burst optical receiver

Technical Field

The invention belongs to the technical field of optical power detection, relates to an optical power intensity detection circuit, and particularly relates to a receiving power intensity detection circuit for a burst optical receiver.

Background

With the increasing business requirements of 4K/8K/VR, the bandwidth requirements of optical communication access networks have increased exponentially, and PON systems in FTTH (Fiber To The Home) networks have also been rapidly developed in recent 10 years. The Passive Optical Network (PON) is ODN (Optical Distribution Network) without any active electronic equipment between OLT (Optical Line Terminal) and ONU (Optical Netwrk Unit), and the PON access network performs transparent transmission on various services, is not interfered by electromagnetic environments such as external lightning, has large transmission capacity, good confidentiality and high reliability, and is widely used in wired access networks.

The PON is a single-fiber bidirectional optical fiber access network with a point-to-multipoint structure, a downlink data stream adopts a broadcasting mode to perform signal transmission, and an uplink data stream adopts a time division multiplexing mode to perform signal transmission, so that the PON has the advantages of high efficiency, large transmission capacity and large coverage area, but because the uplink direction is a burst working mode of time division multiplexing, the PON brings higher challenges to network operation and maintenance difficulty, and in order to monitor the working state of the network in real time, an OLT (optical line terminal) at a local side. It is necessary to be able to remotely monitor the terminal ONU (optical network unit's transmit power) in real time to determine if it is working properly, if an alarm is initiated or a backup channel is started.

In order to improve the network operation and maintenance monitoring precision, the received optical power intensity indication (RSSI) index of the OLT is further improved in the national standard YDT1688.3-2017 (part 3 of the technical condition of an xPON optical transceiver integrated module), the monitoring range is-34 dBm to-8 dBm, the resolution is 0.1dB, the precision is +/-2 dB, and the repeatability is +/-0.5 dB.

In practical network application, because the RSSI Trigger signal provided for the OLT module and used for receiving the burst sampling of the optical power is provided by the external PON MAC chip, the time sequence (width and position) of the RSSI Trigger signal is not controlled by the optical module, and the length of the uplink optical packet is long or short in the RSSI sampling process, so that the RSSI sampling precision is greatly influenced.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a received power strength detection circuit for an OLT burst receiver, which is used for solving the problem of insufficient optical power detection accuracy of the OLT burst receiver in the prior art.

To achieve the above and other related objects, the present invention provides a received power strength detection circuit for an burst optical receiver, characterized in that: comprises an RSSI Trigger signal sequential logic processing circuit, a mirror current source circuit, a sampling hold circuit and an analog-digital conversion circuit, wherein,

the RSSI Trigger signal sequential logic processing circuit is used for processing an external RSSI Trigger signal into a pulse signal with a fixed width;

the RSSI Trigger signal sequential logic processing circuit comprises 3 CLU and 1 Timer, wherein the 3 CLU are CLU1, CLU2 and CLU0 respectively;

the CLU1 comprises: the CLU1 is used for receiving, maintaining and outputting RSSI Trigger signals;

the CLU0 includes: the OR gate is a logic gate and a D trigger, and the CLU0 is used for converting the Timer overflow mark into a pulse signal;

the CLU2 is used for forcing the timer to reload;

the image current source circuit is used for realizing APD load current image;

the sampling hold circuit is used for converting an analog current signal into a voltage signal and ensuring that the voltage signal is kept stable within a certain time;

the analog-to-digital conversion circuit is used for converting an analog signal into a digital signal;

when the RSSI Trigger input signal arrives, the high level is latched into the high level after passing through an OR gate and an AND gate of the CLU1, at the moment, the system clock triggers the D Trigger to output the high level, meanwhile, the high level is kept, a high level signal at the output end of the RSSI Trigger enters the CLU2, the Timer is forced to reload a preset value, when the timing time arrives, the T2OVF at the input end of the OR gate of the CLU0 is set into the high level, the D Trigger of the CLU0 outputs the high level and is latched, the high level is output to the low level through an inverter of the CLU1, the low level is output to enter the D Trigger of the CLU1 after passing through the AND gate, and the RSSI Trigger output end outputs the low level;

through firmware detecting RSSI Trigger Input IO, if the RSSI Trigger input terminal is always high, the D flip-flop of CLU0 is not reset, the output terminal of the D flip-flop of CLU0 is always high, the input terminal of the D flip-flop of CLU1 is always low, the RSSI Trigger output terminal of CLU1 is low, when RSSI Trigger Input Signal is changed to low, the D flip-flop of CLU0 is reset, and the not gate in CLU1 outputs high, so that the RSSI Trigger signal can be processed again.

Preferably, the CLU2 is electrically connected to the CLU1, and the CLU2 outputs the input high level in the RSSI Trigger input signal to the Timer in an inverted manner to complete the preset value of the reload Timer.

Preferably, the mirror current source circuit is composed of two transistors, and the mirror current source circuit comprises 1 input port and two output ports, wherein,

the input port is connected to the APD boost circuit and is used for providing bias voltage required by the work of the APD;

one of the output ports is connected to a load APD and the other output port is used to output mirrored load current to a transimpedance amplifier.

Preferably, the sample-and-hold circuit comprises a transimpedance amplifier, a sampling switch, a sampling capacitor and a voltage follower.

Preferably, the transimpedance amplifier comprises a high bandwidth operational amplifier and a resistor R for converting a current signal into a voltage signal.

Preferably, the non-inverting input end of the operational amplifier is connected to the reference voltage output by the singlechip, the inverting input end of the operational amplifier is connected to the APD load mirror current signal channel output by the current mirror, the output end of the operational amplifier is connected to the sampling switch, the sampling switch is connected to the sampling capacitor C, the sampling capacitor C is connected to the voltage follower, the voltage follower is composed of a high-bandwidth operational amplifier, the sampling capacitor C is connected to the non-inverting input end of the operational amplifier, and the inverting input end and the output end of the operational amplifier are directly connected and then sampled to the ADC port of the MCU for realizing conversion from analog to digital signals.

Preferably, a voltage follower circuit A2 is arranged between the sampling and holding capacitor C and the ADC port of the MCU.

Preferably, the analog-to-digital conversion circuit comprises a 14bit ADC conversion circuit.

As described above, the present invention has the following advantageous effects: by adopting the technical scheme, the RSSI trigger signal provided by the PON MAC chip is processed into the fixed pulse width required by the OLT module by using the logic unit and the timer in the singlechip, the method can ensure that the time point of the optical power sampling received by the OLT is not influenced by the external RSSI trigger width and the uplink optical packet length, ensure that each sampling is at the same time, improve the RSSI sampling precision, and have low cost and high efficiency without adding extra circuits, thereby being suitable for mass production.

Drawings

FIG. 1 is a logic diagram of a sequential processing according to the present invention.

Fig. 2 shows a circuit principle and a block diagram of the structure of the invention.

Description of the embodiments

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

Referring to fig. 1-2, the present invention provides a received power strength detection circuit for an abrupt light receiver, which includes an RSSI Trigger signal sequential logic processing circuit, a mirror current source circuit, a sample hold circuit and an analog-to-digital conversion circuit, wherein,

the RSSI Trigger signal sequential logic processing circuit is used for processing the external RSSI Trigger signal into a pulse signal with a fixed width. The RSSI Trigger signal sequential logic processing circuit comprises 3 CLUs (configurable logic units) and 1 Timer. The 3 CLUs are CLU1, CLU2 and CLU0 respectively, wherein,

the CLU1 is used for receiving, maintaining and outputting RSSI Trigger signals;

CLU2 is used to force timer reloads;

CLU0 is used to convert the Timer overflow flag into a pulse signal.

The image current source circuit is used for realizing APD load current image. The mirror current source circuit is composed of two transistors, and comprises 1 input port and two output ports, wherein,

the input port is connected to an APD (avalanche diode) boost circuit and is used for providing bias voltage required by the work of the APD;

The sample hold circuit is used for converting an analog current signal into a voltage signal and ensuring that the voltage signal is kept stable for a certain time. The sampling hold circuit comprises a transimpedance amplifier, a sampling switch, a sampling capacitor and a voltage follower. Wherein, the liquid crystal display device comprises a liquid crystal display device,

the transimpedance amplifier comprises a high-bandwidth operational amplifier and a resistor R for converting a current signal into a voltage signal.

The non-inverting input end of the operational amplifier is connected to the reference voltage output by the singlechip, the inverting input end of the operational amplifier is connected to an APD load image current signal channel output by the current mirror, the output end of the operational amplifier is connected to the sampling switch, the sampling switch is connected to the sampling and holding capacitor C, when the RSSI trigger out is at a high level, the sampling switch is closed, the capacitor is charged, the RSSI trigger out signal outputs a low level after the charging is completed, and the sampling switch end is opened. After the sampling switch is disconnected, the sampling and holding capacitor C is connected to a voltage follower, the voltage follower is composed of a high-bandwidth operational amplifier, the sampling and holding capacitor C is connected to the in-phase input end of the operational amplifier, the inverting input end and the output end of the operational amplifier are directly connected and then sample is sent to an ADC port of an MCU (single chip microcomputer) for sampling, and the conversion from analog signals to digital signals is realized.

And a voltage follower circuit A2 is arranged between the sampling and holding capacitor C and the ADC port of the MCU. In order to ensure that the capacitor charge can be fully charged in a short time, the capacitance value of the sampling capacitor cannot be too large, otherwise, the condition that the uplink optical signal is ended, the voltage of the sampling capacitor does not reach the maximum value, and undersampling is caused may occur. However, the sampling capacitor cannot be too small, because the RSSI Trigger signal enters the singlechip to Trigger the ADC to interrupt, which has a minimum response time, usually in the uS level, if the capacitor is too small, the charge on the capacitor will be released quickly after the switch K is turned off, and the signal voltage amplitude at the moment of the RSSI interrupt cannot be reflected when the MCU ADC starts sampling. For this purpose, we add a voltage follower circuit A2 between the hold capacitor C and the ADC port of the MCU.

The voltage follower circuit A2 is used for keeping the sampling voltage on the sampling and holding capacitor C for a period of time and inputting the sampling voltage to the ADC port of the MCU, and the interruption response time is prevented from being longer than the discharge time of the sampling and holding capacitor C, so that the sampling voltage is ensured to accurately reflect the optical signal intensity at the interruption moment. The output end of the voltage follower A2 is connected to the ADC sampling port of the MCU.

The analog-to-digital conversion circuit is used for converting an analog signal into a digital signal. The analog-digital conversion circuit comprises a 14-bit ADC conversion circuit, when the RSSI trigger in signal is changed from low to high, the RSSI interrupt sampling inside the MCU is triggered, the ADC circuit starts an ADC conversion function, converts an analog signal into a digital signal, converts the digital signal into a quantization unit according to 0.1uW, and stores the digital signal into a register specified by a protocol.

By adopting the technical scheme, the problems of inconsistent sampling moments and insufficient RSSI precision caused by different uplink optical packet lengths due to the RSSI trigger signal widths provided by different PON MAC chips are successfully avoided, the monitoring precision of +/-1 dB can be realized in the full temperature range, and the monitoring precision of the network operation quality is greatly improved.

In order to better understand and implement the present invention, a detailed description of a schematic circuit diagram is provided below by way of an embodiment of the present invention.

As shown in fig. 1, the RSSI Trigger from the system is connected to the input of RSSI Trigger Input Signal, and is processed by Trigger signal sequential logic processing circuit to generate RSSI Trigger Output Signal with a fixed width.

The Trigger signal sequential logic processing circuit includes three CLUs (configurable logic units). One logic unit CLU1 is connected to an RSSI trigger In signal output by the PON MAC chip, and a D trigger output processed pulse signal In the CLU1 is connected to an RSSI sampling switch for closing the sampling switch to charge a sampling and holding capacitor. CLU2 is used to force timer reloads; CLU0 converts the Timer overflow flag into a pulse signal. Wherein, the liquid crystal display device comprises a liquid crystal display device,

CLU2: when an RSSI Trigger input signal arrives, the CLU2 outputs the input high level in an inverted phase to the Timer, and the Timer starts to reload the preset value of the Timer, and the function setting is completed through the RLFSEL bit of the TMRxCN1 register.

CLU1: the CLU1 comprises three logic gates, or gate, and not gate, and a D flip-flop.

The OR gate in the CLU1 is provided with two input ends, one is an RSSI Trigger input signal, and the other is an RSSI Trigger output feedback signal for latching high level; the AND gate in the CLU1 outputs a high level when an RSSI Trigger input signal arrives, and outputs a low level when a timer overflow signal arrives; the NOT gate in CLU1 is used for setting the output of the AND gate to be low level when the Timer times out; the D flip-flop clock signal in CLU1 uses the system clock, whose output is the RSSI Trigger output signal.

CLU0: CLU0 comprises or gate one logic gate and one D flip-flop.

The OR gate in CLU0 has two input ends, one input end is connected with the pulse signal generated after the timer overflows, the other input end is connected with the feedback signal of the output end of the D Trigger as a latch signal, the D Trigger in CLU0 needs to reset the RST bit of the CLU0CF register through firmware after the power-on initialization or the RSSI Trigger signal processing is finished once, and at the moment, the D Trigger outputs a low level to prepare for the next Trigger.

In this embodiment, the logic signal processing flow is:

when the RSSI Trigger input signal arrives, the high level is latched to be high level after passing through an OR gate and an AND gate of the CLU1, and the system clock triggers the D Trigger to output the high level, and meanwhile the high level is kept. The RSSI Trigger output end has a high level signal to enter the CLU2, the Timer is forced to reload a preset value, when the timing time is up, the OR gate input end T2OVF of the CLU0 is set to a high level, the D Trigger of the CLU0 outputs a high level and is latched at the same time, the high level is output to a low level through the inverter of the CLU1, the low level is output to enter the D Trigger of the CLU1 after the high level passes through the AND gate, and the RSSI Trigger output end outputs a low level. Through the logic processing, a pulse waveform with the width being the timing time length is formed at the D trigger output end of the CLU 1. Thereby realizing the processing of the external RSSI Trigger signal into a pulse signal with fixed width.

When the RSSI Trigger signal is a pulse signal with a longer width, false triggering occurs, thereby affecting the sampling accuracy of the RSSI. In this embodiment, in order to prevent false triggering, the firmware detects RSSI Trigger Input IO input signals, if the RSSI Trigger input terminal is always at a high level, then the D flip-flop of CLU0 is not reset, the output terminal of the D flip-flop of CLU0 is always at a high level, the input terminal of the D flip-flop of CLU1 is always at a low level, and the RSSI Trigger output terminal of CLU1 is at a low level. When RSSI Trigger Input Signal goes low, the D flip-flop of CLU0 is reset and the not gate in CLU1 outputs a high level, so that the RSSI Trigger signal can be processed again.

In this embodiment, the CLU input pins and output pins are not fixed at a certain Port (Port) and a certain Pin (Pin), and other ports and pins can be selected according to application scenarios to perform flexible selection configuration.

In this embodiment, the Timer (Timer) may be selected and configured, for example: timer 0, timer 1, timer 2. Meanwhile, the Timer can set different timing time according to different application scenes, so that pulse output with different widths is obtained.

In this embodiment, the Trigger signal sequential logic processing circuit may not only broaden and output the pulse of the external input narrower RSSI Trigger signal, but also narrow and output the length of the intercepting part of the input wide pulse signal. Meanwhile, the Trigger signal sequential logic processing circuit is not limited to the application of the PON, and can be used for inputting signals with different widths and outputting signals with adjustable widths.

In this embodiment, the implementation of the RSSI Trigger signal sequential logic circuit is implemented on an EFM8LB1 single chip microcomputer of silicon Labs company, or may be implemented in a microcontroller including CLU and Timer with the same structure.

As shown in fig. 2, the working flow of the burst optical receiver received power strength detection circuit is as follows:

the high voltage of the APD generated In the booster circuit is firstly input to an APD chip through a current mirror U3 to form a current load, meanwhile, the other output end B of the mirror current source is connected to a transimpedance amplifier A1 to convert a current signal into a voltage signal, the output current of the end B of the current mirror is 20% of the end A, when the uplink optical power intensity at a certain moment needs to be monitored, an RSSI Trigger In signal is initiated once by an OLT system, the signal is sent to a U1 MCU and is processed into a fixed RSSI Trigger out through the sequential logic (600 ns In the embodiment but not limited to 600ns and can be flexibly adjusted according to different requirements), the signal is sent to an RSSI sampling switch K, the signal is high-level effective, when the RSSI Trigger out signal is high-level, the switch is closed, the sampling capacitor C is charged by the operational amplifier output end, and the capacitor is always ensured to be full by 300ns of charging time. In order to ensure that the capacitor charge can be fully charged in a short time, the capacitance value of the sampling capacitor cannot be too large, otherwise, the condition that the uplink optical signal is ended, the voltage of the sampling capacitor does not reach the maximum value, and undersampling is caused may occur. However, the sampling capacitor cannot be too small, because the RSSI Trigger signal enters the singlechip to Trigger the ADC to interrupt, which has a minimum response time, usually in the uS level, if the capacitor is too small, the charge on the capacitor will be released quickly after the switch K is turned off, and the signal voltage amplitude at the moment of the RSSI interrupt cannot be reflected when the MCU ADC starts sampling. Therefore, a voltage follower circuit A2 is added between the sampling holding capacitor C and the ADC port of the MCU, and the voltage follower circuit A2 has the function of holding the sampling voltage on the capacitor C for a period of time and inputting the sampling voltage to the MCU ADC port, so that the interruption response time is prevented from being longer than the discharge time of the capacitor C, and the sampling voltage is ensured to accurately reflect the light signal intensity at the interruption moment. The output end of the voltage follower A2 is connected to an ADC sampling port of the singlechip, the ADC is 14 bits, the full range is 2.4V, the minimum sampling precision is about 0.146mV and is far higher than the traditional RSSI sampling precision by 0.58V, a group of corresponding relations between input light intensity and a lookup table of the sampling ADC are set in the invention, the relations are written into a register of the singlechip, and the corresponding light power is calculated through the lookup table and reported to a register position specified by a protocol, so that network management personnel can monitor the network operation state in real time.

In summary, the method processes the RSSI trigger signal provided by the PON MAC chip into the fixed pulse width required by the OLT module by using the logic unit and the timer in the singlechip, so that the time point of the optical power sampling received by the OLT is not influenced by the external RSSI trigger width and the uplink optical packet length, each time of sampling is ensured to be the same time, the RSSI sampling precision is improved, no additional circuit is added, the cost is low, the efficiency is high, and the method is suitable for mass production. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

Variations and modifications of the disclosed embodiments may become possible, and alternatives to and equivalents of the embodiments may be apparent to those skilled in the art. It should be clear to those skilled in the art that the RSSI Trigger sequential logic circuit for the burst light sampling circuit of the present invention may be implemented by flexibly combining and configuring registers for each logic unit, and the RSSI Trigger sequential logic circuit, the mirror current source circuit, the sample hold circuit, and the analog-to-digital conversion circuit may be implemented by combination and collocation without departing from the spirit or essential characteristics of the present invention.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A received power strength detection circuit for a burst optical receiver, characterized by: comprises an RSSI Trigger signal sequential logic processing circuit, a mirror current source circuit, a sampling hold circuit and an analog-digital conversion circuit, wherein,

the CLU2 is used for forcing the timer to reload;

the image current source circuit is used for realizing APD load current image;

2. The received power strength detection circuit for an abrupt light receiver according to claim 1, wherein:

and the CLU2 is electrically connected with the CLU1, and the CLU2 outputs the input high level in the RSSI Trigger input signal to the Timer in an inverted mode so as to finish the preset value of the reload Timer.

3. The received power strength detection circuit for a burst optical receiver according to claim 2, wherein: the mirror current source circuit is composed of two transistors, and comprises 1 input port and two output ports, wherein,

4. The received power strength detection circuit for an burst light receiver according to claim 3, wherein: the sampling hold circuit comprises a transimpedance amplifier, a sampling switch, a sampling capacitor and a voltage follower.

5. The received power strength detection circuit for an burst light receiver as claimed in claim 4, wherein: the transimpedance amplifier comprises a high-bandwidth operational amplifier and a resistor R for converting a current signal into a voltage signal.

6. The received power strength detection circuit for an burst light receiver as claimed in claim 5, wherein: the non-inverting input end of the operational amplifier is connected to the reference voltage output by the singlechip, the inverting input end of the operational amplifier is connected to an APD load image current signal channel output by the current mirror, the output end of the operational amplifier is connected to the sampling switch, the sampling switch is connected to the sampling capacitor C, the sampling capacitor C is connected to the voltage follower, the voltage follower is composed of a high-bandwidth operational amplifier, the sampling capacitor C is connected to the non-inverting input end of the operational amplifier, and the inverting input end and the output end of the operational amplifier are directly connected and then sample is sent to an ADC port of the MCU for sampling, so that the conversion from analog to digital signals is realized.

7. The received power strength detection circuit for an burst light receiver as claimed in claim 6, wherein: and a voltage follower circuit A2 is arranged between the sampling and holding capacitor C and the ADC port of the MCU.

8. The received power strength detection circuit for an abrupt light receiver according to claim 1, wherein: the analog-to-digital conversion circuit includes a 14bit ADC conversion circuit.