CN102325281B - Device and method for processing received signal strength indicator (RSSI) Trigger time sequence of optical module of optical line terminal (OLT) by utilizing programmable logic cell - Google Patents
Device and method for processing received signal strength indicator (RSSI) Trigger time sequence of optical module of optical line terminal (OLT) by utilizing programmable logic cell Download PDFInfo
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Abstract
The invention discloses a device and a method for processing a received signal strength indicator (RSSI) Trigger time sequence of an optical module of an optical line terminal (OLT) by utilizing a programmable logic cell. The processing device comprises the programmable logic cell, a sampling holding circuit, an analogue-to-digital converter and a digital signal processing unit. The processing method comprises a starting step, an inverting step, a normal phase OR step, a normal phase AND step, a normal phase and inverted AND step and a finishing step. By the processing device and the method, different RSSI Trigger time sequences can be unified to meet different requirements of different clients on the RSSI Trigger time sequences, and simultaneously the same optical module of the OLT can be used, thereby reducing production and management cost and improving the compatibility of similar optical modules.
Description
Technical field
The present invention relates to optical communication field, relate in particular under a kind of optical-fiber network time division multiplexing, to triggering the sequential of the RSSI Trigger signal of luminous power sampling, the apparatus and method of utilizing programmable logic cells to process.
Background technology
Traditional communication field transmission line used is all copper core cable, and efficiency of transmission is low, and anti-electromagnetic interference capability is poor.Due to optical fiber, to have efficiency of transmission high, the features such as anti-electromagnetic interference capability is strong, therefore, along with the raising to communications rate requirement, and the lifting of modern manufacturing process declines fiber manufacturing cost, modern communications field more and more utilizes optical fiber to carry out the transmission of information.Optical communication network is connected to the Access Network of user terminal, according to whether having accessed active device, can be divided into AON (Active Optical Network, active optical network) and PON (Passive Optical Network, EPON).Because PON has easy maintenance, the feature of being convenient to installation and expanding, has obtained using widely, and becomes the standard criterion of International Telecommunications Union.
A PON is conventionally by an OLT (Optical Line Terminal who is positioned at central office, optical line terminal), several optical distribution networks that are positioned at the ONU (Optical Network Unit, optical network unit) of user side and are positioned between the two form.In the time of data downstream, OLT is broadcast to each ONU by downlink data packet, and each ONU mates separately according to the address information in downlink data packet.In the time of data uplink, due to upstream data, often to measure little and temporal regularity is not high, existing way is to allow each ONU with time division multiplexing work.Due to fibre circuit, have the possibility of external interference, this just needs OLT to judge certain light signal that it receives, and is the upward signal from the burst of certain ONU simultaneously, or is one section of external interference.General way is that the upward signal of this burst is carried out to the Indicator based on RSSI(Received Signal Strength, received signal strength indicator, be used for judging external interference) luminous power sampling, the received optical power value obtaining is judged, if in appropriate threshold range, just think one section of upward signal, according to corresponding numerical value, adjust threshold level simultaneously.
As shown in Figure 1, a typical sample circuit consists of sampling hold circuit, analog to digital converter and digital signal processing unit.Wherein sampling hold circuit, except receiving the upward signal detecting for luminous power, also will receive and be used for starting this sample circuit from OLT system, triggers the RSSI Trigger signal of sampling, i.e. received signal strength indicator sampling trigger signal.Sample circuit, under the control of this RSSI Trigger, starts or stops luminous power sampling.
According to IEEE802.3ah agreement, a complete PON upward signal comprises standardized reception settling time and CDR (Clock Data Recovery, clock and data recovery) locking time general 400ns, add minimum sampling time 600ns, actual light bag be about 1us for a long time.This just require OLT optical module 1us light bag for a long time in, complete the capacitor charging in sampling hold circuit, enter the process that sampling keeps.
The regulation that the < < EPON of China Telecom establishes specification requirement V2.1 > > have been increased on the basis of V2.0 version " received optical power of OLT detects ": " OLT should support the measurement function of the up average light power from each ONU that it is received, at-30dBm to the be not inferior to ± 1dB of certainty of measurement within the scope of-10dBm, minimum measurement is not more than 600ns sample time ", minimum message length and monitoring precision have only been stipulated, but but clearly do not stipulate for the RSSI Trigger that triggers OLT sampling, the present situation that this has just caused each system manufacturer to define separately.Except light packet length is in 1us, sampling precision requires to accomplish +/-1dB, meet outside protocol requirement, each system manufacturer is for cost or ASIC (Application Specific Intergrated Circuits, application-specific integrated circuit (ASIC)) consideration of the factors such as restriction of this class user specific (special) requirements, sequential definition to RSSI Trigger is different, mainly contains following two kinds:
A kind of is the sequential of growing.Conventionally the sample rate that is integrated in the analog to digital converter of microprocessor internal only has tens to hundreds of KSPS (Kilo Samples per Second, sampling per second thousand times), and speed is up to hundreds of MSPS(sampling per second 1,000,000 times) the independent analog to digital converter price in outside extremely expensive, can greatly increase cost, volume and the circuit complexity of whole optical module.Therefore, some system manufacturer and optical module manufacturer cooperatively interact, defined longer RSSI Trigger sequential, be that sample circuit outside provides sufficiently long RSSI Trigger sequential, as shown in Figure 2, RSSI Trigger postpones probably in 850ns (nanosecond) left and right, and RSSI Trigger width is 10us (microsecond), in order to meet the sample rate requirement of the integrated analog to digital converter of microprocessor internal that optical module uses.
Another kind is shorter sequential.Some system manufacturer is due to because can marry again optical module manufacturer by the cost of high-speed AD converter, or be subject to user's specific (special) requirements and the restriction of ASIC customized, and defined shorter RSSI Trigger sequential, as shown in Figure 3, RSSI Trigger delay is probably in 250ns left and right, and RSSI Trigger width only has 600ns.
For OLT optical module manufacturer, because different OLT system manufacturer define different RSSI Trigger sequential, if will do for different clients the optical module that meets different RSSI Trigger sequential, will customize different hardware designs, what have even has several widely different hardware schemes, research and development drop into, operation is got the raw materials ready, project and the management of product will become very difficult, with high costs, also can cause the similar product due to the difference of single index simultaneously, produce incompatible on hardware.
Therefore, in the urgent need to a kind of RSSI Trigger sequential that can provide system in optical module inside, process, make the sequential after processing consistent as far as possible, thereby produce the requirement that can meet each system manufacturer, the unified optical module of hardware again, so a kind of technical scheme.
Summary of the invention
For the problems referred to above, thereby being to provide, first object of the present invention a kind ofly can process the processing unit that obtains the unified RSSI Trigger sequential that is applicable to the integrated digital to analog converter of microprocessor internal to different RSSI Trigger sequential.
For the problems referred to above, thereby second object of the present invention is to provide a kind of processing method that obtains unified RSSI Trigger sequential that different RSSI Trigger sequential is processed.
First object of the present invention is achieved through the following technical solutions:
A kind of processing unit of programmable logic cells to OLT optical module RSSI Trigger sequential that utilize, comprise sampling hold circuit, analog to digital converter, digital signal processing unit, sampling hold circuit is for receiving optical signals and RSSI Trigger, analog to digital converter is for being converted into digital signal by analog quantity, digital signal processing unit is for calculating received optical power value according to digital signal, and its key is:
Also comprise programmable logic cells, the RSSI Trigger before this programmable logic cells reception & disposal, processes it, and the RSSI Trigger after processing is outputed to sampling hold circuit and analog to digital converter simultaneously;
Described programmable logic cells, comprise inverter or door, register, first and door and second with; RSSI Trigger send to simultaneously inverter input and or door one end input; Inverter output inversion signal to the second and door one end input; Or the reception first of door other end input and the positive and the signal that feed back, or door output positive or signal to the first and one end input; First with a door other end input receiving register signal, first with door also by positive with signal outputs to or door other end input and second and an other end input; Second exports the RSSI Trigger signal after processing with door.
A preferred embodiment according to the present invention, described programmable logic cells, also comprise the second inverter, RSSI Trigger after this second inverter reception & disposal, export the RSSI Trigger after anti-phase processing, applicable to the occasion of the analog switch high level conducting in sampling hold circuit, applied widely.
Another preferred embodiment according to the present invention, described inverter or door, register, first and door, second with and the second inverter, the microprocessor chip by model for Aduc7020 or Aduc7023 provides.This type of microprocessor chip is inner integrated programmable logic array, integrated level is high, has reduced industrial cost.
Another preferred embodiment according to the present invention, described sampling hold circuit, comprises that model is the image current source chip of MAX4007 and the analog switch that model is TS5A4595.This class chip technology is ripe, and stability is high, can guarantee the safe operation of circuit.
Second object of the present invention is achieved through the following technical solutions:
Utilize the processing method of programmable logic cells to OLT optical module RSSI Trigger sequential, its key is, comprises the following steps:
S1: start step: register original levels is set to 0; RSSI Trigger is divided into two-way ，Yi road and by step S2, processes, process by step S3 on another road;
S2: anti-phase road step: to RSSI Trigger negate, obtain inversion signal;
S3: positive or step: the positive feeding back in RSSI Trigger and step S4 and signal are carried out to logic OR computing, obtain positive or signal;
S4: positive and step: positive or signal are carried out to logic and operation with the register signal being stored in register, obtain positive and signal; Wherein, when sample circuit is received sample enable signal, register level is set to 1;
S5: just anti-phase and step: inversion signal and positive and signal are carried out to logic and operation, the RSSI Trigger after being processed;
S6: end step: after analog to digital converter has been sampled, register level is set to 0 again.
A preferred embodiment according to the present invention, also comprise the anti-phase step of output: to the RSSI Trigger negate after processing, obtain the RSSI Trigger after anti-phase processing, applicable to the occasion of the analog switch high level conducting in sampling hold circuit, applied widely.
Beneficial effect of the present invention is:
The programmable logic cells that utilizes of the present invention carries out that processing by increase programmable logic cells in common sample circuit to the RSSI Trigger of different sequential to the processing unit of OLT optical module RSSI Trigger sequential, make it unified sequential of sampling for being applicable to the integrated analog to digital converter of microprocessor internal, use same hardware configuration to meet different sequential demands, industrial cost and the circuit complexity of optical module have been reduced, the compatibility of similar optical module is improved, facilitate optical module manufacturer to produce and the management of flow process simultaneously, can also after completing, product design accomplish quick response for client's new demand, avoided again trouble development or change material.
Of the present invention utilize programmable logic cells to the processing method of OLT optical module RSSI Trigger sequential by the method for the RSSI Trigger of different sequential being processed to the RSSI Trigger that makes it to obtain unified sequential is provided, can facilitate this area engineering staff to adopt the hardware designs being equal to complete the flow process of unified RSSI Trigger sequential, and then reduction optical module industrial cost, improve optical module compatible, reduce the cost of production process management.
Accompanying drawing explanation
Fig. 1 is the module diagram of typical sample circuit.
Fig. 2 is longer RSSI Trigger sequential schematic diagram.
Fig. 3 is shorter RSSI Trigger sequential schematic diagram.
Fig. 4 is a kind of module diagram of programmable logic cells to the processing unit of OLT optical module RSSI Trigger sequential that utilize of the present invention.
Fig. 5 is a kind of logic circuit structure figure of programmable logic cells to the processing unit of OLT optical module RSSI Trigger sequential that utilize of the present invention.
Fig. 6 is a kind of schematic flow sheet of programmable logic cells to the processing method of OLT optical module RSSI Trigger sequential that utilize of the present invention.
Fig. 7 is before the sequential processing of RSSI Trigger of a complete process process, process in and process after sequential comparison diagram.
Fig. 8 is a kind of logic circuit structure figure of programmable logic cells to the processing unit of OLT optical module RSSI Trigger sequential that utilize that has increased inverter of the present invention.
Embodiment
Disclosed all features in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing), unless narration especially all can be replaced by other equivalences or the alternative features with similar object.That is,, unless narration especially, each feature is an example in a series of equivalences or similar characteristics.
Below in conjunction with accompanying drawing, further the present invention will be described in detail.
As shown in Figure 1, be the module diagram of existing typical sample circuit.This sample circuit is comprised of sampling hold circuit, analog to digital converter and digital signal processing unit.RSSI Trigger is input to sampling hold circuit and analog to digital converter simultaneously; Because the decay part of RSSI Trigger sequential is low level, make the analog switch conducting of sampling hold circuit, sampling hold circuit starts to receive the light signal that enters OLT, and the electric capacity in sampling hold circuit starts charging, when being charged to when consistent with light signal, charge complete; When RSSI Trigger sequential is high level, analog switch cuts out, and sampling hold circuit keeps the current state of electric capacity, enters sampling hold mode; Sampling hold circuit, using the current state of electric capacity as analog output to analog to digital converter, is sampled for analog to digital converter; Analog to digital converter is converted to analog quantity digital signal and sends to digital signal processing unit under the control of RSSI Trigger; Digital signal processing unit calculates digital signal, obtains the received optical power value of this sampling; After having sampled, the capacitor discharge of sampling hold circuit, gets back to sampling state before.
As shown in Figure 2, be long RSSI Trigger sequential schematic diagram.T
opticalexpression enters the duration of the light signal of OLT, is 1us; TD represents that RSSI Trigger postpones duration, is 850ns, and TW represents RSSI Trigger width, is 10us.The electric capacity of sampling hold circuit start charging work at light signal input OLT, completes charging within 850ns, enters sampling and keep; The analog to digital converter being integrated in microprocessor carries out analog-to-digital conversion, the digital signal after conversion is sent to digital signal processing unit and carry out computing, after 10us, obtains received optical power value, completes sampling.After completing sampling, microprocessor internal is processed, and the received optical power value calculating is write to the appropriate address position of the microprocessor registers of optical module.OLT system host computer can conduct interviews by the microprocessor registers appropriate address of OLT optical module, obtains the received optical power value of sampling.Longer RSSI Trigger sequential can meet the sample rate requirement of the integrated analog to digital converter of microprocessor internal that optical module uses.
As shown in Figure 3, be shorter RSSI Trigger sequential schematic diagram.TD is 250ns, and TW is 600ns.So the short time, require to use independent analog to digital converter at a high speed, this will increase volume, cost and the circuit complexity of optical module.
As shown in Figure 4, Figure 5, a kind of module diagram and the logic circuit structure figure of programmable logic cells to the processing unit of OLT optical module RSSI Trigger sequential that utilize of the present invention.One utilize programmable logic cells to the processing unit of OLT optical module RSSI Trigger sequential by programmable logic cells, sampling hold circuit, analog to digital converter and digital signal processing unit form, RSSI Trigger before this programmable logic cells reception & disposal, it is processed, RSSI Trigger after processing is outputed to sampling hold circuit and analog to digital converter simultaneously, sampling hold circuit is for receiving optical signals and the maintenance of sampling, analog to digital converter is for being converted into digital signal by analog quantity, digital signal processing unit is for calculating received optical power value according to digital signal.
This programmable logic cells, comprise inverter or door, register, first and door and second with; RSSI Trigger send to simultaneously inverter input and or door one end input; Inverter output inversion signal to the second and door one end input; Or the reception first of door other end input and the positive and the signal that feed back, or door output positive or signal to the first and one end input; First with a door other end input receiving register signal, first with door also by positive with signal outputs to or door other end input and second and an other end input; Second exports the RSSI Trigger signal after processing with door.
Be illustrated in figure 6 a kind of schematic flow sheet of programmable logic cells to the processing method of OLT optical module RSSI Trigger sequential that utilize of the present invention.This flow process comprises the following steps:
S1: start step: register original levels is set to 0; RSSI Trigger is divided into two-way ，Yi road and by step S2, processes, process by step S3 on another road;
S2: anti-phase road step: to RSSI Trigger negate, obtain inversion signal;
S3: positive or step: the positive feeding back in RSSI Trigger and step S4 and signal are carried out to logic OR computing, obtain positive or signal;
S4: positive and step: positive or signal are carried out to logic and operation with the register signal being stored in register, obtain positive and signal; Wherein, when sample circuit is received sample enable signal, register level is set to 1;
S5: just anti-phase and step: inversion signal and positive and signal are carried out to logic and operation, the RSSI Trigger after being processed;
S6: end step: after analog to digital converter has been sampled, register level is set to 0 again,
S7: export anti-phase step: the RSSI Trigger negate to after processing, obtains the RSSI Trigger after anti-phase processing.
As shown in Figure 7, be before the sequential processing of RSSI Trigger of a complete process process, process in and process after sequential comparison diagram.The delay duration of the RSSI Trigger sequential before processing is 250ns, and width is 600ns, and the RSSI Trigger before this processing is divided into two-way, enters respectively inverter and or door.
In the delay duration of the RSSI of 250ns Trigger sequential, because initial register logical level is 0, therefore second with door output logic level be 0 positive and a signal; RSSI Trigger logic level before simultaneously processing is 0, therefore the inversion signal that inverter output logic level is 1; Therefore second carries out and computing positive and signal and inversion signal with door, and result is that output logic level is 0 just anti-phase and signal.
In the width of the RSSI of 600ns Trigger sequential, because the RSSI Trigger logic level before processing is 1, the inversion signal that inverter output logic level is 0; Or door receives that logic level is positive and the signal that the logic level that fed back RSSI Trigger before 1 processing and a upper period is 0, therefore the positive that output logic level is 1 or signal; Meanwhile, because the RSSI Trigger rising edge before processing is sample enable signal, therefore register logical level is set to 1; First carries out and computing positive or signal and register signal with door, therefore the positive that output logic level is 1 and signal; Second carries out and computing inversion signal and positive and signal with door, therefore the just anti-phase and signal that output logic level is 0.
When RSSI Trigger sequential enters the duration after 850ns, because the RSSI Trigger logic level before processing is 0, the inversion signal that inverter output logic level is 1; Or door receives that logic level is positive and the signal that the logic level that fed back RSSI Trigger before 0 processing and a upper period is 1, therefore the positive that output logic level is 1 or signal; Meanwhile, the logic level in register is still 1; First carries out and computing positive or signal and register signal with door, therefore the positive that output logic level is 1 and signal; Second carries out and computing inversion signal and positive and signal with door, therefore the just anti-phase and signal that output logic level is 1.
Now analog to digital converter starts sampling, complete when 10us post-sampling, and register logical level is set to 0; Then, first is 1 with the door register signal that is 0 to logic level and logic level, and positive or signal carry out and computing, the positive that is 0 by output logic level and signal; Second is still 1 to positive and signal and logic level with door, and inversion signal carries out and computing, the just anti-phase and signal that is 0 by output logic level.
Whole sampling process completes.The above is set to 0 or be set to 1 behavior by register logical level, by the microprocessor of integrated register, analog to digital converter, is completed.
As shown in Figure 8, be a kind of logic circuit structure figure of programmable logic cells to the processing unit of OLT optical module RSSI Trigger sequential that utilize that has increased inverter of the present invention.Conducting while being generally low level due to the analog switch in optical module sampling hold circuit, sampling hold circuit capacitor charging, charged and made sampling hold circuit enter sampling hold mode, therefore this class sampling hold circuit is directly used the RSSI Trigger after processing.And the analog switch of some customer requirement is high level conducting, therefore need to be to the RSSI Trigger negate after processing, making the decay part of the RSSI Trigger sequential after anti-phase processing is high level, thereby within time of delay, complete the conducting of analog switch, the charging of sampling hold circuit electric capacity, last sampling hold circuit enters the process of sampling hold mode.Therefore, the RSSI Trigger after processing outputs to analog to digital converter, for controlling the work of analog to digital converter; RSSI Trigger after anti-phase processing outputs to sampling hold circuit, for supporting that analog switch is the sampling maintenance electric weight of high level conducting.
A preferred embodiment according to the present invention, analog to digital converter, digital signal processing unit, register, inverter or door, first with door, second and and the second inverter by ADuC7020 or the Aduc7023 chip of U.S. ADI company, provided.Due to this chip simultaneously integrated include the microprocessor of analog to digital converter, digital signal processing unit, register and include inverter, with the programmable logic array of door or door etc., during use, only need to the integrated device of this chip internal be coupled together according to circuit diagram, therefore use this chip integration Gao， industrial cost cheap.Certainly, separated microprocessor and programmable logic array are combined to use and also have the effect being equal to, for example microprocessor is selected the DS4830 of MAXIM company, the MEGA88 of Atmel company, the C8051F413 of Silicon Lab company; Programmable logic array is selected the LCMX02-256ZC-1UMG64I of Lattice company or the EPM240Z of altera corp.
Another preferred embodiment according to the present invention, sampling hold circuit is by the image current source chip MAX4007 of U.S. MAXIM company, and the analog switch TS5A4595 of American TI Company, and conventional electric capacity and resistance, form according to known mode.This that use in sampling hold circuit two chip block technology maturations, stability is good.
The above; be only preferably embodiment of the present invention, but protection scope of the present invention is not limited to this, any people who is familiar with this technology is in the disclosed technical scope of the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.
Claims (4)
1. one kind is utilized the processing unit of programmable logic cells to OLT optical module RSSI Trigger sequential, comprise sampling hold circuit, analog to digital converter, digital signal processing unit, sampling hold circuit is for receiving optical signals and received optical power intensity triggering signal RSSI Trigger, analog to digital converter is for being converted into digital signal by analog quantity, digital signal processing unit, for calculating received optical power value according to digital signal, is characterized in that:
Also comprise programmable logic cells, the RSSI Trigger before this programmable logic cells reception & disposal, processes it, and the RSSI Trigger after processing is outputed to sampling hold circuit and analog to digital converter simultaneously;
Described programmable logic cells, comprise inverter or door, register, first and door and second with; RSSI Trigger send to simultaneously inverter input and or door one end input; Inverter output inversion signal to the second and door one end input; Or the reception first of door other end input and the positive and the signal that feed back, or door output positive or signal to the first and one end input; First with a door other end input receiving register signal, first with door also by positive with signal outputs to or door other end input and second and an other end input; Second exports the RSSI Trigger signal after processing with door.
2. utilize according to claim 1 the processing unit of programmable logic cells to OLT optical module RSSI Trigger sequential, it is characterized in that: described programmable logic cells, also comprise the second inverter, RSSI Trigger after this second inverter reception & disposal, exports the RSSI Trigger after anti-phase processing.
3. according to the processing unit that utilizes programmable logic cells to OLT optical module RSSI Trigger sequential described in claim 1 or 2, it is characterized in that: described inverter or door, register, first and door, second with and the second inverter, the microprocessor chip by model for Aduc7020 or Aduc7023 provides.
4. according to the processing unit that utilizes programmable logic cells to OLT optical module RSSI Trigger sequential described in claim 1 or 2, it is characterized in that: described sampling hold circuit, comprises that model is the image current source chip of MAX4007 and the analog switch that model is TS5A4595.
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| CN104168067A (en) * | 2014-08-29 | 2014-11-26 | 四川华拓光通信股份有限公司 | Method for judging optical power signal intensity in optical receiving circuit and circuit thereof |
| CN112511240B (en) * | 2020-11-17 | 2021-10-08 | 成都优博创通信技术有限公司 | Control circuit, switch control circuit, optical line terminal and control method thereof |
| CN112737672B (en) * | 2020-12-21 | 2023-06-09 | 成都储翰科技股份有限公司 | Receiving power intensity detection circuit for burst optical receiver |
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| EP1710931A1 (en) * | 2005-04-08 | 2006-10-11 | Ricoh Company, Ltd. | DSSS and OFDM two-way waiting reception method and wireless LAN apparatus |
| CN101127567A (en) * | 2007-09-20 | 2008-02-20 | 中兴通讯股份有限公司 | A method and device for optical line terminal to detect the optical power of optical network unit |
| CN101594184A (en) * | 2009-06-11 | 2009-12-02 | 青岛海信宽带多媒体技术有限公司 | A kind of optical line terminal |
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| EP1710931A1 (en) * | 2005-04-08 | 2006-10-11 | Ricoh Company, Ltd. | DSSS and OFDM two-way waiting reception method and wireless LAN apparatus |
| CN101127567A (en) * | 2007-09-20 | 2008-02-20 | 中兴通讯股份有限公司 | A method and device for optical line terminal to detect the optical power of optical network unit |
| CN101594184A (en) * | 2009-06-11 | 2009-12-02 | 青岛海信宽带多媒体技术有限公司 | A kind of optical line terminal |
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