CN112711560A - Reconstruction method for single-point connection RapidIO bus of ZYNQ chip - Google Patents
Reconstruction method for single-point connection RapidIO bus of ZYNQ chip Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention discloses a reconstruction method of a ZYNQ chip single-point connection RapidIO bus, and aims to provide a reconstruction design idea of a single-point connection RapidIO link of an FPGA and a DSP program, which has the advantages of low labor cost, high joint test efficiency and low software coupling. The invention is realized by the following technical scheme: after any program in the FPGA and the DSP is loaded, the FPGA and the DSP enter an external reset flow, then when the reset release flow is switched in, the FPGA program starts to work before the DSP program, the DSP reset release is later than the FPGA reset release, so that a fixed RapidIO link sequence relation exists after the FPGA and the DSP program are loaded, and the reconstruction of a single-point connection RapidIO link is realized through the control of a ZYNQ chip.
Description
Technical Field
The invention relates to the radar and communication related field, and discloses a reconstruction method for realizing a single-point connection RapidIO bus of an FPGA and a DSP by ZYNQ chip control.
Background
With the rapid development of communication and network technologies, in an embedded system, to implement a DSP algorithm with higher and higher requirements for computation and real-time performance, higher requirements are put forward for the processing capability of a DSP processor and the parallel processing capability of a chip in the system, and the adoption of an FPGA + DSP hardware architecture has gradually become a mainstream configuration. The low speed EMIF bus employed between the DSP processor and the peripherals is gradually replaced by a RapidIO bus based on a high performance interconnect architecture.
In the existing system connected through a single point of a RapidIO bus, the sequential relation exists between the FPGA and the DSP program loading. Particularly, after one of the two programs reaches a curing state, the power needs to be re-powered on, and meanwhile, the time for loading the programs of the FPGA chip and the DSP processor needs to be adjusted to meet the sequential relation of the loading of the programs of the FPGA chip and the DSP processor, so that the problem that a communication link between the FPGA and the DSP program through the RapidIO bus is unstable can be solved. In the debugging process, the sequential relation between the FPGA and the DSP program loading is found in a system in which the FPGA and the DSP are connected through a RapidIO bus single point. The FPGA program is loaded firstly, then the DSP program is loaded, and then the DSP RapidIO thread is started to initialize, so that the RapidIO link can be stably established, the RapidIO 0x158 register state corresponding to the corresponding FPGA and the DSP program is normal, and the FPGA and the DSP program can perform data communication through the RapidIO bus. Often, in a large system, there are as many as tens of hardware boards. In the initial stage of the system joint test, whether the FPGA program or the DSP program is adopted, the program is inevitably frequently modified and then loaded. If the operation is not performed according to the program loading sequence relationship described above, the RapidIO link between the FPGA and the DSP program cannot be stably established, which may have a certain effect on the efficiency of the joint test. Particularly, when one software of the FPGA and the DSP reaches a solidified state, the FPGA or the DSP is modified and then loaded, and the RapidIO link between the FPGA and the DSP cannot be normally established. At this time, on one hand, the system needs to be powered off and then powered on, and the time for loading the programs of the FPGA chip and the DSP processor needs to be adjusted to meet the sequential relation of the program loading of the FPGA chip and the DSP processor, so that the RapidIO link between the FPGA chip and the DSP processor can be ensured to work normally. Frequent modification of software can lead to frequent power-on and power-off of a system, which causes interruption of joint test of other functions in the system, and after a joint tester modifies a program, sometimes the joint tester may load the program for several hours in order to wait for power-on and power-off of the system, which causes unnecessary waste of manpower, and thus the joint test efficiency of the system is extremely low.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the reconstruction method for the RapidIO bus through the single-point connection of the ZYNQ chip, which has the advantages of low labor cost, high joint test efficiency and low software coupling, so as to solve the problems of precedence relationship between the FPGA and the DSP program loading and the coupling relationship when the RapidIO bus is used in the existing system, and improve the integration efficiency of the joint test of the system.
The above object of the present invention can be achieved by the following measures, a reconstruction method of a ZYNQ chip single-point connection RapidIO bus is characterized in that: a ZYNQ chip of the PS control unit and the PL programmable logic unit is adopted to form a main control unit, the main control unit is arranged in the PL programmable logic unit, and the FPGA loading monitoring module and the DSP loading monitoring module which are connected through a hardware bus or a RapidIO bus single point are adopted to realize the real-time monitoring of the FPGA and DSP program loading condition by the PL programmable logic unit; the ZYNQ program loading is prior to the FPGA chip of the field programmable gate array and the DSP program to start working, the ZYNQ program is loaded and then starts a monitoring program, the conditions of the first loading and the dynamic loading of the FPGA and the DSP program are monitored in real time in parallel, after any one program of the FPGA and the DSP program is loaded, the FPGA and the DSP program enter an external reset flow, and then the reset release flow is switched to, so that the DSP reset release is later than the FPGA reset release; after the ZYNQ program is loaded, starting an FPGA loading monitoring module and a DSP loading monitoring module monitoring program, and monitoring the conditions of first loading and dynamic loading of the FPGA and the DSP program in real time in parallel; when the RapidIO link is loaded for the first time, the FPGA loading monitoring module and the DSP loading monitoring module enable a Reset signal RIO Reset and a DSP program synchronous Reset signal System Reset in an FPGA program through a hardware bus, the FPGA program Reset signal RIO Reset is released firstly, then the DSP program synchronous Reset signal Sysetm Reset is released, so that a fixed RapidIO link sequence relation exists after the FPGA and the DSP program are loaded, and the reconstruction of a single-point connection RapidIO link is realized through the control of a ZYNQ chip.
Compared with the prior art, the method has the beneficial effects that:
the labor cost is low. The invention adopts a ZYNQ chip of a PS control unit and a PL programmable logic unit to form a main control unit, and an FPGA loading monitoring module which is connected with a field programmable gate array FPGA chip through a hardware bus or a RapidIO bus single point and a DSP loading monitoring module which is connected with a digital signal processor DSP through a hardware bus or a RapidIO bus single point are arranged in the PL programmable logic unit, thereby realizing the real-time monitoring of the FPGA and the DSP program loading condition of the PL programmable logic unit. And starting a monitoring program after the ZYNQ program is loaded, and monitoring the conditions of the first loading and the dynamic loading of the FPGA and the DSP program in real time in parallel. After any program of the FPGA and the DSP is loaded, the FPGA and the DSP can enter an external reset flow, and then when the FPGA and the DSP are switched into a reset release flow, the DSP reset release is later than the FPGA reset release, so that the FPGA program can start to work before the DSP program, and the requirements of the RapidIO link on the FPGA and the DSP are met. The RapidIO link is automatically reconstructed under the control of the ZYNQ chip, and the waiting time of designers is saved.
The joint test efficiency is high. The method adopts ZYNQ program loading prior to FPGA and DSP programs, starts an FPGA loading monitoring module and a DSP loading monitoring module monitoring program after the ZYNQ program is loaded, and monitors the conditions of first loading and dynamic loading of the FPGA and the DSP programs in real time in parallel; when the RapidIO bus is loaded for the first time, the FPGA program RIO Reset and the DSP program System Reset are set to be effective by monitoring the first loading and dynamic loading of the FPGA program and the DSP program, the FPGA program RIO Reset is released firstly, and then the DSP program Sysetm Reset is released, so that a fixed sequence relation exists after the FPGA program and the DSP program are loaded, and stable chain establishment and normal communication can be ensured when the RapidIO bus is used by the FPGA program and the DSP program. Therefore, after software designers do not need to modify any program in the two programs each time, the joint test can be carried out after the system is powered off again and then powered on, and the debugging efficiency of the system is improved.
Low software coupling. According to the invention, the RIO Reset is released according to an FPGA program, then the synchronous Reset signal Sysetm Reset is released according to a DSP program, so that a fixed sequential relation exists after the FPGA and the DSP program are loaded, and the RapidIO reconstruction method by realizing single-point connection through the control of the ZYNQ chip can solve the coupling relation existing between the FPGA and the DSP program by using a RapidIO bus. The method for realizing the RapidIO reconstruction through the ZYNQ chip control solves the problem that in the prior art, after one of the FPGA and the DSP program reaches a curing state, the loading time of the FPGA chip and the DSP processor program is required to be adjusted to meet the sequential relation of the loading of the two programs, and the problem that a communication link between the FPGA and the DSP program through the RapidIO bus is unstable is solved.
Drawings
The method is further described with reference to the figures and the detailed description.
FIG. 1 is a schematic diagram of the reconstruction principle of the RapidIO bus based on single-point connection of a ZYNQ chip.
Fig. 2 is a flow chart of the FPGA monitoring module process of fig. 1.
Fig. 3 is a flow chart of the DSP monitoring block process of fig. 1.
Detailed Description
See fig. 1. According to the invention, a ZYNQ chip of a PS control unit and a PL programmable logic unit is adopted to form a main control unit, and an FPGA loading monitoring module which is connected with a field programmable gate array FPGA chip through a hardware bus or a RapidIO bus single point and a DSP loading monitoring module which is connected with a digital signal processor DSP through a hardware bus or a RapidIO bus single point are arranged in the PL programmable logic unit, so that the PL programmable logic unit can monitor the FPGA and DSP program loading condition in real time. And the ZYNQ program loading starts to work prior to the FPGA and DSP programs, the monitoring program is started after the ZYNQ program is loaded, and the conditions of the first loading and the dynamic loading of the FPGA and the DSP programs are monitored in real time in parallel. After any program of the FPGA and the DSP is loaded, the FPGA and the DSP enter an external reset flow and then are switched to a reset release flow, so that the reset release of the DSP is later than that of the FPGA. After the ZYNQ program is loaded, the FPGA loading monitoring module and the DSP loading monitoring module monitoring program are started, and the conditions of first loading and dynamic loading of the FPGA and the DSP program are monitored in real time in parallel. When the RapidIO link is loaded for the first time, the FPGA loads a monitoring module program and the DSP loads a monitoring module program, a Reset signal RIO Reset and a DSP program synchronous Reset signal System Reset in the FPGA program are set to be effective, the FPGA program Reset signal RIO Reset is released firstly, then the DSP program synchronous Reset signal Sysetm Reset is released, so that a fixed RapidIO link sequence relation exists after the FPGA and the DSP program are loaded, and the reconstruction of a single-point connection RapidIO link is realized through the control of a ZYNQ chip.
The FPGA chip comprises an FPGA heartbeat module and an RIO Reset module controlled by external input. The DSP processor comprises a DSP heartbeat module and a System Reset module controlled by external input. After the FPGA program is loaded, the FPGA heartbeat module starts to work, and firstly 0xAAAAAAA is continuously output for 5 times, and then 0 xBBBBBBBBBB is continuously output. The RIO Reset module outputs high level and continuously generates RapidIO Reset signals; when the external input is low level, RapidIO reset is stopped. After the DSP program is loaded, the DSP heartbeat module starts to work, 0xCCCCCC is output for 5 times, and then 0 xDDDDDDDDDDD is continuously output; the Sysetm Reset module outputs high level and continuously sets the System Reset signal to low level; when the external input is low level, the System Rese signal is set to high level.
See fig. 2. When the FPGA program loads the program for the first time, the PL unit FPGA loading monitoring module enters an initial state after power-on reset is completed, hardware bus input from the FPGA chip is monitored, whether the FPGA chip hardware bus input is 0xAAAAAAA or not is judged, and if yes, the state of setting the FPGA hardware bus output high level is switched to. And judging whether the DSP loading monitoring module outputs a low level to the hardware bus, and when the DSP loading monitoring module outputs the low level to the hardware bus, immediately switching the FPGA loading monitoring module to a state of setting the output low level of the FPGA hardware bus, and then returning to the initial state. When the hardware bus input from the FPGA chip is monitored to be not 0xAAAAAAA, switching to a state of monitoring whether the hardware bus input from the FPGA chip is 0 xBBBBBBBBBB or not, and when the input is not 0 xBBBBBBBBBB, returning to the initial state; when the input is 0xBBBBBBBB, switching to a state of monitoring whether the input of the DSP hardware bus is 0xCCCCCC or not, and returning to an initial state when the input of the DSP hardware bus is not 0xCCCCCCCC or not in the state of monitoring whether the input of the DSP hardware bus is 0xCCCCCCCC or not; and when the input is 0xCCCCCC, switching to a state of setting the output high level of the FPGA hardware bus, and when the DSP loading monitoring module outputs the low level to the hardware bus, immediately switching the FPGA loading monitoring module to a state of setting the output low level of the FPGA hardware bus, and then returning to the initial state. And (4) performing subsequent operation, and switching to a corresponding state for processing when the condition of the relevant state is met.
In fig. 2, when the DSP program is dynamically loaded, the FPGA load monitoring module is in 2 possible states. The 1 st type is in an initial state, monitors the hardware bus input from the FPGA chip, and because the FPGA is not dynamically loaded at the moment, the monitored input is continuously 0 xBBBBBBBBBB. After the DSP program is dynamically loaded, the DSP heartbeat module inputs 0xCCCCCC for 5 times to a ZYNQ chip PL unit through a hardware bus, the FPGA loading monitoring module monitors that the hardware input of the DSP processor meets the condition of 0xCCCCCCCC, and then the FPGA hardware bus is switched to a state of setting the high level output of the FPGA hardware bus. After the monitoring DSP loading monitoring module outputs low level to the hardware bus, the FPGA loading monitoring module immediately shifts to a state of setting the output low level of the FPGA hardware bus, and then returns to the initial state. And 2, in a state that the FPGA program is just loaded soon, the FPGA loading monitoring module is in a state of outputting a high level to the FPGA hardware bus, and in the state, the FPGA loading monitoring module immediately shifts to a state of setting the output low level of the FPGA hardware bus and then returns to the initial state only after monitoring that the DSP loading monitoring module outputs a low level to the hardware bus.
See fig. 3. When the DSP program loads the program for the first time, the DSP loading monitoring module enters an initial state after power-on reset is completed. Monitoring hardware bus input from a DSP processor, judging whether the DSP hardware bus inputs 0xCCCCCC, when the input is 0xCCCCCCCC, switching to a state of setting the DSP hardware bus to output low level, judging whether an FPGA loading monitoring module outputs high level to the hardware bus, when the FPGA loading monitoring module outputs high level to the hardware bus, switching the DSP loading monitoring module to a delay waiting state, when the delay waiting time meets 1ms, switching to a state of setting the DSP hardware bus high level, and then returning to an initial state. When the hardware bus input from the DSP processor is not 0xCCCCCC, monitoring the hardware bus input from the DSP processor, judging whether the hardware bus input is in a 0 xDDDDDDDDDDD state, and returning to the initial state when the hardware bus input is not 0 xDDDDDDDDDDDDDDDDDDD; when the input is 0 xDDDDDDDDD, switching to monitoring FPGA hardware bus input, judging whether the input is in a 0xAAAAAAA state, and returning to an initial state when the input of the monitoring FPGA hardware bus is not in the 0xAAAAAAA state; when the input is 0xAAAAAAA, the state is transferred to the state of setting the DSP hardware bus output low level. After the FPGA loading monitoring module outputs low level to the hardware bus, the DSP loading monitoring module is switched into a delay waiting state, and after the delay waiting time meets 1ms, the DSP loading monitoring module is switched into a state of setting high level of the DSP hardware bus and then returns to the initial state. And (4) performing subsequent operation, and switching to a corresponding state for processing when the condition of the relevant state is met.
In fig. 3, when the FPGA program is dynamically loaded, the DSP loading monitoring module is in 2 possible states, the 1 st is in an initial state, and monitors the hardware bus input from the DSP chip, and since the DSP is not dynamically loaded at this time, the monitored input is continuously 0 xdddddddddd; after the FPGA program is dynamically loaded, the FPGA heartbeat module inputs 0xAAAAAAA for 5 times to a PL unit of the ZYNQ chip through a hardware bus; when the loading monitoring module monitors that the hardware input of the FPGA chip meets the condition of 0xAAAAAAA, switching to a state of setting a DSP hardware bus output low level; after the FPGA loading monitoring module outputs high level to the hardware bus, the DSP loading monitoring module is switched into a delay waiting state, and after the delay waiting time meets 1ms, the DSP hardware bus is switched into a state of outputting high level, and then the initial state is returned. And 2, in a state that the DSP is just loaded soon, the DSP loading monitoring module is in a state of outputting a low level to the DSP hardware bus, in the state, the DSP loading monitoring module is switched into a delay waiting state only after monitoring that the FPGA loading monitoring module outputs a high level to the hardware bus, and the DSP loading monitoring module is switched into a state of setting the DSP hardware bus to output a high level after the delay waiting time meets 1ms, and then the DSP loading monitoring module returns to the initial state.
The above embodiments are merely illustrative, and not restrictive, and any modifications, equivalents, improvements, etc., which may occur to those skilled in the art, may be made without departing from the spirit and principles of the present invention.
Claims (10)
1. A reconstruction method of a ZYNQ chip single-point connection RapidIO bus is characterized by comprising the following steps: a ZYNQ chip of the PS control unit and the PL programmable logic unit is adopted to form a main control unit, the main control unit is arranged in the PL programmable logic unit, and the FPGA loading monitoring module and the DSP loading monitoring module which are connected through a hardware bus or a RapidIO bus single point are adopted to realize the real-time monitoring of the FPGA and DSP program loading condition by the PL programmable logic unit; the ZYNQ program loading is prior to the FPGA chip of the field programmable gate array and the DSP program to start working, the ZYNQ program is loaded and then starts a monitoring program, the conditions of the first loading and the dynamic loading of the FPGA and the DSP program are monitored in real time in parallel, after any one program of the FPGA and the DSP program is loaded, the FPGA and the DSP program enter an external reset flow, and then the reset release flow is switched to, so that the DSP reset release is later than the FPGA reset release; after the ZYNQ program is loaded, starting an FPGA loading monitoring module and a DSP loading monitoring module monitoring program, and monitoring the conditions of first loading and dynamic loading of the FPGA and the DSP program in real time in parallel; when the RapidIO link is loaded for the first time, the FPGA loading monitoring module and the DSP loading monitoring module are used for setting a Reset signal RIO Reset in an FPGA program and a DSP program synchronous Reset signal System Reset to be effective through a hardware bus, the Reset signal RIO Reset is released firstly according to the FPGA program, then the DSP program synchronous Reset signal Sysetm Reset is released, so that a fixed RapidIO link sequence relation exists after the FPGA and the DSP program are loaded, and the reconstruction of a single-point connection RapidIO link is realized through the control of a ZYNQ chip.
2. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 1, wherein: the FPGA chip comprises an FPGA heartbeat module and an RIO Reset module controlled by external input; the DSP processor comprises a DSP heartbeat module and a System Reset module controlled by external input.
3. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 2, wherein: after the FPGA program is loaded, the FPGA heartbeat module starts to work, and firstly 0xAAAAAAA is continuously output for 5 times, and then 0 xBBBBBBBBBB is continuously output.
4. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 2, wherein: the RIO Reset module outputs high level and continuously generates RapidIO Reset signals; when the external input is low level, RapidIO reset is stopped.
5. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 3, wherein: after the DSP program is loaded, the DSP heartbeat module starts to work, 0xCCCCCC is output for 5 times, and then 0 xDDDDDDDDDDD is continuously output; the Sysetm Reset module outputs high level and continuously sets the System Reset signal to low level; when the external input is low level, the System Rese signal is set to high level.
6. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 1, wherein: when the FPGA program loads the program for the first time, the FPGA loading monitoring module enters an initial state after power-on reset is completed, hardware bus input from an FPGA chip is monitored, whether the FPGA chip hardware bus input is 0xAAAAAAA is judged, if yes, after the FPGA loading monitoring module is shifted to a state of setting the FPGA hardware bus output high level, whether the DSP loading monitoring module outputs low level to the hardware bus is judged, and after the DSP loading monitoring module outputs low level to the hardware bus, the FPGA loading monitoring module is immediately shifted to a state of setting the FPGA hardware bus output low level and returns to the initial state.
7. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 6, wherein: when monitoring that the hardware bus input from the FPGA chip is not 0xAAAAAAA, the FPGA loading monitoring module shifts to a state of monitoring whether the hardware bus input from the FPGA chip is 0xBBBBBBBB or not, and returns to an initial state when the input is not 0 xBBBBBBBB; when the input is 0xBBBBBBBB, switching to a state of monitoring whether the input of the DSP hardware bus is 0xCCCCCC or not, and returning to an initial state when the input of the DSP hardware bus is not 0xCCCCCCCC or not in the state of monitoring whether the input of the DSP hardware bus is 0xCCCCCCCC or not; and when the input is 0xCCCCCC, switching to a state of setting the output high level of the FPGA hardware bus, and when the DSP loading monitoring module outputs the low level to the hardware bus, immediately switching the FPGA loading monitoring module to a state of setting the output low level of the FPGA hardware bus, and then returning to the initial state.
8. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 1, wherein: when a DSP program loads a program for the first time, the DSP loading monitoring module enters an initial state after power-on reset is completed, hardware bus input from a DSP processor is monitored, whether 0xCCCCCC is input into the DSP hardware bus is judged, when the input is 0xCCCCCC, the DSP loading monitoring module is switched to a state of setting a low level output of the DSP hardware bus, whether a high level output to the hardware bus is output by the FPGA loading monitoring module is judged, when the high level output to the hardware bus is output by the FPGA loading monitoring module, the DSP loading monitoring module is switched to a delay waiting state, and the DSP loading monitoring module is switched to a state of setting a high level of the DSP hardware bus after the delay waiting time meets 1ms, and then the initial state.
9. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 1, wherein: when monitoring that the hardware bus input from the DSP processor is not 0xCCCCCC, the DSP loading monitoring module is switched to monitor the hardware bus input from the DSP processor, judges whether the hardware bus input is in a 0 xDDDDDDDDDDD state or not, and returns to the initial state when the input is not 0 xDDDDDDDDDDDDDDD; when the input is 0 xDDDDDDDDD, switching to monitoring FPGA hardware bus input, judging whether the input is in a 0xAAAAAAA state, and returning to an initial state when the input of the monitoring FPGA hardware bus is not in the 0xAAAAAAA state; when the input is 0xAAAAAAA, the state is transferred to the state of setting the DSP hardware bus output low level.
10. The method for reconstructing a single-point connection RapidIO bus of a ZYNQ chip as claimed in claim 1, wherein: after the FPGA loading monitoring module outputs low level to the hardware bus, the DSP loading monitoring module is switched into a delay waiting state, and after the delay waiting time meets 1ms, the DSP loading monitoring module is switched into a state of setting high level of the DSP hardware bus and then returns to the initial state.
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| CN114706607A (en) * | 2022-06-07 | 2022-07-05 | 成都航天通信设备有限责任公司 | Software online upgrading system and method for fully programmable system on chip |
| CN115484219A (en) * | 2022-08-23 | 2022-12-16 | 中国电子科技集团公司第十研究所 | Method, equipment and medium for avoiding port association of domestic SRIO (serial-to-input/output) switching chip |
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