WO2006032196A1 - A chip program loading method - Google Patents

A chip program loading method Download PDF

Info

Publication number
WO2006032196A1
WO2006032196A1 PCT/CN2005/001512 CN2005001512W WO2006032196A1 WO 2006032196 A1 WO2006032196 A1 WO 2006032196A1 CN 2005001512 W CN2005001512 W CN 2005001512W WO 2006032196 A1 WO2006032196 A1 WO 2006032196A1
Authority
WO
WIPO (PCT)
Prior art keywords
program
chip
loaded
loading
consistent
Prior art date
Application number
PCT/CN2005/001512
Other languages
French (fr)
Chinese (zh)
Inventor
Tianxiang Zhou
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2006032196A1 publication Critical patent/WO2006032196A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating

Definitions

  • the present invention relates to programmable chip technology, and more particularly to a program loading technique for a programmable chip. Background of the invention
  • Programmable Chip refers to a variety of electronic chips that need to be loaded before use. It is widely used in modern electronic products, including but not limited to Field Programmable Gate Array (FPGA). ), digital signal processor (Digital Signal Processor, "DSP"), Erasable Programmable Logic Device (EPLD) and other logic devices.
  • FPGA Field Programmable Gate Array
  • DSP Digital Signal Processor
  • EPLD Erasable Programmable Logic Device
  • the programmable chip development cycle is short, the direct development cost is low, and the minimum order quantity is not limited.
  • the cost of the gate circuit decreases and the number of gate circuits in the device increases, the programmable chip is entering the traditional gate array field.
  • companies are using the flexibility of programmable chips to design their products differently than their competitors.
  • semiconductor manufacturers have developed unique EPLDs and FPGAs for performance, power, and integration. And achieve specific goals in terms of cost and other aspects. Such an approach leads to significant differences in the functional areas and complexity of such programmable chips.
  • Programmable chip program The loading process is usually performed after the central processor (CenraJ Processing Unit cartridge "CPU") is powered up or reset, and the CPU controls the entire loading process.
  • CPU Central processor
  • the design process of the entire programmable chip is as follows: First, use the hardware description language (Hardware Description Language, "HDL”) to describe the hardware structure and hardware behavior in a similar way to programming; then use the design tool These descriptions are comprehensively mapped into hardware process files related to semiconductor processes. These descriptions are very similar to those in the software field. Programmable chips are the carriers of these hardware process files. Finally, hardware process files are loaded by special writing tools. On the programmable chip, it has the corresponding function.
  • HDL Hardware Description Language
  • program loading is a critical step in the overall programmable chip design. Although the program loading technology and loading process of various programmable chips are different, they should meet the requirements of reliable, fast, and stable. In addition, the chip life and system upgrade process must be fully considered.
  • the first is the most common loading technique at the moment: simple loading.
  • This method is mostly used in programmable chips that can be repeatedly loaded and loaded, such as FPGA and DSP.
  • the specific implementation method is to force the programmable chip to be loaded directly after the CPU is powered on or reset, so that it has a specific function.
  • This method is simple and effective, easy to implement, and can fully meet the requirements of system upgrade.
  • the second method is the version check loading method, which is applicable to programmable chips such as EPLDs with their own non-volatile memory.
  • the specific implementation method is that the CPU performs version detection on the programmable chip before loading, that is, checks whether the program stored on the non-volatile memory and the version of the program to be loaded are consistent, if the detection result and the program version to be loaded. Consistent, no load operation is performed. This method can reduce the number of invalid repeated loads.
  • the above solution has the following problems: For the first solution, since the number of meaningless reloads is large and the life of the chip is consumed, this solution is only applicable to chips that can be repeatedly loaded multiple times, such as FPGA and DSP; in addition, due to chip loading It takes a long time, so this forced loading method generally extends the time required for system initialization, but in many cases, especially system charging reset, this additional program loading is not required.
  • the main object of the present invention is to provide a chip program loading method, which avoids repeated loading of a chip program, shortens system reset time, improves chip life, and ensures system upgrade reliability.
  • the invention discloses a chip program loading method, which comprises:
  • step B It is judged whether the program currently running by the chip is consistent with the target program to be loaded, and if so, the current processing flow is ended; otherwise, step B is performed;
  • step A when the determination is consistent, before the end of the current processing flow, the method further includes: initializing the chip; and/or, after the step B, further comprising: initializing the chip.
  • step A the determining whether the currently running program is consistent with the target program to be loaded is: obtaining the identification process from the program currently running on the chip and the target program to be loaded respectively. A program summary of the uniqueness of the sequence; determining whether the program of the pre-running program is consistent with the program summary of the target program to be loaded.
  • the program summary is any one of the program's digital digest, digital signature, program content check field, program size, program construction date and time, and the program itself, or any combination of the six.
  • step A the program summary is data of fixed length or variable length.
  • the chip is a field programmable gate array FPGA, or an erasable programming logic device EPLD, or a digital signal processor DSP.
  • the method is implemented by a central processing unit CPU, or by a programmable chip, or by a load control system.
  • the method further includes: determining whether the function of the chip is normal, and if yes, continuing to perform the determining in step A, otherwise performing step B.
  • step A when the chip is an FPGA or an EPLD, the function of the determining chip is judged.
  • the method for determining whether the function of the chip is normal is: performing a loopback test between the DSP and the CPU through the communication link to perform judgment.
  • the key of the present invention is: Before the chip program is loaded, it is judged whether the program currently running by the chip is consistent with the target program to be loaded, and when the judgment is inconsistent, the program loading process is performed on the chip.
  • the invention discloses a chip program loading method, and the main design idea thereof is: firstly, before preparing the loading program, first determining whether the current running program of the chip and the target program to be loaded are consistent, and loading the target program only when the judgment is inconsistent, This avoids repeated loading of the chip program.
  • the program of the chip When the chip function is abnormal, the program of the chip must be reloaded. Therefore, before judging whether the current program is consistent with the target program, it is first determined whether the function of the chip is normal, and if it is normal, it continues to determine whether the current program and the target program are normal. Consistent; If not, directly load the chip into the program.
  • FIG. 1 is a schematic diagram of a processing flow of a preferred embodiment of a method according to the present invention.
  • the program loading process of the present invention is implemented by a CPU.
  • the specific processing includes:
  • Step 100 The CPU determines whether the function of the chip is normal. If it is normal, step 101 is performed; otherwise, step 102 is performed.
  • the CPU can detect the function of the programmable chip by executing a preset detection program to determine whether the chip can work normally.
  • the chip described herein can be a DSP, or an FPGA, or an EPLD.
  • the test procedure executed by the CPU in this step will be different:
  • the loopback test between the DSP and the CPU can be performed through the communication link to make a judgment.
  • the so-called loopback test specifically: the CPU presets a data and sends a test to the DSP through its communication link with the DSP. Data.
  • the DSP processes the data from the CPU, and J returns the result to the CPU through the communication link between the CPU and the DSP.
  • the CPU compares the processing result from the DSP with its preset data to determine whether the two are consistent. If they are completely consistent, it means that the DSP can work normally, and the function of the DSP chip is normal; if not completely consistent, the DSP cannot work normally.
  • the function of the DSP chip is abnormal.
  • the detection register includes: a detection input register and a detection output register.
  • the so-called read and write operation of the detection register specifically: the CPU presets a data, writes it to the detection input register of the known address in the chip through the address bus and the data bus.
  • the logic unit inside the chip calculates and processes the data of the detection input register according to a specific calculation rule, and then sends the processed data to the detection output register of the known address in the chip.
  • the CPU reads the data of the detection output register in the chip, compares the read data with the data previously written to the detection input register, and determines whether the two data meet the specific calculation rule, and if yes, Indicates that the detection register can work normally, and the function of the chip is normal; if it does not match, it means that the detection register is not working properly, and the function of the chip is abnormal.
  • Step 101 The CPU determines whether the currently running program of the chip is consistent with the target program to be loaded. If yes, step 103 is performed; otherwise, step 102 is performed.
  • a program summary for identifying the uniqueness of the program may be separately obtained from a program currently running by the chip and a target program to be loaded, and then a program summary of the program currently running by the chip and a program of the target program to be loaded may be determined. Whether the sum is consistent, if they are consistent, it means that the current running program of the chip is consistent with the target program to be loaded; if it is inconsistent, it means that the program currently running on the chip is inconsistent with the target program to be loaded.
  • the above-mentioned program summary for identifying the uniqueness of a program is unique in that the program summary can be directly obtained or exported through a program file without artificial setting.
  • the program summary can be Any one of the program's digital digest, digital signature, program content check field, program size reel construction period and time, program itself, etc., or any combination of these, for further understanding of the method of the present invention
  • the processing principle the following is a brief description of the meaning of these several program abstracts.
  • Digital summaries are obtained during the calculation of program content using a certain digest algorithm. For different programs, the content is not completely consistent, and the digital summary calculated by using the same digest algorithm to calculate its content will be different.
  • Digital signatures are obtained during the calculation of program content using known public keys and signature algorithms. For different programs, the program content is not completely consistent, and the digital signature calculated by using the same public key and signature algorithm to calculate its content will be different.
  • the program content check field is a check field calculated by using a check algorithm for the program content, such as a Cyclic Redundancy Check (CRC), for different programs, the content is not If they are identical, the face field calculated by using the same check algorithm to calculate the content will be different.
  • CRC Cyclic Redundancy Check
  • the size is different for two different programs.
  • the program summary may also be any combination of the above several program summaries. It is worth mentioning that most file formats currently contain check fields, digital digests, or digital signatures. This way, the system does not need to perform additional operations. It is easy to read the program files by using some standard operations provided by the file system. Check word Segment, digital digest, or digital signature.
  • the system After the system generates a program file, it automatically sets the attribute options for the file, and records the number of bytes of the storage space occupied by the program file, that is, the size of the program, and the date and time of the program construction in the file attribute option.
  • the file system read program file's property options make it easy to get the program size and program construction time and time.
  • the present invention does not limit the specific form of the program summary and the specific calculation process, and can be obtained or derived directly from the program itself, and can be used to determine the uniqueness of the program, and belongs to the scope of the program summary of the present invention.
  • the calculation process of the program summary may also include or use information such as the version number that is not related to the program content; although the program summary is usually a set of fixed length numbers, and the length is significantly shorter than the original program, which can save calculation, acquisition and Compare the overhead, but you can also use a program summary that is longer, or even the program itself. Whatever the form of the program summary and the method used to obtain the program summary are within the scope of the present invention.
  • Step 102 The CPU forces the target program to be loaded for the chip.
  • the target program loading process is different, and the loading process of the target program is a well-known technology.
  • the target program data is transmitted in a fixed data frame format, and the transmission of one frame after another.
  • the length of its data frame varies with the device model.
  • the built-in counter of the chip counts the data transferred to the chip from 0.
  • the FPGA automatically checks the loaded target program data. Once an error is found, it immediately interrupts the loading of the target program and outputs an error flag to the CPU, telling the CPU that the loading process has terminated and the CPU needs to restart the loading process.
  • Step 103 The CPU reinitializes the chip. This step is used to perform the necessary initialization operations, and the reset chip execution time is much less than the loader time, so the system will not be made. The reset time is too long. chorus ,
  • step 103 is optional, and it may be determined according to actual conditions whether step 103 is to be performed: the step 103 may be performed after the determination is consistent in step 101, or after step 102, or in step 101. Step 103 is performed after the judgment is consistent and after step 102.
  • the FPGA chip is taken as an example to illustrate the initialization process of the chip:
  • the CPU first triggers the power-on/reset circuit inside the chip, then the FPGA clears the configurable memory in the chip, and judges the chip by detecting the level of the pin. Way of working.
  • the output pin needs to be placed in a high-impedance state.
  • the FPGA chip has a built-in delay circuit, which allows the chip to have enough time to complete the initialization operation.
  • the chip target program loading process if a valid chip reset signal is applied, the chip target program will be interrupted, the chip will be reinitialized, and the chip target program will be reloaded. After the chip enters normal operation, if the external forced input of a valid reset signal, the chip will be re-cut: 1 ⁇ 2 t.
  • the chip program loading method of the present invention is implemented by a CPU, and the method of the present invention can also be implemented by a programmable chip or a load control system.
  • the specific processing is as shown in FIG. The descriptions are similar, and therefore, are not described herein, but are all within the scope of the present invention.
  • the chip can be detected before loading the chip program to avoid meaningless repeated loading, thereby shortening the system reset restart time.
  • the system reset time can be shortened by more than 60% by using the technology of the present invention.
  • a programmable chip with a built-in nonvolatile memory such as an EPLD mainly uses a storage medium such as a flash memory, and the number of writes of such a medium is limited, the present invention can also reduce the number of times of loading for such a chip. Chip life.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

A chip program loading method comprises: A. determines whether a currently running chip accords with a target program to be loaded, and if yes, terminates the currently processing procedural flow; otherwise performs step B; B. toads said target program for said chip. By adopting the method of present invention, the time of system reset can be reduced, and reliability of system reset can be improved.

Description

一种芯片程序加载方法  Chip program loading method
技术领域 Technical field
本发明涉及可编程芯片技术， 特别涉及一种可编程芯片的程序加载 技术。 发明背景  The present invention relates to programmable chip technology, and more particularly to a program loading technique for a programmable chip. Background of the invention
微电子技术经过 50多年的发展， 目前进入一个很关键的时期， 工艺 尺寸越来越小， 集成度越来越高， 与其它学科结合越来越紧密。 而逻辑 器件领域是微电子技术的一个重要发展分支， 目前此领域内发展最快的 是可编程芯片。 可编程芯片 （Programmable Chip )泛指各种在使用前需 要进行程序加载的电子芯片， 在现代电子产品中大量使用， 包括但不限 于现场可编程门阵列 （Field Programmable Gate Array , 筒称" FPGA" )、 数字信号处理器（Digital Signal Processor, 筒称" DSP'，）、 可擦可编程逻 辑器件（Erasable Programmable Logic Device , 简称 "EPLD" )等逻辑器 件。  After more than 50 years of development, microelectronics technology has entered a critical period. The process size is getting smaller and smaller, the integration is getting higher and higher, and it is more and more closely integrated with other disciplines. The field of logic devices is an important development branch of microelectronics technology, and the fastest growing in this field is programmable chips. Programmable Chip refers to a variety of electronic chips that need to be loaded before use. It is widely used in modern electronic products, including but not limited to Field Programmable Gate Array (FPGA). ), digital signal processor (Digital Signal Processor, "DSP"), Erasable Programmable Logic Device (EPLD) and other logic devices.
可编程芯片研制周期较短， 直接开发费用较低， 也没有限定最少订 购数量， 随着门电路成本的降低和器件中门电路数量的增加， 可编程芯 片正大举打入传统的门阵列领域， 但是各家公司都在利用可编程芯片的 灵活性把自己的产品设计得不同于竟争对手的产品， 同样， 半导体厂商 已经开发出独特的 EPLD和 FPGA等， 以便在性能、 功耗、 集成度和成 本等方面达到特定的目标。 这样的做法导致这类可编程芯片在功能领域 和复杂度上存在明显差异。  The programmable chip development cycle is short, the direct development cost is low, and the minimum order quantity is not limited. As the cost of the gate circuit decreases and the number of gate circuits in the device increases, the programmable chip is entering the traditional gate array field. But companies are using the flexibility of programmable chips to design their products differently than their competitors. Similarly, semiconductor manufacturers have developed unique EPLDs and FPGAs for performance, power, and integration. And achieve specific goals in terms of cost and other aspects. Such an approach leads to significant differences in the functional areas and complexity of such programmable chips.
但不管此类可编程芯片有多么大的差异， 都具有一个共同点， 即按 照前述定义中描述的， 在使用前需要为其加载程序。 可编程芯片的程序 加载过程通常是在中央处理器（ CentraJ Processing Unit 筒称" CPU" ) 上电或复位完成后进行， 并由 CPU控制整个加载过程。 以 FPGA为例， 整个可编程芯片的设计过程是这样的：首先釆用硬件描述语言（ Hardware Description Language, 筒称" HDL" ) 以类似于编程的方式描述硬件结构 和硬件行为； 然后用设计工具将这些描述综合映射成与半导体工艺有关 的硬件工艺文件， 这些描述和软件领域中的程序非常类似， 可编程芯片 则是这些硬件工艺文件的载体； 最后通过特殊的写入工具将硬件工艺文 件加载到可编程芯片上， 使之具有相应的功能。 But no matter how big the difference between such programmable chips, they all have one thing in common, that is, as described in the foregoing definition, the program needs to be loaded before use. Programmable chip program The loading process is usually performed after the central processor (CenraJ Processing Unit cartridge "CPU") is powered up or reset, and the CPU controls the entire loading process. Taking an FPGA as an example, the design process of the entire programmable chip is as follows: First, use the hardware description language (Hardware Description Language, "HDL") to describe the hardware structure and hardware behavior in a similar way to programming; then use the design tool These descriptions are comprehensively mapped into hardware process files related to semiconductor processes. These descriptions are very similar to those in the software field. Programmable chips are the carriers of these hardware process files. Finally, hardware process files are loaded by special writing tools. On the programmable chip, it has the corresponding function.
由此可见， 程序加载是整个可编程芯片设计的关键步骤。 虽然各种 可编程芯片的程序加载技术和加载过程都不尽相同， 但都应该满足可 靠、 快速、 稳定的要求， 此外还必须充分考虑到芯片使用寿命和***升 级过程。  Thus, program loading is a critical step in the overall programmable chip design. Although the program loading technology and loading process of various programmable chips are different, they should meet the requirements of reliable, fast, and stable. In addition, the chip life and system upgrade process must be fully considered.
常用的加载技术包括下面两种：  Commonly used loading techniques include the following two:
第一种是目前最常见的加载技术： 简单加载法。 这种方法多用于 FPGA、 DSP等可多次反复加载的可编程芯片。 具体的实现方法是 CPU 上电或复位完成后， 直接对可编程芯片进行强制加载， 使之具有特定的 功能。这种方法简单有效， 容易实现，也可以充分满足***升级的要求。  The first is the most common loading technique at the moment: simple loading. This method is mostly used in programmable chips that can be repeatedly loaded and loaded, such as FPGA and DSP. The specific implementation method is to force the programmable chip to be loaded directly after the CPU is powered on or reset, so that it has a specific function. This method is simple and effective, easy to implement, and can fully meet the requirements of system upgrade.
第二种方法是版本检查加载法， 适用于 EPLD等自带非易失性存储 器的可编程芯片。具体的实现方法是 CPU在加载前先对可编程芯片进行 版本检测， 即检查其自带非易失性存储器上存储的程序和待加载的程序 版本是否一致， 如果检测结果和待加载的程序版本一致， 则不进行加载 操作。 这种方法可以减少无效重复加载的次数。  The second method is the version check loading method, which is applicable to programmable chips such as EPLDs with their own non-volatile memory. The specific implementation method is that the CPU performs version detection on the programmable chip before loading, that is, checks whether the program stored on the non-volatile memory and the version of the program to be loaded are consistent, if the detection result and the program version to be loaded. Consistent, no load operation is performed. This method can reduce the number of invalid repeated loads.
在实际应用中， 上述方案存在以下问题： 对于第一种方案， 由于无 意义的重复加载次数多， 消耗芯片的使用寿命， 因此这种方案仅仅适用 于可以多次反复加载的芯片， 例如 FPGA和 DSP; 另外， 由于芯片加载 需要耗费较长时间， 因此这种强制加载的方式普遍¾延长了***初始化 所需的时间， 然而在很多情况下， 尤其是***带电复位是， 并不需要这 种额外的程序加载。 In practical applications, the above solution has the following problems: For the first solution, since the number of meaningless reloads is large and the life of the chip is consumed, this solution is only applicable to chips that can be repeatedly loaded multiple times, such as FPGA and DSP; in addition, due to chip loading It takes a long time, so this forced loading method generally extends the time required for system initialization, but in many cases, especially system charging reset, this additional program loading is not required.
对于第二种方案， 由于这种方案需要在发布的芯片程序中附带一个 不重复的版本号， 因此给***升级带来不便。 具体的说， 如果采用开发 者预先设置的版本号， 则由于一般开发计划只规划到大版本， 导致内部 小测试版本和不定版本采用相同版本号， 升级到这些版本时就不得不采 用手工强制升级， 造成***升级不可靠和不方便； 如果根据程序编译时 间生成版本号， 则对于不采用 "日构造，，方法的公司来说， 难以进行管理 和实施。 发明内容  For the second option, since this solution requires a non-repeating version number in the released chip program, it is inconvenient for system upgrade. Specifically, if the developer's pre-set version number is adopted, since the general development plan only plans to the large version, the internal small test version and the indefinite version use the same version number, and the manual forced upgrade is required when upgrading to these versions. It is unreliable and inconvenient to upgrade the system; if the version number is generated according to the program compile time, it is difficult for the company that does not adopt the "day structure" method to manage and implement it.
有鉴于此， 本发明的主要目的在于提供一种芯片程序加载方法， 避 免芯片程序的重复加载， 缩短***复位时间， 提高芯片使用寿命， 保证 ***升级的可靠性。  In view of this, the main object of the present invention is to provide a chip program loading method, which avoids repeated loading of a chip program, shortens system reset time, improves chip life, and ensures system upgrade reliability.
为达到上述目的， 本发明的技术方案是这样实现的：  In order to achieve the above object, the technical solution of the present invention is achieved as follows:
本发明公开了一种芯片程序加载方法， 该方法包括：  The invention discloses a chip program loading method, which comprises:
A.判断芯片当前运行的程序与待加载的目标程序是否一致， 如果一 致， 则结束当前处理流程； 否则执行步骤 B;  A. It is judged whether the program currently running by the chip is consistent with the target program to be loaded, and if so, the current processing flow is ended; otherwise, step B is performed;
B.为所述芯片加载所述目标程序。  B. loading the target program for the chip.
步骤 A中， 当判断一致时， 在结束当前处理流程之前进一步包括： 初始化所述芯片； 和 /或， 在所述步骤 B之后进一步包括： 初始化所述芯 片。  In step A, when the determination is consistent, before the end of the current processing flow, the method further includes: initializing the chip; and/or, after the step B, further comprising: initializing the chip.
步驟 A中， 所述判断当前运行的程序与待加载的目标程序是否一致 为： 从芯片当前运行的程序和待加载的目标程序中分别获取用于标识程 序唯一性的程序摘要； 判断所述芯片 . 前运行的程序 0¾ 序摘要与所述 待加载的目标程序的程序摘要是否一致。 In step A, the determining whether the currently running program is consistent with the target program to be loaded is: obtaining the identification process from the program currently running on the chip and the target program to be loaded respectively. A program summary of the uniqueness of the sequence; determining whether the program of the pre-running program is consistent with the program summary of the target program to be loaded.
步骤 Α中， 所述程序摘要为程序的数字摘要、 数字签名、 程序内容 校验字段、 程序大小、 程序构造日期和时间、 程序本身这六者中的任意 一种或这六者的任意组合。  In the step, the program summary is any one of the program's digital digest, digital signature, program content check field, program size, program construction date and time, and the program itself, or any combination of the six.
步骤 A中， 所述程序摘要为定长或变长的数据。  In step A, the program summary is data of fixed length or variable length.
其中， 所述芯片为现场可编程门阵列 FPGA、 或可擦编程逻辑器件 EPLD、 或数字信号处理器 DSP。  The chip is a field programmable gate array FPGA, or an erasable programming logic device EPLD, or a digital signal processor DSP.
其中， 该方法由中央处理器 CPU实现、 或由可编程芯片实现、 或由 加载控制***来实现。  Wherein, the method is implemented by a central processing unit CPU, or by a programmable chip, or by a load control system.
其中， 在步骤 A所述判断之前进一步包括： 判断所述芯片的功能是 否正常， 如果是， 则继续执行步骤 A所述判断， 否则执行步骤 B。  Before the determining in step A, the method further includes: determining whether the function of the chip is normal, and if yes, continuing to perform the determining in step A, otherwise performing step B.
步骤 A中， 当所述芯片为 FPGA或 EPLD时， 所述判断芯片的功能 操作来进行判断。  In step A, when the chip is an FPGA or an EPLD, the function of the determining chip is judged.
步骤 A中， 当所述芯片为 DSP时，所述判断芯片的功能是否正常的 方法为： 通过通信链路进行 DSP与 CPU之间的环回测试来进行判断。  In the step A, when the chip is a DSP, the method for determining whether the function of the chip is normal is: performing a loopback test between the DSP and the CPU through the communication link to perform judgment.
由上述方案可以看出， 本发明的关键在于： 在芯片程序加载之前， 判断芯片当前运行的程序与待加载的目标程序是否一致， 当判断不一致 时， 才对芯片进行程序加载处理。  It can be seen from the above solution that the key of the present invention is: Before the chip program is loaded, it is judged whether the program currently running by the chip is consistent with the target program to be loaded, and when the judgment is inconsistent, the program loading process is performed on the chip.
因此， 本发明所提供的芯片程序加载方法， 能显著缩短***复位的 时间， 提高***复位效率， 由于避免了无效的芯片程序重复加载， 因此 也延长了芯片的使用寿命， 从而提高整个***的性能。 -附图简要说明 ―― -- ― -―… 图 1为本发明方法一较佳实施例处理流程示意图。 实施本发明的方式 为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对 本发明作进一步地详细描述。 Therefore, the chip program loading method provided by the invention can significantly shorten the system reset time, improve the system reset efficiency, and avoid the repeated loading of the invalid chip program, thereby prolonging the service life of the chip, thereby improving the performance of the whole system. . - BRIEF DESCRIPTION OF THE DRAWINGS - - - - - Figure 1 is a schematic diagram of the processing flow of a preferred embodiment of the method of the present invention. The present invention will be further described in detail below with reference to the accompanying drawings.
本发明公开了一种芯片程序加载方法， 其主要设计思想在于： 在准 备加载程序之前， 首先判断芯片当前运行的程序和待加载的目标程序是 否一致， 只有在判断不一致时才加载该目标程序， 从而避免了对芯片程 序的重复加载。  The invention discloses a chip program loading method, and the main design idea thereof is: firstly, before preparing the loading program, first determining whether the current running program of the chip and the target program to be loaded are consistent, and loading the target program only when the judgment is inconsistent, This avoids repeated loading of the chip program.
由于芯片功能出现异常时， 必须要重新加载芯片的程序， 因此， 可 在判断当前程序与目标程序是否一致之前， 首先判断： 芯片的功能是否 正常， 如果正常， 则继续判断当前程序与目标程序是否一致； 如果不正 常， 则直接对芯片进行程序加载处理。  When the chip function is abnormal, the program of the chip must be reloaded. Therefore, before judging whether the current program is consistent with the target program, it is first determined whether the function of the chip is normal, and if it is normal, it continues to determine whether the current program and the target program are normal. Consistent; If not, directly load the chip into the program.
图 1为本发明方法一较佳实施例处理流程示意图。 本实施例中， 由 CPU来实现本发明程序加载过程。 如图 1所示， 具体处理包括：  FIG. 1 is a schematic diagram of a processing flow of a preferred embodiment of a method according to the present invention. In this embodiment, the program loading process of the present invention is implemented by a CPU. As shown in Figure 1, the specific processing includes:
步骤 100: CPU判断芯片的功能是否正常， 如果正常， 则执行步驟 101； 否则执行步骤 102。  Step 100: The CPU determines whether the function of the chip is normal. If it is normal, step 101 is performed; otherwise, step 102 is performed.
其中， CPU可通过执行预设的检测程序对可编程芯片的功能进行检 测， 从而判断芯片是否能正常工作。 根据背景技术可知， 本文所述的芯 片可以为 DSP、 或 FPGA、 或 EPLD。 对于不同的芯片而言， 本步骤中 CPU执行的检测程序将有所不同：  The CPU can detect the function of the programmable chip by executing a preset detection program to determine whether the chip can work normally. According to the background art, the chip described herein can be a DSP, or an FPGA, or an EPLD. For different chips, the test procedure executed by the CPU in this step will be different:
当判断 DSP芯片的功能是否正常时， 可通过通信链路进行 DSP与 CPU之间的环回测试来进行判断。 所谓环回测试， 具体来说就是： CPU 预设一个数据， 并通过其与 DSP之间的通信链路向 DSP发送一个测试 数据。 接肴， DSP处理来自 CPU测 据， J将处 ¾ί结果通过 CPU 与 DSP之间的通信链路返回给 CPU。 CPU再将来自 DSP的处理结果与 其预设的数据作比较， 判断二者是否一致， 如果完全一致， 则表示 DSP 能正常工作， DSP芯片的功能正常； 如果不完全一致， 则表示 DSP不能 正常工作， DSP芯片的功能异常。 When it is judged whether the function of the DSP chip is normal, the loopback test between the DSP and the CPU can be performed through the communication link to make a judgment. The so-called loopback test, specifically: the CPU presets a data and sends a test to the DSP through its communication link with the DSP. Data. In the case of food, the DSP processes the data from the CPU, and J returns the result to the CPU through the communication link between the CPU and the DSP. The CPU then compares the processing result from the DSP with its preset data to determine whether the two are consistent. If they are completely consistent, it means that the DSP can work normally, and the function of the DSP chip is normal; if not completely consistent, the DSP cannot work normally. The function of the DSP chip is abnormal.
另一方面， 当判断 FPGA或 EPLD芯片的功能是否正常时， 可通过 对芯片中已知地址的检测寄存器进行读写操作来进行判断。 该检测寄存 器包括： 检测输入寄存器和检测输出寄存器。 所谓对检测寄存器进行读 写操作，具体来说就是： CPU预设一个数据，通过地址总线和数据总线， 将其写入到该芯片中已知地址的检测输入寄存器中。 芯片内部的逻辑单 元， 对检测输入寄存器的数据按特定计算规则进行计算处理， 然后将处 理后的数据发送至芯片中已知地址的检测输出寄存器。 然后， CPU读取 芯片中该检测输出寄存器的数据， 将所读取的数据和之前写入到该检测 输入寄存器的数据进行比较， 判断两个数据是否符合所述特定计算规 则， 如果符合， 则表示检测寄存器能正常工作， 该芯片的功能正常； 如 果不符合， 则表示检测寄存器不能正常工作， 该芯片的功能异常。  On the other hand, when it is judged whether the function of the FPGA or the EPLD chip is normal, it can be judged by reading and writing the detection register of a known address in the chip. The detection register includes: a detection input register and a detection output register. The so-called read and write operation of the detection register, specifically: the CPU presets a data, writes it to the detection input register of the known address in the chip through the address bus and the data bus. The logic unit inside the chip calculates and processes the data of the detection input register according to a specific calculation rule, and then sends the processed data to the detection output register of the known address in the chip. Then, the CPU reads the data of the detection output register in the chip, compares the read data with the data previously written to the detection input register, and determines whether the two data meet the specific calculation rule, and if yes, Indicates that the detection register can work normally, and the function of the chip is normal; if it does not match, it means that the detection register is not working properly, and the function of the chip is abnormal.
步骤 101: CPU判断芯片当前运行的程序是否与待加载的目标程序 一致， 如果一致， 则执行步骤 103 , 否则执行步骤 102。  Step 101: The CPU determines whether the currently running program of the chip is consistent with the target program to be loaded. If yes, step 103 is performed; otherwise, step 102 is performed.
本步骤中， 可从芯片当前运行的程序和待加载的目标程序中分别获 取用于标识程序唯一性的程序摘要， 然后判断芯片当前运行的程序的程 序摘要与所述待加载的目标程序的程序摘要是否一致， 如果一致， 则表 示芯片当前运行的程序与待加载的目标程序一致； 如果不一致， 则表示 芯片当前运行的程序与待加载的目标程序不一致。  In this step, a program summary for identifying the uniqueness of the program may be separately obtained from a program currently running by the chip and a target program to be loaded, and then a program summary of the program currently running by the chip and a program of the target program to be loaded may be determined. Whether the sum is consistent, if they are consistent, it means that the current running program of the chip is consistent with the target program to be loaded; if it is inconsistent, it means that the program currently running on the chip is inconsistent with the target program to be loaded.
上述用于标识程序唯一性的程序摘要的独特之处在于， 该程序摘要 可通过程序文件直接获得或导出， 而无需人为设置。 该程序摘要可以是 程序的数字摘要、 数字签名、 程序内容校验字段、—程序大小 卷序构造 曰期和时间、 程序本身等这几项中的任意一项或这几项的任意组合， 为 进一步了解本发明方法的处理原理， 下面对这几种程序摘要的意义加以 许细说明。 The above-mentioned program summary for identifying the uniqueness of a program is unique in that the program summary can be directly obtained or exported through a program file without artificial setting. The program summary can be Any one of the program's digital digest, digital signature, program content check field, program size reel construction period and time, program itself, etc., or any combination of these, for further understanding of the method of the present invention The processing principle, the following is a brief description of the meaning of these several program abstracts.
一、 数字摘要  First, the digital summary
数字摘要是在对程序内容使用某种摘要算法进行计算的过程中得到 的。 对不同的程序来说， 其内容不完全一致， 则使用同一种摘要算法分 别对其内容进行计算得到的数字摘要也会不同。  Digital summaries are obtained during the calculation of program content using a certain digest algorithm. For different programs, the content is not completely consistent, and the digital summary calculated by using the same digest algorithm to calculate its content will be different.
二、 数字签名  Second, digital signature
数字签名是在对程序内容使用已知的公共密钥和签名算法进行计算 的过程中得到的。 对不同的程序来说， 其程序内容不完全一致， 则使用 同一公共密钥和签名算法对其内容进行计算得到的数字签名也会不同。  Digital signatures are obtained during the calculation of program content using known public keys and signature algorithms. For different programs, the program content is not completely consistent, and the digital signature calculated by using the same public key and signature algorithm to calculate its content will be different.
三、 程序内容校验字段  Third, the program content check field
程序内容校验字段是对程序内容使用校验算法进行计算得到的校验 字段， 比如循环冗余校验码（Cyclic Redundancy Check, 筒称" CRC，）。 对不同的程序来说， 其内容不完全一致， 则使用同一校验算法对其内容 进行计算得到的校脸字段也会不同。  The program content check field is a check field calculated by using a check algorithm for the program content, such as a Cyclic Redundancy Check (CRC), for different programs, the content is not If they are identical, the face field calculated by using the same check algorithm to calculate the content will be different.
四、 程序的大小  Fourth, the size of the program
通常， 对于两个不同的程序， 其大小也是不同的。  Usually, the size is different for two different programs.
五、 程序构造日期和时间  Fifth, the program constructs the date and time
通常， 对两个不同的程序而言， 其构造日期和时间一^:不同。  Usually, for two different programs, the construction date and time are different.
为使本步骤的判断更加准确， 所述程序摘要还可为上述若干种程序 摘要的任意组合。 值得一提的是， 目前多数文件格式已经包含了校验字 段、 数字摘要或者数字签名， 这样， ***不需要进行额外的运算， 只要 利用文件***提供的一些标准操作就很容易读取到程序文件的校验字 段、 数字摘要或者数字签名。 此外， ***生成一个程序文件后， 就会自 动为文件设置属性选项 , 并在文件属性选项中记录程序文件所占存储空 间的字节数即程序的大小、 以及程序构造的日期和时间， 这样利用文件 ***读取程序文件的属性选项就很容易获取到程序的大小和程序构造 曰期和时间。 In order to make the judgment of this step more accurate, the program summary may also be any combination of the above several program summaries. It is worth mentioning that most file formats currently contain check fields, digital digests, or digital signatures. This way, the system does not need to perform additional operations. It is easy to read the program files by using some standard operations provided by the file system. Check word Segment, digital digest, or digital signature. In addition, after the system generates a program file, it automatically sets the attribute options for the file, and records the number of bytes of the storage space occupied by the program file, that is, the size of the program, and the date and time of the program construction in the file attribute option. The file system read program file's property options make it easy to get the program size and program construction time and time.
这里， 本发明并不限定程序摘要的具体形式和具体的计算过程， 只 要能从程序本身直接获得或导出， 并能用于确定程序的唯一性， 就属于 本发明所述程序摘要的范畴。 其中， 程序摘要的计算过程还可包含或使 用版本号等与程序内容无关的信息； 虽然程序摘要通常是一组定长的数 字， 且长度明显比原始程序要短， 这样可以节省计算、 获取和比较的开 销， 但也可以使用变长的程序摘要， 甚至可以为程序本身。 无论采用何 种形式的程序摘要以及用何种方法来获得程序摘要， 均属本发明的保护 范围。  Here, the present invention does not limit the specific form of the program summary and the specific calculation process, and can be obtained or derived directly from the program itself, and can be used to determine the uniqueness of the program, and belongs to the scope of the program summary of the present invention. The calculation process of the program summary may also include or use information such as the version number that is not related to the program content; although the program summary is usually a set of fixed length numbers, and the length is significantly shorter than the original program, which can save calculation, acquisition and Compare the overhead, but you can also use a program summary that is longer, or even the program itself. Whatever the form of the program summary and the method used to obtain the program summary are within the scope of the present invention.
步骤 102: CPU为该芯片强制加载目标程序。  Step 102: The CPU forces the target program to be loaded for the chip.
对于不同的芯片而言， 其目标程序加载过程不尽相同， 并且目标程 序的加载过程属公知技术。 下面以 FPGA芯片为例， 对目标程序的加载 过程加以筒要说明： 目标程序数据以固定的数据帧格式传送， 一帧接一 帧的传送。 其数据帧的长度随着器件型号的不同而有所差异。 加载开始 后，芯片内置的计数器便从 0开始对传送到芯片内部的数据作加法计数， 当计数的值与目标程序的大小相同时， 则表示目标程序加载结束。 目标 程序在加载的过程当中， FPGA 自动检查加载的目标程序数据， 一旦发 现错误， 就立即中断目标程序的加载， 并输出出错标志给 CPU, 告诉 CPU加载过程已终止， CPU需要重新启动加载过程。  For different chips, the target program loading process is different, and the loading process of the target program is a well-known technology. The following takes the FPGA chip as an example to describe the loading process of the target program: The target program data is transmitted in a fixed data frame format, and the transmission of one frame after another. The length of its data frame varies with the device model. After the loading starts, the built-in counter of the chip counts the data transferred to the chip from 0. When the value of the counter is the same as the size of the target program, it indicates that the target program is loaded. During the loading process, the FPGA automatically checks the loaded target program data. Once an error is found, it immediately interrupts the loading of the target program and outputs an error flag to the CPU, telling the CPU that the loading process has terminated and the CPU needs to restart the loading process.
步骤 103: CPU重新初始化芯片。 本步骤用于执行必要的初始化操 作， 而且复位芯片的执行时间远少于加载程序的时间， 因此不会使*** 复位的时间过长。 „ , Step 103: The CPU reinitializes the chip. This step is used to perform the necessary initialization operations, and the reset chip execution time is much less than the loader time, so the system will not be made. The reset time is too long. „ ,
需要说明的是， 步骤 103是可选的， 可根据实际情况确定是否要执 行步骤 103: 可在步驟 101 中判断一致后执行该步骤 103 , 或者在步骤 102之后执行该步骤 103 , 或者在步骤 101中判断一致后和步驟 102之 后均要执行步骤 103。  It should be noted that step 103 is optional, and it may be determined according to actual conditions whether step 103 is to be performed: the step 103 may be performed after the determination is consistent in step 101, or after step 102, or in step 101. Step 103 is performed after the judgment is consistent and after step 102.
另外， 不同类型芯片的初始化过程也一^：不尽相同， 并且芯片的初 始化过程属公知技术。 下面以 FPGA芯片为例对芯片的初始化过程加以 筒要说明： CPU首先触发芯片内部的加电 /复位电路， 接着 FPGA清除 片内的可配置存储器， 并通过检测引脚的电平来判断芯片的工作方式。 芯片初始化时需要将输出引脚置成高阻状态， 一般 FPGA芯片内置有延 时电路， 使得芯片有足够的时间完成初始化操作。 需要说明的是， 在芯 片目标程序加载过程中， 如果施加有效的芯片复位信号， 则芯片目标程 序将被中断， 使芯片重新初始化， 并重新加载芯片目标程序。 在芯片进 入正常工作状态后， 如果外界强制施加有效复位信号， 则芯片也会重新 刀: ½ t。  In addition, the initialization process of different types of chips is also different, and the initialization process of the chips is a well-known technique. The FPGA chip is taken as an example to illustrate the initialization process of the chip: The CPU first triggers the power-on/reset circuit inside the chip, then the FPGA clears the configurable memory in the chip, and judges the chip by detecting the level of the pin. Way of working. When the chip is initialized, the output pin needs to be placed in a high-impedance state. Generally, the FPGA chip has a built-in delay circuit, which allows the chip to have enough time to complete the initialization operation. It should be noted that during the chip target program loading process, if a valid chip reset signal is applied, the chip target program will be interrupted, the chip will be reinitialized, and the chip target program will be reloaded. After the chip enters normal operation, if the external forced input of a valid reset signal, the chip will be re-cut: 1⁄2 t.
上述实施例中， 由 CPU来实现本发明芯片程序加载方法， 本发明方 法也可由可编程芯片或加载控制***来实现， 当由可编程芯片或加载控 制***来实现时， 具体处理与图 1所述类似， 因此， 本文不再——描述， 但均在本发明保护范围内。  In the above embodiment, the chip program loading method of the present invention is implemented by a CPU, and the method of the present invention can also be implemented by a programmable chip or a load control system. When implemented by a programmable chip or a load control system, the specific processing is as shown in FIG. The descriptions are similar, and therefore, are not described herein, but are all within the scope of the present invention.
综上所述，应用本发明方法， 可在加载芯片程序前对芯片进行检测， 以避免无意义的重复加载，从而缩短***复位重启时间。以 FPGA为例， 采用本发明技术可使***复位时间缩短达 60%以上。 由于 EPLD等内置 非易失性存储器的可编程芯片， 主要使用闪存（Flash )等存储介质， 而 这类介质的写次数有限， 因此， 针对这类芯片， 本发明技术还可减少加 载次数以延长芯片使用寿命。 以上所述仅为本发明—的较佳.实旅例而已， 并_非用于限定本发明的保 护范围。 凡在本发明的精神和原则之内所作的任何修改、 等同替换、 改 进等， 均包含在本发明的保护范围内。 In summary, by applying the method of the present invention, the chip can be detected before loading the chip program to avoid meaningless repeated loading, thereby shortening the system reset restart time. Taking the FPGA as an example, the system reset time can be shortened by more than 60% by using the technology of the present invention. Since a programmable chip with a built-in nonvolatile memory such as an EPLD mainly uses a storage medium such as a flash memory, and the number of writes of such a medium is limited, the present invention can also reduce the number of times of loading for such a chip. Chip life. The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalents, improvements, etc. made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

权利要求书 Claim
1、 一种芯片程序加载方法， 其特征在于， 该方法包括：  A chip program loading method, characterized in that the method comprises:
A.判断芯片当前运行的程序与待加载的目标程序是否一致， 如果一 致， 则结束当前处理流程； 否则执行步驟 B;  A. It is judged whether the program currently running by the chip is consistent with the target program to be loaded, and if so, the current processing flow is ended; otherwise, step B is performed;
B.为所述芯片加载所述目标程序。  B. loading the target program for the chip.
2、 根据权利要求 1所述的方法， 其特征在于， 步骤 A中， 当判断 一致时， 在结束当前处理流程之前进一步包括： 初始化所述芯片； 和 / 在所述步驟 B之后进一步包括： 初始化所述芯片。  2. The method according to claim 1, wherein, in step A, when the determination is consistent, before the end of the current processing flow, the method further comprises: initializing the chip; and/ after the step B further comprising: initializing The chip.
3、 根据权利要求 1所述的方法， 其特征在于， 步骤 A中， 所述判 断当前运行的程序与待加载的目标程序是否一致为：  3. The method according to claim 1, wherein in step A, the determining whether the currently running program is consistent with the target program to be loaded is:
从芯片当前运行的程序和待加载的目标程序中分别获取用于标识程 序唯一性的程序摘要； 判断所述芯片当前运行的程序的程序摘要与所述 待加载的目标程序的程序摘要是否一致。  Obtaining, from the program currently running by the chip and the target program to be loaded, respectively, a program summary for identifying the uniqueness of the program; determining whether the program summary of the program currently running by the chip is consistent with the program summary of the target program to be loaded.
4、 根据权利要求 3所述的方法， 其特征在于， 步骤 A中， 所述程 序摘要为程序的数字摘要、 数字签名、 程序内容校验字段、 程序大小、 程序构造日期和时间、 程序本身这六者中的任意一种或这六者的任意组 合。  4. The method according to claim 3, wherein in step A, the program summary is a digital summary of the program, a digital signature, a program content check field, a program size, a program construction date and time, and the program itself. Any of the six or any combination of the six.
5、 根据权利要求 3或 4所述的方法， 其特征在于， 步驟 A中， 所 述程序摘要为定长或变长的数据。  The method according to claim 3 or 4, wherein in step A, the program summary is data of fixed length or variable length.
6、根据权利要求 1至 4任一项所述的方法， 其特征在于， 所述芯片 为现场可编程门阵列 FPGA、 或可擦编程逻辑器件 EPLD、 或数字信号 处理器 DSP。  The method according to any one of claims 1 to 4, wherein the chip is a field programmable gate array FPGA, or an erasable programming logic device EPLD, or a digital signal processor DSP.
7、根据权利要求 1至 4任一项所述的方法， 其特征在于， 该方法由 中央处理器 CPU实现、或由可编程芯片实现、或由加载控制***来实现。 7. A method according to any one of claims 1 to 4, characterized in that the method is implemented by a central processing unit CPU, or by a programmable chip, or by a load control system.
8、根据权利要求 1至 4任一项所述的方法， 其特征在于， 在步驟 A 所述判断之前进一步包括： The method according to any one of claims 1 to 4, further comprising: before the determining in step A, further comprising:
判断所述芯片的功能是否正常， 如果是， 则继续执行步骤 A所述判 断， 否则执行步驟 B。  It is judged whether the function of the chip is normal, and if so, the judgment described in step A is continued, otherwise step B is performed.
9、 根据权利要求 8所述的方法， 其特征在于， 步骤 A中， 当所述 芯片为 FPGA或 EPLD时， 所述判断芯片的功能是否正常的方法为： 通过对所述芯片中已知地址的检测寄存器进行读写操作来进行判 断。  The method according to claim 8, wherein in the step A, when the chip is an FPGA or an EPLD, the method for determining whether the function of the chip is normal is: by using a known address in the chip The detection register performs read and write operations to determine.
10、 根据权利要求 8所述的芯片程序加载方法， 其特征在于， 步驟 A中， 当所述芯片为 DSP时， 所述判断芯片的功能是否正常的方法为： 通过通信链路进行 DSP与 CPU之间的环回测试来进行判断。  The chip program loading method according to claim 8, wherein in the step A, when the chip is a DSP, the method for determining whether the function of the chip is normal is: performing DSP and CPU through a communication link. A loopback test between them is used to make a judgment.
PCT/CN2005/001512 2004-09-23 2005-09-20 A chip program loading method WO2006032196A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200410083025.9 2004-09-23
CNB2004100830259A CN100342335C (en) 2004-09-23 2004-09-23 Chip program loading method

Publications (1)

Publication Number Publication Date
WO2006032196A1 true WO2006032196A1 (en) 2006-03-30

Family

ID=36089846

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2005/001512 WO2006032196A1 (en) 2004-09-23 2005-09-20 A chip program loading method

Country Status (2)

Country Link
CN (1) CN100342335C (en)
WO (1) WO2006032196A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112306402A (en) * 2020-07-31 2021-02-02 神州融安科技（北京）有限公司 Program execution method, electronic device, and computer-readable storage medium
CN112711560A (en) * 2021-02-10 2021-04-27 西南电子技术研究所（中国电子科技集团公司第十研究所） Reconstruction method for single-point connection RapidIO bus of ZYNQ chip

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8429218B2 (en) * 2006-04-06 2013-04-23 International Business Machines Corporation Process restart on a compute node
CN101441574B (en) * 2007-11-20 2011-10-26 中兴通讯股份有限公司 Multiple-FPGA logical loading method in embedded system
TWI499929B (en) * 2012-03-09 2015-09-11 Nuvoton Technology Corp Programming system
CN103677876A (en) * 2012-09-12 2014-03-26 中兴通讯股份有限公司 Manufacturing and installing method, device and system of software installation package
CN104102563A (en) * 2014-07-10 2014-10-15 浪潮(北京)电子信息产业有限公司 Method and device for finding MCA (machine check architecture) errors of server system
CN109120432B (en) * 2018-07-18 2021-10-15 北京奇艺世纪科技有限公司 Fault server positioning method and device
CN109032660A (en) * 2018-07-31 2018-12-18 北京城市网邻信息技术有限公司 A kind of generation method of VersionCode, device, electronic equipment and storage medium
CN112685089A (en) * 2020-08-06 2021-04-20 艾德克斯电子（南京）有限公司 Communication board system suitable for various machines and working method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542075A (en) * 1992-05-06 1996-07-30 International Business Machines Corporation Method and apparatus for improving performance of out of sequence load operations in a computer system
US5974528A (en) * 1998-04-17 1999-10-26 Winbond Electronics Corp. Microcomputer with embedded flash memory having on-chip programming capability and method of programming data into the embedded flash memory
CN1467631A (en) * 2002-07-08 2004-01-14 华为技术有限公司 Method for dynamic loading program
CN1467629A (en) * 2002-07-08 2004-01-14 华为技术有限公司 Method for implementing dynamic loading of single board chip FIRMWARE program
CN1503488A (en) * 2002-11-21 2004-06-09 ��Ϊ�������޹�˾ Method for upgrading TRX monoboard program in WCDMA

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1160666A3 (en) * 2000-04-27 2005-03-23 Ncr International Inc. Switching versions of software in a system background
CN100426226C (en) * 2002-08-16 2008-10-15 中兴通讯股份有限公司 Single board edition automatic loading method
CN1253786C (en) * 2002-10-18 2006-04-26 华为技术有限公司 Loading method for digital signal processing program

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542075A (en) * 1992-05-06 1996-07-30 International Business Machines Corporation Method and apparatus for improving performance of out of sequence load operations in a computer system
US5974528A (en) * 1998-04-17 1999-10-26 Winbond Electronics Corp. Microcomputer with embedded flash memory having on-chip programming capability and method of programming data into the embedded flash memory
CN1467631A (en) * 2002-07-08 2004-01-14 华为技术有限公司 Method for dynamic loading program
CN1467629A (en) * 2002-07-08 2004-01-14 华为技术有限公司 Method for implementing dynamic loading of single board chip FIRMWARE program
CN1503488A (en) * 2002-11-21 2004-06-09 ��Ϊ�������޹�˾ Method for upgrading TRX monoboard program in WCDMA

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112306402A (en) * 2020-07-31 2021-02-02 神州融安科技（北京）有限公司 Program execution method, electronic device, and computer-readable storage medium
CN112306402B (en) * 2020-07-31 2024-05-07 神州融安科技（北京）有限公司 Program execution method, electronic device, and computer-readable storage medium
CN112711560A (en) * 2021-02-10 2021-04-27 西南电子技术研究所（中国电子科技集团公司第十研究所） Reconstruction method for single-point connection RapidIO bus of ZYNQ chip
CN112711560B (en) * 2021-02-10 2023-05-26 西南电子技术研究所（中国电子科技集团公司第十研究所） Reconstruction method for single-point connection of ZYNQ chip to rapidIO bus

Also Published As

Publication number Publication date
CN100342335C (en) 2007-10-10
CN1752930A (en) 2006-03-29

Similar Documents

Publication Publication Date Title
WO2006032196A1 (en) A chip program loading method
US7296143B2 (en) Method and system for loading processor boot code from serial flash memory
US7310726B2 (en) Booting from non-linear memory
TWI408597B (en) Initialization of flash storage via an embedded controller
US7506208B2 (en) Apparatus and method for crisis recovery
US7650556B2 (en) System and method for checking and correcting BIOS errors
TWI307469B (en) System and method for fpga upgrade and method of fpga operation
US20060020844A1 (en) Recovery of custom BIOS settings
TWI710952B (en) Firmware update method and computer system
US20080294838A1 (en) Universal boot loader using programmable on-chip non-volatile memory
US20120117429A1 (en) Baseboard management controller and memory error detection method of computing device utilized thereby
US20050177709A1 (en) Apparatus and method for updating firmware
US20060064576A1 (en) Boot systems and methods
WO2012106912A1 (en) Method and system for dynamically upgrading chip and baseboard management controller thereof
US10606677B2 (en) Method of retrieving debugging data in UEFI and computer system thereof
WO2011063756A1 (en) Method and system for diagnosing apparatus
US20220318109A1 (en) Processing system, related integrated circuit, device and method
US10275299B2 (en) Efficient transfer of data from CPU to onboard management device
JPH1078889A (en) Microcomputer
KR101793282B1 (en) Micro computer
US20070005860A1 (en) Interrupt control system and method
US11422916B2 (en) Usage amount monitoring method and monitoring unit of electronic control unit for vehicle
US11327772B2 (en) Method of loading software code, corresponding system and vehicle equipped with such a system
US20090083021A1 (en) Emulation of ahci-based solid state drive using nand interface
CN111857882B (en) Extensible SSD card opening firmware loading method and device, computer equipment and storage medium

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05791932

Country of ref document: EP

Kind code of ref document: A1