CN107122274B - CPU test system and method based on FPGA reconstruction technology - Google Patents

Abstract

The invention discloses a CPU test system and a method based on FPGA reconstruction technology, wherein the system comprises a test machine platform module, an FPGA module, a switch circuit module and a CPU module to be tested; the test machine platform module is connected with the FPGA module; the FPGA module is connected with the switch circuit module; the switching circuit module is connected with the test machine platform module and the CPU module to be tested; and the CPU module to be tested is connected with the test machine platform module. According to the invention, an FPGA reconfiguration technology is adopted, the upper computer outputs an FPGA reconfiguration instruction, and limited resources of the reconfigurable FPGA are reconfigured out of a plurality of specific data transmission interfaces of a domestic CPU (Central processing Unit), namely JTAG interfaces and maintenance serial ports through a test machine, so that the problems of a newly designed CPU (Central processing Unit) are positioned more quickly and accurately by comparing test results of the plurality of specific data transmission interfaces, and the time is saved for the subsequent batch production of the CPU.

Description

CPU test system and method based on FPGA reconstruction technology

Technical Field

The invention relates to the technical field of CPU testing, in particular to a CPU testing system and method based on an FPGA reconstruction technology.

Background

With the development of the national information technology, the requirements for high integration and autonomous controllability are continuously improved, so that the research and development of a domestic CPU (central processing unit) are imperative. However, because the newly designed CPU has many test items and complicated test procedures, it takes a long time to test and verify the newly designed CPU to a technical maturity stage, and the test efficiency is low.

Disclosure of Invention

The invention aims to solve the problems mentioned in the background technology part by using a CPU testing system and a CPU testing method based on an FPGA reconstruction technology.

In order to achieve the purpose, the invention adopts the following technical scheme:

a CPU test system based on FPGA reconstruction technology comprises a test machine platform module, an FPGA module, a switch circuit module and a CPU module to be tested; the test machine platform module is connected with the FPGA module; the FPGA module is connected with the switch circuit module; the switching circuit module is connected with the test machine platform module and the CPU module to be tested; and the CPU module to be tested is connected with the test machine platform module.

Particularly, the test machine platform module comprises a test machine platform and an upper computer; the FPGA module comprises a reconfigurable FPGA, a JTAG connector, a first FLASH (FLASH memory) and a second FLASH; the CPU module to be tested comprises a domestic CPU, a level conversion chip module and a CPU functional interface module; the upper computer is connected with a test machine, and the test machine is connected with the reconfigurable FPGA, the domestic CPU and the switch circuit module; the test machine is used for providing a power supply signal, a clock signal and a reset signal for the domestic CPU, providing a power supply, a clock, a control signal and a reconfiguration signal for the reconfigurable FPGA, providing a control signal for the switch circuit module and connecting the reconfigurable FPGA through a maintenance input and output interface; one end of the domestic CPU is connected with the level conversion chip module, and the other end of the domestic CPU is connected with the switch circuit module through the maintenance input/output interface and the JTAG interface; the CPU functional interface module is connected with the level conversion chip module; the reconfigurable FPGA is connected with the switch circuit module through a maintenance input/output interface/JTAG interface; the JTAG connector is connected with the reconfigurable FPGA through a JTAG interface; the first FLASH is connected with the reconfigurable FPGA through a parallel port; the second FLASH is connected with the reconfigurable FPGA through an SPI bus; the JTAG connector is used for programming initial function logic to the reconfigurable FPGA; the first FLASH is used for storing a peripheral function interface test program of the domestic CPU, and the peripheral function interface test program in the first FLASH is called through the switch circuit module when the domestic CPU is tested; the second FLASH is used for storing a plurality of functional logics of the reconfigurable FPGA, and the testing machine selects the logic which needs to be loaded into the reconfigurable FPGA from the second FLASH according to the reconfiguration signal.

Based on the CPU test system, the invention also discloses a CPU test method based on the FPGA reconstruction technology, which comprises the following steps:

s101, a domestic CPU is used as a chip to be tested and is placed in a position to be tested;

step S102, starting a test machine by an upper computer, realizing the power-on operation of the test machine on a CPU module and an FPGA module to be tested, and giving out a clock and a reset signal;

step S103, performing initial logic programming on the reconfigurable FPGA through the JTAG connector;

step S104, the upper computer controls the test machine to send reconfiguration signals to the reconfigurable FPGA, and corresponding logic in the second FLASH is selected and loaded into the reconfigurable FPGA;

step S105, the test machine outputs a control signal to the switch circuit module, the switch circuit module calls a peripheral function interface test program of the domestic CPU pre-stored in the first FLASH, sends the peripheral function interface test program to the domestic CPU through the maintenance input/output interface, and starts a test through the upper computer;

step S106, after the upper computer starts the test, the test result is output to the upper computer through the switch circuit module, the reconfigurable FPGA and the test machine table in sequence, the upper computer judges whether the test result passes or not, if the test result passes, the passing prompt is displayed, and if the test result does not pass, the upper computer outputs a detailed test result;

step S107, controlled by the upper computer, a reconfiguration signal is given by a test machine, logic is loaded from the second FLASH under the condition of no power failure, and the logic function of the reconfigurable FPGA is reconfigured, so that another data transmission function interface required by the domestic CPU (Central processing Unit) is reconfigured to form a new JTAG interface, a peripheral function interface test program in the first FLASH is transmitted into the domestic CPU through the new JTAG interface, the test is started through the upper computer, and a test result is displayed back to the upper computer through a JTAG signal;

and S108, comparing the test results obtained in the S106 and the S107 by the upper computer, namely the test result of the domestic CPU.

The CPU test system and method based on the FPGA reconstruction technology provided by the invention adopt the FPGA reconstruction technology, the upper computer outputs the FPGA reconstruction instruction, and the limited resources of the reconfigurable FPGA are reconstructed out of a plurality of specific data transmission interfaces of the domestic CPU, namely JTAG interfaces and maintenance serial ports through the test machine, so that the problems of newly designed CPUs are positioned more quickly and accurately by comparing the test results of the plurality of specific data transmission interfaces, and the time is saved for the subsequent batch production of the CPUs.

Drawings

Fig. 1 is a schematic structural diagram of a CPU test system based on the FPGA reconfiguration technology provided in the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a CPU test system based on FPGA reconfiguration technology according to the present invention.

The CPU test system based on the FPGA reconfiguration technology in this embodiment includes a test machine module, an FPGA module, a switch circuit module, and a CPU module to be tested; the test machine platform module is connected with the FPGA module; the FPGA module is connected with the switch circuit module; the switching circuit module is connected with the test machine platform module and the CPU module to be tested; and the CPU module to be tested is connected with the test machine platform module. Specifically, the test machine platform module comprises a test machine platform and an upper computer; the FPGA module comprises a reconfigurable FPGA, a JTAG connector, a first FLASH and a second FLASH; the CPU module to be tested comprises a domestic CPU, a level conversion chip module and a CPU functional interface module. The reconfigurable FPGA is an FPGA with a reconfigurable function, and the FPGA reconfigurable technology is specifically characterized in that all or part of logic resources of the FPGA chip are switched at high speed under certain logic drive for the FPGA chip, so that time division multiplexing of hardware is realized.

The upper computer is connected with a test machine table, and the test machine table is connected with the reconfigurable FPGA, the domestic CPU and the switch circuit module; the test machine is used for providing a power supply signal, a clock signal and a reset signal for the domestic CPU, providing a power supply, a clock, a control signal and a reconfiguration signal for the reconfigurable FPGA, providing a control signal for the switch circuit module and connecting the reconfigurable FPGA through the maintenance input and output interface. One end of the domestic CPU is connected with the level conversion chip module through various functional interface buses, and the other end of the domestic CPU is connected with the switch circuit module through the maintenance input and output interface and the JTAG interface; the CPU functional interface module is connected with the level conversion chip module through each functional interface bus. The CPU functional interface module includes but is not limited to USB, PCI, network port and serial port. The reconfigurable FPGA is connected with the switch circuit module through a maintenance input/output interface/JTAG interface; the JTAG connector is connected with the reconfigurable FPGA through a JTAG interface; the first FLASH is connected with the reconfigurable FPGA through a parallel port; the second FLASH is connected with the reconfigurable FPGA through an SPI bus; the JTAG connector is used for programming initial function logic to the reconfigurable FPGA; the first FLASH is used for storing a peripheral function interface test program of the domestic CPU, and the peripheral function interface test program in the first FLASH is called through the switch circuit module when the domestic CPU is tested.

The second FLASH is used for storing a plurality of functional logics of the reconfigurable FPGA, and the testing machine selects the logic which needs to be loaded into the reconfigurable FPGA from the second FLASH according to the reconfiguration signal. The corresponding relation when the upper computer carries out reconfiguration configuration on the reconfigurable FPGA is as follows: the upper computer gives a 00 signal, and the reconfigurable FPGA loads a logic 1 in the second FLASH; the upper computer gives a 01 signal, and the reconfigurable FPGA loads a logic 2 in the second FLASH; in the initial state, the signal is in the high impedance state.

Based on the CPU test system, the embodiment also discloses a CPU test method based on the FPGA reconfiguration technology, which specifically includes the following steps:

and S101, taking the domestic CPU as a chip to be tested and putting the chip into a position to be tested.

And S102, starting the test machine by the upper computer, realizing the power-on operation of the test machine on the CPU module and the FPGA module to be tested, and giving out a clock and a reset signal.

And S103, performing initial logic programming on the reconfigurable FPGA through the JTAG connector to enable the reconfigurable FPGA to have basic functions and prepare for subsequently reconfiguring the reconfigurable FPGA.

And step S104, the upper computer controls the test machine to send reconfiguration signals to the reconfigurable FPGA, and selects the corresponding IP core in the second FLASH to load into the reconfigurable FPGA, so as to realize the required interface data transmission function.

And S105, the test machine outputs a control signal to the switch circuit module, the switch circuit module calls a peripheral function interface test program of the domestic CPU prestored in the first FLASH, sends the peripheral function interface test program to the domestic CPU through the maintenance input/output interface, and starts the test through the upper computer.

And S106, after the upper computer starts the test, the test result is output to the upper computer sequentially through the switch circuit module, the reconfigurable FPGA and the test machine, the upper computer judges whether the test result passes or not, if the test result passes, the passing prompt is displayed, and if the test result does not pass, the upper computer outputs a detailed test result.

Step S107, controlled by the upper computer, a reconfiguration signal is given by a test machine, an IP core is loaded from a second FLASH under the condition of no power failure, and the logic function of the reconfigurable FPGA is reconfigured, so that another data transmission function interface required by the domestic CPU (Central processing Unit) is reconfigured to form a new JTAG interface, a peripheral function interface test program in the first FLASH is transmitted into the domestic CPU through the new JTAG interface, the test is started through the upper computer, and a test result is displayed back to the upper computer through a JTAG signal;

and S108, comparing the test results obtained in the S106 and the S107 by the upper computer, namely the test result of the domestic CPU. The design problem of the domestic CPU can be found more quickly and better through the compared test result.

According to the technical scheme, the FPGA reconfiguration technology is adopted, the upper computer outputs the FPGA reconfiguration instruction, and the limited resources of the reconfigurable FPGA are reconfigured out of a plurality of specific data transmission interfaces of the domestic CPU, namely JTAG interfaces and maintenance serial ports through the test machine, so that the problems of newly designed CPUs are positioned more quickly and accurately by comparing the test results of the plurality of specific data transmission interfaces, and the time is saved for the subsequent batch production of the CPUs. The invention has the following specific advantages: the test data transmission function interfaces required by various CPUs to be tested are realized by using fewer resources of the FPGA; the reconfiguration signal can send a reconfiguration instruction to the FPGA only by simple operation of an upper computer, and the realization is simple; the problem of newly designed CPU can be more effectively and quickly positioned by the FPGA reconstruction technology, so that the time is saved for the subsequent CPU batch production; before the system starts the test work, the programming of basic function logic is carried out on the FPGA, and the effective proceeding of the subsequent FPGA reconstruction work is ensured.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.

Claims (2)

1. A CPU test system based on FPGA reconstruction technology is characterized by comprising a test machine platform module, an FPGA module, a switch circuit module and a CPU module to be tested; the test machine platform module is connected with the FPGA module; the FPGA module is connected with the switch circuit module; the switching circuit module is connected with the test machine platform module and the CPU module to be tested; the CPU module to be tested is connected with the test machine platform module; the test machine platform module comprises a test machine platform and an upper computer; the FPGA module comprises a reconfigurable FPGA, a JTAG connector, a first FLASH and a second FLASH; the CPU module to be tested comprises a domestic CPU, a level conversion chip module and a CPU functional interface module; the upper computer is connected with a test machine, and the test machine is connected with the reconfigurable FPGA, the domestic CPU and the switch circuit module; the test machine is used for providing a power supply signal, a clock signal and a reset signal for the domestic CPU, providing a power supply, a clock, a control signal and a reconfiguration signal for the reconfigurable FPGA, providing a control signal for the switch circuit module and connecting the reconfigurable FPGA through a maintenance input and output interface; one end of the domestic CPU is connected with the level conversion chip module, and the other end of the domestic CPU is connected with the switch circuit module through the maintenance input/output interface and the JTAG interface; the CPU functional interface module is connected with the level conversion chip module; the reconfigurable FPGA is connected with the switch circuit module through a maintenance input/output interface/JTAG interface; the JTAG connector is connected with the reconfigurable FPGA through a JTAG interface; the first FLASH is connected with the reconfigurable FPGA through a parallel port; the second FLASH is connected with the reconfigurable FPGA through an SPI bus; the JTAG connector is used for programming initial function logic to the reconfigurable FPGA; the first FLASH is used for storing a peripheral function interface test program of the domestic CPU, and the peripheral function interface test program in the first FLASH is called through the switch circuit module when the domestic CPU is tested; the second FLASH is used for storing a plurality of functional logics of the reconfigurable FPGA, and the testing machine selects the logic which needs to be loaded into the reconfigurable FPGA from the second FLASH according to the reconfiguration signal.

2. A CPU test method based on FPGA reconstruction technology is characterized by comprising the following steps:

s101, a domestic CPU is used as a chip to be tested and is placed in a position to be tested;

step S102, starting a test machine by an upper computer, realizing the power-on operation of the test machine on a CPU module and an FPGA module to be tested, and giving out a clock and a reset signal;

step S103, performing initial logic programming on the reconfigurable FPGA through the JTAG connector;

step S104, the upper computer controls the test machine to send reconfiguration signals to the reconfigurable FPGA, and corresponding logic in the second FLASH is selected and loaded into the reconfigurable FPGA;

step S105, the test machine outputs a control signal to the switch circuit module, the switch circuit module calls a peripheral function interface test program of the domestic CPU pre-stored in the first FLASH, sends the peripheral function interface test program to the domestic CPU through the maintenance input/output interface, and starts a test through the upper computer;

step S106, after the upper computer starts the test, the test result is output to the upper computer through the switch circuit module, the reconfigurable FPGA and the test machine table in sequence, the upper computer judges whether the test result passes or not, if the test result passes, the passing prompt is displayed, and if the test result does not pass, the upper computer outputs a detailed test result;

step S107, controlled by the upper computer, a reconfiguration signal is given by a test machine, logic is loaded from the second FLASH under the condition of no power failure, and the logic function of the reconfigurable FPGA is reconfigured, so that another data transmission function interface required by the domestic CPU (Central processing Unit) is reconfigured to form a new JTAG interface, a peripheral function interface test program in the first FLASH is transmitted into the domestic CPU through the new JTAG interface, the test is started through the upper computer, and a test result is displayed back to the upper computer through a JTAG signal;

and S108, comparing the test results obtained in the S106 and the S107 by the upper computer, namely the test result of the domestic CPU.

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