CN112563140B - 一种碳化硅mosfet器件jfet区自对准掺杂工艺 - Google Patents
一种碳化硅mosfet器件jfet区自对准掺杂工艺 Download PDFInfo
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Abstract
本发明公开了一种碳化硅MOSFET器件JFET区自对准掺杂工艺,采用自对准的方法实现注入掺杂,对具体的自对准加工工艺,又细分为两种实现路线,一种是通过表面平整化的工艺方案,另一种是设计合适的JFET区宽度和多晶硅掩膜厚度比例,从而直接通过全片刻蚀工艺实现JFET区和p阱区的自对准。本发明能够在有效降低JFET区域电阻的同时,避免JFET区未注入完整,或者单边沟道被注入导致性能差异的风险。
Description
技术领域
本发明涉及半导体器件领域,主要涉及一种碳化硅MOSFET器件JFET区自对准掺杂工艺。
背景技术
碳化硅材料禁带宽度大、击穿电场高、饱和漂移速度和热导率大,这些材料优越性能使其成为制作高功率、高频、耐高温、抗辐射器件的理想材料。碳化硅MOSFET器件具有击穿电压高、电流密度大、驱动电路与硅IGBT近似的一系列优点,因此发展前景非常广泛。
碳化硅MOSFET器件的典型参数性能指标包括阻断电压、工作电流、阈值电压和导通电阻等。其中导通电阻由衬底电阻、漂移层电阻、JFET区电阻、沟道电阻和接触电阻等部分组成。随着器件性能需求不断提升,器件的元胞尺寸不断缩小,于是JFET区尺寸随之减小,而串联在器件导通电路中的JFET区电阻将不断上升。于是,对JFET区掺杂以获得较小的JFET区电阻成为可行而有效的方案。常用的JFET区掺杂方案是对整个MOSFET有源区进行整体掺杂,但是这种方案对器件其他区域进行了不必要的注入工艺,带来了额外的损伤。所以,在有可能的情况下,希望实现只对JFET区进行掺杂。
发明内容
本发明的目的在于提供一种碳化硅MOSFET器件JFET区自对准掺杂工艺,通过自对准的工艺方法实现器件JFET区域的掺杂,从而在降低JFET区电阻的同时不引入其他寄生效应。
实现本发明目的的技术解决方案为:一种碳化硅MOSFET器件JFET区自对准掺杂工艺,包括如下步骤:
S1:在碳化硅外延片表面生长淀积掩膜介质;
S2:将JFET区域表面的掩膜介质去除;
S3:对碳化硅表面JFET区域进行n型离子注入;
S4:在整个碳化硅圆片表面淀积多晶硅掩膜介质;
S5:采用表面平整化工艺,抛光去除圆片表面除JFET区域以外的多晶硅掩膜介质;
或者,对圆片表面的多晶硅层进行全片整体刻蚀,直至刻蚀到SiO2掩膜介质表面,而JFET区域有多晶硅介质留存;
S6:通过腐蚀工艺,去除之前的掩膜介质,对于器件的终端区域,通过光刻工艺,用光刻胶作掩膜保留部分掩膜介质;
S7:对碳化硅表面进行p型的p阱离子注入;
S8:通过自对准的方法,即对全片覆盖SiO2介质后再整体刻除,从而保留多晶硅介质侧壁的部分SiO2介质;或者直接对多晶硅介质进行自氧化生长工艺;
S9:对碳化硅表面进行n+型的离子注入,从而在p阱区域自对准地形成沟道;
S10:去除所有掩膜介质,完成整套自对准工艺,SiC圆片继续进行后续工艺。
与现有技术相比,本发明的显著优点为:本发明通过对碳化硅MOSFET器件的JFET区注入工艺采用自对准注入的方案,并将该方案整合进原有的碳化硅MOSFET沟道自对准注入流程中;该方案能够在有效降低JFET区域电阻的同时,避免JFET区未注入完整,或者单边沟道被注入导致性能差异的风险。同时方案的整合使得工艺难度得到一定程度降低。
附图说明
图1是本发明实施例中碳化硅表面淀积掩膜介质SiO2的示意图。
图2是本发明实施例中去除圆片JFET区域表面掩膜介质SiO2的示意图。
图3是本发明实施例中JFET区域进行n型离子注入的示意图。
图4是本发明实施例中完成JFET区注入后全片表面淀积覆盖多晶硅层的示意图。
图5是本发明实施例中表面平整化去除JFET区域以外多晶硅介质的示意图。
图6是本发明实施例中完成JFET区注入后全片表面淀积覆盖较厚多晶硅层,使得JFET区多晶硅层表面高于其他位置的示意图。
图7是本发明实施例中去除多余的掩膜介质SiO2的示意图。
图8是本发明实施例中离子注入形成p阱区域的示意图。
图9是本发明实施例中通过自对准工艺在多晶硅层侧壁形成SiO2薄层的示意图。
图10是本发明实施例中离子注入形成n+区域、p阱沟道的示意图。
图11是本发明实施例中去除所有掩膜介质,完成自对准工艺的示意图。
具体实施方式
碳化硅MOSFET器件的标准制备工艺中,常用多晶硅掩膜自氧化的方法形成自对准图形,从而注入形成p阱沟道,沟道宽度<1um,且通过精确控制自氧化的时间实现对沟道宽度的精确控制。于是,尝试同样通过自对准的方法可以实现JFET区的注入工艺。自对准方法还可以避免仅用光刻的方法制备JFET区注入掩膜存在的风险,特别是横向偏移使得部分JFET区未注入,或者单边沟道被注入导致性能差异等。
本发明提出一种碳化硅MOSFET器件JFET区自对准掺杂工艺,包括如下步骤:
S1:在碳化硅外延片表面生长淀积掩膜介质;
S2:通过光刻、刻蚀(或者腐蚀)工艺,将JFET区域表面的掩膜介质去除;
S3:对碳化硅表面JFET区域进行n型离子注入;
S4:在整个碳化硅圆片表面淀积多晶硅掩膜介质;
S5-1:采用表面平整化(CMP)等工艺方案,抛光去除圆片表面除JFET区域以外的多晶硅掩膜介质,这是整个JFET区域自对准掺杂工艺的核心过程;
S5-2:还有另一种工艺方案,当碳化硅MOSFET器件的JFET区域较窄,并且在S4步骤中选择淀积较厚的多晶硅掩膜介质时,可以使得JFET区域的多晶硅层高度高于圆片其他位置,此时可以选择对圆片表面的多晶硅层进行全片整体刻蚀,直至刻蚀到SiO2掩膜介质表面,而JFET区域有多晶硅介质留存;
S6:通过腐蚀(或者刻蚀)工艺,去除之前的掩膜介质,这里对于器件的终端区域,可以通过光刻工艺,用光刻胶作掩膜保留部分掩膜介质,以保证器件终端不受后续的p阱注入和n+注入的影响;
S7:对碳化硅表面进行p型的p阱离子注入;
S8:再通过自对准的方法,即对全片覆盖SiO2介质后再整体刻除,从而保留多晶硅介质侧壁的部分SiO2介质;或者直接对多晶硅介质进行自氧化生长工艺;
S9:对碳化硅表面进行n+型的离子注入,从而在p阱区域自对准地形成沟道;
S10:去除所有掩膜介质,完成整套自对准工艺,SiC圆片继续进行后续工艺。
进一步的,所述步骤S1中,掩膜介质推荐使用SiO2,也可以采用SiN、变组分SixN1-x、SiON等其他介质,掩膜介质厚度在0.5um至5um,原因是需要用作JFET以外区域注入时的掩膜,同时兼顾工艺成本和难度。
进一步的,所述步骤S2中,去除JFET区域介质的方法可以是氢氟酸(或者BOE)湿法腐蚀,此时需根据介质厚度留足相同宽度的侧蚀余量;或者采用干法刻蚀工艺,此时可以剩余部分介质,厚度小于500埃,避免损伤碳化硅表面,同时对JFET注入能量少量提升,保证注入深度。
进一步的,所述步骤S3中,通过掩膜介质形成对JFET区域的单独注入,此处也可以选择无掩膜介质整片注入,或者注入完成后直接去除掩膜介质,即不采用自对准工艺,如此也能达到掺杂JFET区域的目的,但是会引入额外的风险。
进一步的,所述步骤S4中,淀积的多晶硅层厚度在0.5um至5um,目的是足够满足后续p阱注入时的掩膜需求。
进一步的,所述步骤S5-1中,对表面平整化的片内均匀性有要求,至少正负0.5um以内,要求JFET区域以外的多晶硅层去除干净,可以额外减去部分SiO2掩膜,但是要保证剩余的(多晶硅)厚度满足注入掩膜要求。
进一步的,所述步骤S5-2中,此方案中采用的多晶硅层厚度较厚,大于SiO2掩膜介质的厚度;该方法更适合窄JFET区域的情形,指宽度小于2um;采用全片刻蚀多晶硅的方法,还需要较高的多晶硅和SiO2刻蚀比,大于3:1,从而以一定比例的过刻保证非JFET区无多晶硅残留;最后此方案还需要JFET区域的多晶硅层在过刻后仍有剩余。
进一步的,所述步骤S6中,去除剩余SiO2的过程中,需要不损伤多晶硅层,不损伤碳化硅表面。对于器件终端结构的制备,本发明在后续的p+层注入过程中一并实现,所以此处默认对终端区域保留掩膜介质不注入离子。
进一步的,所述步骤S7-S9中,此处描述的是碳化硅p阱、沟道、n+区注入形成的标准流程,本发明主要创新在于将JFET区注入过程放在这一过程之前,从而实现JFET区、p阱、n+区三者的自对准。实际方案流程中相当于用p阱对准JFET区,再用n+区对准p阱。
下面结合附图,对本发明的技术方案做进一步的阐述。
实施例
本发明公开了一种碳化硅MOSFET器件JFET区自对准掺杂工艺方法,包括以下步骤:
S1:在碳化硅外延片表面生长淀积掩膜介质,掩膜介质使用SiO2,如图1所示;
S2:将JFET区域表面的掩膜介质去除,如图2所示;
S3:对碳化硅表面JFET区域进行n型离子注入,如图3所示;
S4:在整个碳化硅圆片表面淀积多晶硅掩膜介质,如图4所示;
S5-1:采用表面平整化工艺方案,抛光去除圆片表面除JFET区域以外的多晶硅掩膜介质,如图5所示,这是整个JFET区域自对准掺杂工艺的核心过程;
S5-2:还有另一种工艺方案,当碳化硅MOSFET器件的JFET区域较窄,并且在S4步骤中选择淀积较厚的多晶硅掩膜介质时,可以使得JFET区域的多晶硅层高度高于圆片其他位置,如图6所示,此时可以选择对圆片表面的多晶硅层进行全片整体刻蚀,直至刻蚀到SiO2掩膜介质表面,而JFET区域有多晶硅介质留存;
S6:通过腐蚀工艺,去除之前的掩膜介质SiO2,如图7所示,这里对于器件的终端区域,可以通过光刻工艺,用光刻胶作掩膜保留部分掩膜介质,以保证器件终端不受后续的p阱注入和n+注入的影响;
S7:对碳化硅表面进行p型的p阱离子注入,如图8所示;
S8:再通过自对准的方法,即对全片覆盖SiO2介质后再整体刻除,从而保留多晶硅介质侧壁的部分SiO2介质,如图9所示;
S9:对碳化硅表面进行n+型的离子注入,从而在p阱区域自对准地形成沟道,如图10所示;
S10:去除所有掩膜介质,完成整套自对准工艺,如图11所示,SiC圆片继续进行后续工艺。
Claims (8)
1.一种碳化硅MOSFET器件JFET区自对准掺杂工艺,其特征在于,包括如下步骤:
S1:在碳化硅外延片表面生长淀积掩膜介质;
S2:将JFET区域表面的掩膜介质去除;
S3:对碳化硅表面JFET区域进行n型离子注入;
S4:在整个碳化硅圆片表面淀积多晶硅掩膜介质;
S5:采用表面平整化工艺,抛光去除圆片表面除JFET区域以外的多晶硅掩膜介质;
或者,对圆片表面的多晶硅层进行全片整体刻蚀,直至刻蚀到掩膜介质表面,而JFET区域有多晶硅介质留存;
S6:通过腐蚀工艺,去除之前的掩膜介质,对于器件的终端区域,通过光刻工艺,用光刻胶作掩膜保留部分掩膜介质;
S7:对碳化硅表面进行p型的p阱离子注入;
S8:通过自对准的方法,即对全片覆盖SiO2介质后再整体刻除,从而保留多晶硅介质侧壁的部分SiO2介质;或者直接对多晶硅介质进行自氧化生长工艺;
S9:对碳化硅表面进行n+型的离子注入,从而在p阱区域自对准地形成沟道;
S10:去除所有掩膜介质,完成整套自对准工艺,SiC圆片继续进行后续工艺。
2.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S1中,掩膜介质为SiO2、SiN、变组分SixN1-x、SiON,掩膜介质厚度在0.5um至5um。
3.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S2中,去除JFET区域介质的方法为氢氟酸湿法腐蚀或者BOE湿法腐蚀,根据介质厚度留足相同宽度的侧蚀余量。
4.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S2中,采用干法刻蚀工艺,剩余部分介质,厚度小于500埃。
5.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S3中,通过掩膜介质形成对JFET区域的单独注入。
6.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S4中,淀积的多晶硅层厚度在0.5um至5um。
7.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S5中,抛光去除圆片表面除JFET区域以外的多晶硅掩膜介质时,对表面平整化的片内均匀性有要求,至少正负0.5um以内。
8.根据权利要求1所述的JFET区自对准掺杂工艺,其特征在于:所述S5中,对圆片表面的多晶硅层进行全片整体刻蚀,直至刻蚀到SiO2掩膜介质表面,而JFET区域有多晶硅介质留存,其中采用的多晶硅层厚度大于SiO2掩膜介质的厚度;JFET区域宽度小于2um;多晶硅和SiO2刻蚀比大于3:1。
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