CN112542193A - FLASH memory of SPI interface for reading data at high speed - Google Patents

FLASH memory of SPI interface for reading data at high speed Download PDF

Info

Publication number
CN112542193A
CN112542193A CN202011604951.1A CN202011604951A CN112542193A CN 112542193 A CN112542193 A CN 112542193A CN 202011604951 A CN202011604951 A CN 202011604951A CN 112542193 A CN112542193 A CN 112542193A
Authority
CN
China
Prior art keywords
output
trigger
data
unit
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011604951.1A
Other languages
Chinese (zh)
Other versions
CN112542193B (en
Inventor
刘佳庆
黎永健
蒋双泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XTX Technology Shenzhen Ltd
Original Assignee
XTX Technology Shenzhen Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XTX Technology Shenzhen Ltd filed Critical XTX Technology Shenzhen Ltd
Priority to CN202011604951.1A priority Critical patent/CN112542193B/en
Publication of CN112542193A publication Critical patent/CN112542193A/en
Application granted granted Critical
Publication of CN112542193B publication Critical patent/CN112542193B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Information Transfer Systems (AREA)

Abstract

The invention discloses a FLASH memory of SPI interface for reading data at high speed, which samples the input data signal respectively at the rising edge and the falling edge of the transmission clock signal, can realize the doubling of the transmission rate of the input data without changing the frequency of the external clock signal, and simultaneously accepts 4-line input data, the combination of the two can reach 8 times of the SCK frequency, and simultaneously, the data rate is reduced in the chip, the power consumption is reduced, and the subsequent processing is also convenient; the two paths of data are synchronized through the output rising edge synchronization unit and the output falling edge synchronization unit, the output selection unit selects and outputs the data output of the output falling edge synchronization unit when the transmission clock signal SCK is at a high level, the data output of the output rising edge synchronization unit is selected when the transmission clock signal SCK is at a low level, and the double rate of the data output is realized under the condition that the clock frequency is not changed.

Description

FLASH memory of SPI interface for reading data at high speed
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a FLASH memory of an SPI (serial peripheral interface) for reading data at a high speed.
Background
FLASH generally adopts an SPI protocol instruction, has a relatively high requirement on the speed of a FLASH read instruction, a circuit in a traditional mode adopts multi-line transmission to meet the requirement of high speed, some designs adopt a dual-edge output DTR mode to output data in order to improve the speed, but many designs cannot perfectly combine the multi-line transmission and the dual-edge output DTR mode, so that the finally realized read data speed is not as fast as imaginable: only by adopting the multi-line transmission, although the transmission rate can be doubled or quadrupled, the transmission is not carried out by utilizing the falling edge of the transmission clock, and the speed is not optimal; the mode using dual edge output does not use multiline transmission and is not optimal.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a FLASH memory of an SPI interface for reading data at high speed, aiming at solving the problem that the reading instruction speed cannot meet the requirement because the traditional FLASH cannot well combine the DTR modes of multi-line transmission and double-edge output.
The technical scheme of the invention is as follows: a FLASH memory of an SPI interface for reading data at high speed, comprising:
the SPI interface module is used for receiving an external transmission clock signal SCK and an input data signal and outputting data of a storage unit in the FLASH memory;
the input rising edge synchronization unit samples the input data signal at the rising edge of the transmission clock signal SCK to obtain a first group of data;
the input falling edge synchronization unit samples the input data signal at the falling edge of the transmission clock signal SCK to obtain a second group of data;
a combining unit which receives the first set of data and the second set of data and combines the first set of data and the second set of data;
the synchronization unit synchronizes the combined first group of data and the second group of data to obtain a synchronization result, and transmits the synchronization result to the storage unit;
the storage unit outputs corresponding data according to the synchronization result transmitted by the synchronization unit;
the output rising edge synchronization unit synchronizes the data output by the storage unit at the rising edge of the transmission clock signal SCK and simultaneously connects the high 4-bit data of the data output by the synchronized storage unit with the output selection unit; and the low 4-bit data of the data output by the storage unit are connected with the output falling edge synchronization unit;
the output falling edge synchronization unit is used for receiving the lower 4-bit data of the data output by the storage unit transmitted by the output rising edge synchronization unit, synchronizing the lower 4-bit data at the falling edge of the transmission clock signal SCK and simultaneously connecting the synchronized lower 4-bit data to the output selection unit;
and the output selection unit is used for selecting one of the synchronized high 4-bit data and low 4-bit data according to the transmission clock signal SCK and outputting the selected one to the SPI interface module, and finally outputting the selected one through the SPI interface module.
The FLASH memory of the SPI interface for reading data at high speed, wherein the synchronization unit stores the synchronization result into the storage unit at a rising edge of the external transmission clock signal SCK; or the synchronization result is stored in the storage unit at the falling edge of the external transmission clock signal SCK.
The FLASH memory of the SPI interface for reading data at high speed is characterized in that the input rising edge synchronization unit comprises a first D trigger, a second D trigger, a third D trigger and a fourth D trigger, the D end of the first D trigger is connected with the HOLD end of the SPI interface module, the Q end of the first D trigger is connected with the combination unit, and the CK end of the first D trigger is connected with the transmission clock signal SCK; the D end of the second D trigger is connected with the WP end of the SPI interface module, the Q end of the second D trigger is connected with the combination unit, and the CK end of the second D trigger is connected with the SCK; the D end of the third D trigger is connected with the SO end of the SPI interface module, the Q end of the third D trigger is connected with the combination unit, and the CK end of the third D trigger is connected with the SCK; the D end of the fourth D trigger is connected with the SI end of the SPI interface module, the Q end of the fourth D trigger is connected with the combination unit, and the CK end of the fourth D trigger is connected with the SCK.
The FLASH memory of the SPI interface for reading data at high speed is characterized in that the input falling edge synchronization unit comprises a fifth D trigger, a sixth D trigger, a seventh D trigger and an eighth D trigger, the D end of the fifth D trigger is connected with the HOLD end of the SPI interface module, the Q end of the fifth D trigger is connected with the combination unit, and the CK end of the fifth D trigger is connected with a transmission clock signal SCK through a phase inverter; the D end of the sixth D trigger is connected with the WP end of the SPI interface module, the Q end of the sixth D trigger is connected with the combination unit, and the CK end of the sixth D trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the seventh D trigger is connected with the SO end of the SPI interface module, the Q end of the seventh D trigger is connected with the combination unit, and the CK end of the seventh D trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the eighth D trigger is connected with the SI end of the SPI interface module, the Q end of the eighth D trigger is connected with the combination unit, and the CK end of the eighth D trigger is connected with the transmission clock signal SCK through the phase inverter.
The FLASH memory of the SPI interface for reading data at high speed is characterized in that the combination unit adopts a buffer.
The FLASH memory of the SPI interface for reading data at high speed is characterized in that the synchronization unit adopts a ninth D trigger, the D end of the ninth D trigger is connected with the combination unit, the CK end of the ninth D trigger is connected with the transmission clock signal SCK, and the Q end of the ninth D trigger is connected with the storage unit; and the D end of the synchronization unit is connected with the Q ends of the input rising edge synchronization unit and the input falling edge synchronization unit through a buffer of the combination unit, and the Q end of the synchronization unit outputs the synchronization result to the storage unit.
The FLASH memory of the SPI interface for reading data at a high speed, wherein the output rising edge synchronization unit includes a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop and a seventeenth D flip-flop, a D end of the tenth D flip-flop is connected to the data output end of the storage unit, a Q end of the tenth D flip-flop is connected to the output selection unit, and a CK end of the tenth D flip-flop is connected to the transmission clock signal SCK; the D end of the eleventh D trigger is connected with the data output end of the storage unit, the Q end of the eleventh D trigger is connected with the output selection unit, and the CK end of the eleventh D trigger is connected with the transmission clock signal SCK; the D end of the twelfth D trigger is connected with the data output end of the storage unit, the Q end of the twelfth D trigger is connected with the output selection unit, and the CK end of the twelfth D trigger is connected with the transmission clock signal SCK; the D end of the thirteenth D trigger is connected with the data output end of the storage unit, the Q end of the thirteenth D trigger is connected with the output selection unit, and the CK end of the thirteenth D trigger is connected with the transmission clock signal SCK; the D end of the fourteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fourteenth D trigger is connected with the output falling edge synchronization unit; the D end of the fifteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fifteenth D trigger is connected with the output falling edge synchronization unit; the D end of the sixteenth D trigger is connected with the data output end of the storage unit, and the Q end of the sixteenth D trigger is connected with the output falling edge synchronization unit; the D end of the seventeenth D trigger is connected with the data output end of the storage unit, and the Q end of the seventeenth D trigger is connected with the output falling edge synchronization unit.
The FLASH memory of the SPI interface for reading data at high speed is characterized in that the output falling edge synchronization unit comprises an eighteenth D trigger, a nineteenth D trigger, a twentieth D trigger and a twenty-first D trigger, the D end of the eighteenth D trigger is connected with the output rising edge synchronization unit, the Q end of the eighteenth D trigger is connected with the output selection unit, and the CK end of the eighteenth D trigger is connected with a transmission clock signal SCK through a phase inverter; the D end of the nineteenth D trigger is connected with the output rising edge synchronization unit, the Q end of the nineteenth D trigger is connected with the output selection unit, and the CK end of the nineteenth D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the twentieth trigger is connected with the output rising edge synchronization unit, the Q end of the twentieth trigger is connected with the output selection unit, and the CK end of the twentieth trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the twenty-first D trigger is connected with the output rising edge synchronization unit, the Q end of the twenty-first D trigger is connected with the output selection unit, and the CK end of the twenty-first D trigger is connected with the transmission clock signal SCK through the phase inverter.
The FLASH memory of the SPI interface for reading data at high speed, wherein when the external transmission clock signal SCK is at high level, the output selection unit selects the data transmitted by the output falling edge synchronization unit to output; and when the external transmission clock signal SCK is at a low level, the output selection unit selects the data transmitted by the output rising edge synchronization unit to output.
The FLASH memory of the SPI interface for reading data at high speed is characterized in that the output selection unit comprises a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer, wherein the input end A of the first multiplexer is connected with the output rising edge synchronization unit, the input end B of the first multiplexer is connected with the output falling edge synchronization unit, the SEL end of the first multiplexer is connected with the transmission clock signal SCK, and the output end of the first multiplexer is connected with the HOLD end of the SPI interface module; the input end A of the second multiplexer is connected with the output rising edge synchronization unit, the input end B of the second multiplexer is connected with the output falling edge synchronization unit, the SEL end of the second multiplexer is connected with the transmission clock signal SCK, and the output end of the second multiplexer is connected with the WP end of the SPI interface module; the input end A of the third multi-path selector is connected with the output rising edge synchronization unit, the input end B of the third multi-path selector is connected with the output falling edge synchronization unit, the SEL end of the third multi-path selector is connected with the transmission clock signal SCK, and the output end of the third multi-path selector is connected with the SO end of the SPI interface module; the input end A of the fourth multiplexer is connected with the output rising edge synchronization unit, the input end B of the fourth multiplexer is connected with the output falling edge synchronization unit, the SEL end of the fourth multiplexer is connected with the transmission clock signal SCK, and the output end of the fourth multiplexer is connected with the SI end of the SPI interface module.
The invention has the beneficial effects that: the invention provides a FLASH memory of SPI interface for reading data at high speed, which samples the input data signal respectively at the rising edge and the falling edge of the external transmission clock signal SCK through an input rising edge synchronization unit, an input falling edge synchronization unit, a combination unit, a synchronization unit and a bidirectional SPI interface module, and can realize the doubling of the transmission rate of the input data without changing the frequency of the external clock signal; meanwhile, the data input by 4 lines is received, the combination of the data and the input speed can reach 8 times of the SCK frequency, and meanwhile, the data speed is reduced in the chip, so that the subsequent processing is facilitated while the power consumption is reduced; according to the technical scheme, two paths of data are synchronized through the D trigger of the output rising edge synchronization unit and the D trigger of the output falling edge synchronization unit, when the transmission clock signal SCK is at a high level, the multiplexer MUX of the output selection unit selects and outputs data at the Q end of the D trigger of the output falling edge synchronization unit, when the transmission clock signal SCK is at a low level, the data output at the Q end of the D trigger of the output rising edge synchronization unit is selected and output, and under the condition that the clock frequency is not changed, the double rate of data output is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a FLASH memory of an SPI interface for reading data at high speed in the present invention.
FIG. 2 is a schematic diagram of the input rising edge synchronization unit, the input falling edge synchronization unit, the combination unit, the synchronization unit, and the storage unit according to the present invention.
FIG. 3 is a schematic diagram of the structure of a memory unit, an output rising edge synchronization unit, an output falling edge synchronization unit, and an output selection unit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1 to 3, a FLASH memory of an SPI interface (generally referred to as a serial peripheral interface) for reading data at a high speed includes:
the SPI interface module 1 is used for receiving an external transmission clock signal SCK and an input data signal and outputting data of the storage unit 6 in the FLASH memory;
an input rising edge synchronization unit 2, which samples the input data signal at the rising edge of the transmission clock signal SCK to obtain a first group of data;
an input falling edge synchronization unit 3 for sampling the input data signal at the falling edge of the transmission clock signal SCK to obtain a second group of data;
a combining unit 4 for receiving the first set of data and the second set of data and combining the first set of data and the second set of data;
the synchronization unit 5 synchronizes the combined first group of data and the second group of data to obtain a synchronization result, and transmits the synchronization result to the storage unit 6;
the storage unit 6 outputs corresponding data according to the synchronization result transmitted by the synchronization unit 5;
an output rising edge synchronizing unit 7 for synchronizing the data output from the memory unit 6 at the rising edge of the transmission clock signal SCK and simultaneously connecting the high 4-bit data of the data output from the synchronized memory unit 6 to the output selection unit 9; and a lower 4-bit data connection output falling edge synchronization unit 8 for connecting the data output by the storage unit 6;
the output falling edge synchronization unit 8 is used for receiving the lower 4-bit data of the data output by the storage unit 6 transmitted by the output rising edge synchronization unit 7, synchronizing the lower 4-bit data at the falling edge of the transmission clock signal SCK, and simultaneously connecting the synchronized lower 4-bit data with the output selection unit 9;
and the output selection unit 9 is configured to select one of the synchronized high 4-bit data and low 4-bit data according to the transmission clock signal SCK, output the selected one to the SPI interface module 1, and finally output the selected one through the SPI interface module 1.
In some embodiments, the synchronization unit 5 may store the synchronization result into the storage unit 6 at a rising edge of the external transmission clock signal SCK, or store the synchronization result into the storage unit 6 at a falling edge of the external transmission clock signal SCK.
In some embodiments, the input rising edge synchronization unit 2 includes a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, a D end of the first D flip-flop is connected to a HOLD end of the SPI interface module 1, a Q end of the first D flip-flop is connected to the combination unit 4, and a CK end of the first D flip-flop is connected to the transmission clock signal SCK; the D end of the second D trigger is connected with the WP end of the SPI interface module 1, the Q end of the second D trigger is connected with the combination unit 4, and the CK end of the second D trigger is connected with the transmission clock signal SCK; the D end of the third D trigger is connected with the SO end of the SPI interface module 1, the Q end of the third D trigger is connected with the combination unit 4, and the CK end of the third D trigger is connected with the transmission clock signal SCK; the end D of the fourth D trigger is connected with the end SI of the SPI interface module 1, the end Q of the fourth D trigger is connected with the combination unit 4, and the end CK of the fourth D trigger is connected with the transmission clock signal SCK.
In some embodiments, the input falling edge synchronization unit 3 includes a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and an eighth D flip-flop, a D end of the fifth D flip-flop is connected to the HOLD end of the SPI interface module 1, a Q end of the fifth D flip-flop is connected to the combination unit 4, and a CK end of the fifth D flip-flop is connected to the transmission clock signal SCK through an inverter; the D end of the sixth D trigger is connected with the WP end of the SPI interface module 1, the Q end of the sixth D trigger is connected with the combination unit 4, and the CK end of the sixth D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the seventh D trigger is connected with the SO end of the SPI interface module 1, the Q end of the seventh D trigger is connected with the combination unit 4, and the CK end of the seventh D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the eighth D trigger is connected with the SI end of the SPI interface module 1, the Q end of the eighth D trigger is connected with the combination unit 4, and the CK end of the eighth D trigger is connected with the transmission clock signal SCK through the phase inverter.
In some embodiments, the combining unit 4 employs a buffer.
In some embodiments, the synchronizing unit 5 adopts a ninth D flip-flop, a D end of the ninth D flip-flop is connected to the combining unit 4, a CK end of the ninth D flip-flop is connected to the transmission clock signal SCK, and a Q end of the ninth D flip-flop is connected to the storage unit 6; the D terminal of the synchronization unit 5 is connected to the Q terminals of the input rising edge synchronization unit 2 and the input falling edge synchronization unit 3 through the buffer of the combination unit 4, and the Q terminal of the synchronization unit 5 outputs the synchronization result to the storage unit 6.
In the technical scheme, the input data signals are respectively sampled by the rising edge and the falling edge of an external transmission clock signal SCK through the input rising edge synchronization unit 2, the input falling edge synchronization unit 3, the combination unit 4, the synchronization unit 5 and the bidirectional SPI interface module 1, and 8 times of data input rate under a lower-frequency clock is realized.
In this technical solution, the D flip-flop of the input rising edge synchronization unit 2 samples data at the rising edge of the transmission clock signal SCK, and the D flip-flop of the input falling edge synchronization unit 3 samples data at the falling edge of the transmission clock signal SCK, so that both sets of input data are synchronously output to the storage unit 6 at the rising edge of the external transmission clock signal SCK; therefore, the doubling of the transmission rate of the input data can be realized without changing the frequency of the external clock signal; and simultaneously, the data input by 4 lines is received, the combination of the data and the input speed can reach 8 times of the SCK frequency, and meanwhile, the data speed is reduced in the chip, so that the subsequent processing is facilitated while the power consumption is reduced.
In the technical scheme, the I/O interface of the serial interface flash memory is improved, so that double speed and external data can be adopted; other components of the bi-directional I/O serial output flash memory, transmission among the components, control implementation schemes, and connection schemes with the outside (such as high Vcc, ground GND, chip select CS #, W #, and HOLD #) can be the same as the prior art, and are not described herein again.
In some specific embodiments, the output rising edge synchronization unit 7 includes a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, and a seventeenth D flip-flop, a D terminal of the tenth D flip-flop is connected to the data output terminal of the storage unit 6, a Q terminal of the tenth D flip-flop is connected to the output selection unit 9, and a CK terminal of the tenth D flip-flop is connected to the transmission clock signal SCK; the D end of the eleventh D trigger is connected with the data output end of the storage unit 6, the Q end of the eleventh D trigger is connected with the output selection unit 9, and the CK end of the eleventh D trigger is connected with the transmission clock signal SCK; the D end of the twelfth D trigger is connected with the data output end of the storage unit 6, the Q end of the twelfth D trigger is connected with the output selection unit 9, and the CK end of the twelfth D trigger is connected with the transmission clock signal SCK; the D end of the thirteenth D trigger is connected with the data output end of the storage unit 6, the Q end of the thirteenth D trigger is connected with the output selection unit 9, and the CK end of the thirteenth D trigger is connected with the transmission clock signal SCK; the D end of the fourteenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the fourteenth D trigger is connected with the output falling edge synchronization unit 8; the D end of the fifteenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the fifteenth D trigger is connected with the output falling edge synchronization unit 8; the D end of the sixteenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the sixteenth D trigger is connected with the output falling edge synchronization unit 8; the end D of the seventeenth D flip-flop is connected with the data output end of the storage unit 6, and the end Q of the seventeenth D flip-flop is connected with the output falling edge synchronization unit 8.
In some specific embodiments, the output falling edge synchronization unit 8 includes an eighteenth D flip-flop, a nineteenth D flip-flop, a twentieth D flip-flop, and a twenty-first D flip-flop, a D terminal of the eighteenth D flip-flop is connected to the output rising edge synchronization unit 7, a Q terminal of the eighteenth D flip-flop is connected to the output selection unit 9, and a CK terminal of the eighteenth D flip-flop is connected to the transmission clock signal SCK through an inverter; the D end of the nineteenth D trigger is connected with the output rising edge synchronization unit 7, the Q end of the nineteenth D trigger is connected with the output selection unit 9, and the CK end of the nineteenth D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the twentieth trigger is connected with the output rising edge synchronization unit 7, the Q end of the twentieth trigger is connected with the output selection unit 9, and the CK end of the twentieth trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the twenty-first D flip-flop is connected with the output rising edge synchronization unit 7, the Q end of the twenty-first D flip-flop is connected with the output selection unit 9, and the CK end of the twenty-first D flip-flop is connected with the transmission clock signal SCK through the inverter.
In some embodiments, the output selection unit 9 includes a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer, an a input terminal of the first multiplexer is connected to the output rising edge synchronization unit 7, a B input terminal of the first multiplexer is connected to the output falling edge synchronization unit 8, an SEL terminal of the first multiplexer is connected to the transmission clock signal SCK, and an output terminal of the first multiplexer is connected to the HOLD terminal of the SPI interface module 1; the input end A of the second multiplexer is connected with the output rising edge synchronization unit 7, the input end B of the second multiplexer is connected with the output falling edge synchronization unit 8, the SEL end of the second multiplexer is connected with the transmission clock signal SCK, and the output end of the second multiplexer is connected with the WP end of the SPI interface module 1; the input end A of the third multiplexer is connected with the output rising edge synchronization unit 7, the input end B of the third multiplexer is connected with the output falling edge synchronization unit 8, the SEL end of the third multiplexer is connected with the transmission clock signal SCK, and the output end of the third multiplexer is connected with the SO end of the SPI interface module 1; the input end A of the fourth multiplexer is connected with the output rising edge synchronization unit 7, the input end B of the fourth multiplexer is connected with the output falling edge synchronization unit 8, the SEL end of the fourth multiplexer is connected with the transmission clock signal SCK, and the output end of the fourth multiplexer is connected with the SI end of the SPI interface module 1.
When the external transmission clock signal SCK is at a high level, the output selection unit 9 selects the data output from the Q-side of the D flip-flop Q of the output falling edge synchronization unit 8, and when the external transmission clock signal SCK is at a low level, the data output from the Q-side of the D flip-flop Q of the highest 4-bit D flip-flop Q of the output rising edge synchronization unit 7 is selected, and the output data is output through the SPI interface module 1.
In the technical scheme, the D flip-flop of the output rising edge synchronization unit 7 and the D flip-flop of the output falling edge synchronization unit 8 synchronize two paths of data; when the transmission clock signal SCK is at a high level, the multiplexer MUX of the output selection unit 9 selects the data output of the Q terminal of the D flip-flop of the output falling edge synchronization unit 8, and when the transmission clock signal SCK is at a low level, the multiplexer MUX selects the data output of the Q terminal of the D flip-flop of the output rising edge synchronization unit 7; double rate of data output is achieved without changing the clock frequency.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A FLASH memory of an SPI interface for reading data at high speed, comprising:
the SPI interface module is used for receiving an external transmission clock signal SCK and an input data signal and outputting data of a storage unit in the FLASH memory;
the input rising edge synchronization unit samples the input data signal at the rising edge of the transmission clock signal SCK to obtain a first group of data;
the input falling edge synchronization unit samples the input data signal at the falling edge of the transmission clock signal SCK to obtain a second group of data;
a combining unit which receives the first set of data and the second set of data and combines the first set of data and the second set of data;
the synchronization unit synchronizes the combined first group of data and the second group of data to obtain a synchronization result, and transmits the synchronization result to the storage unit;
the storage unit outputs corresponding data according to the synchronization result transmitted by the synchronization unit;
the output rising edge synchronization unit synchronizes the data output by the storage unit at the rising edge of the transmission clock signal SCK and simultaneously connects the high 4-bit data of the data output by the synchronized storage unit with the output selection unit; and the low 4-bit data of the data output by the storage unit are connected with the output falling edge synchronization unit;
the output falling edge synchronization unit is used for receiving the lower 4-bit data of the data output by the storage unit transmitted by the output rising edge synchronization unit, synchronizing the lower 4-bit data at the falling edge of the transmission clock signal SCK and simultaneously connecting the synchronized lower 4-bit data to the output selection unit;
and the output selection unit is used for selecting one of the synchronized high 4-bit data and low 4-bit data according to the transmission clock signal SCK and outputting the selected one to the SPI interface module, and finally outputting the selected one through the SPI interface module.
2. The FLASH memory of the SPI interface for reading data at a high speed according to claim 1, wherein said synchronization unit saves said synchronization result into said storage unit at a rising edge of said external transmission clock signal SCK; or the synchronization result is stored in the storage unit at the falling edge of the external transmission clock signal SCK.
3. The FLASH memory of the SPI interface for reading data at a high speed according to claim 1, wherein the input rising edge synchronization unit comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, wherein a D terminal of the first D flip-flop is connected to a HOLD terminal of the SPI interface module, a Q terminal of the first D flip-flop is connected to the combination unit, and a CK terminal of the first D flip-flop is connected to the transmission clock signal SCK; the D end of the second D trigger is connected with the WP end of the SPI interface module, the Q end of the second D trigger is connected with the combination unit, and the CK end of the second D trigger is connected with the SCK; the D end of the third D trigger is connected with the SO end of the SPI interface module, the Q end of the third D trigger is connected with the combination unit, and the CK end of the third D trigger is connected with the SCK; the D end of the fourth D trigger is connected with the SI end of the SPI interface module, the Q end of the fourth D trigger is connected with the combination unit, and the CK end of the fourth D trigger is connected with the SCK.
4. The FLASH memory of the SPI interface for reading data at a high speed according to claim 1, wherein the input falling edge synchronization unit comprises a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and an eighth D flip-flop, wherein a D terminal of the fifth D flip-flop is connected to a HOLD terminal of the SPI interface module, a Q terminal of the fifth D flip-flop is connected to the combination unit, and a CK terminal of the fifth D flip-flop is connected to the transmission clock signal SCK through an inverter; the D end of the sixth D trigger is connected with the WP end of the SPI interface module, the Q end of the sixth D trigger is connected with the combination unit, and the CK end of the sixth D trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the seventh D trigger is connected with the SO end of the SPI interface module, the Q end of the seventh D trigger is connected with the combination unit, and the CK end of the seventh D trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the eighth D trigger is connected with the SI end of the SPI interface module, the Q end of the eighth D trigger is connected with the combination unit, and the CK end of the eighth D trigger is connected with the transmission clock signal SCK through the phase inverter.
5. The SPI interface FLASH memory for high speed reading of data according to claim 1 wherein said combining unit employs a buffer.
6. The FLASH memory of SPI interface for high speed reading of data according to any of claims 1, 2, 5, characterized in that said synchronization unit employs a ninth D flip-flop, whose D terminal is connected to the combination unit, whose CK terminal is connected to the transmission clock signal SCK, whose Q terminal is connected to the storage unit; and the D end of the synchronization unit is connected with the Q ends of the input rising edge synchronization unit and the input falling edge synchronization unit through a buffer of the combination unit, and the Q end of the synchronization unit outputs the synchronization result to the storage unit.
7. The FLASH memory of the SPI interface for reading data at a high speed according to claim 1, wherein the output rising edge synchronization unit comprises a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, and a seventeenth D flip-flop, wherein a D terminal of the tenth D flip-flop is connected to the data output terminal of the storage unit, a Q terminal of the tenth D flip-flop is connected to the output selection unit, and a CK terminal of the tenth D flip-flop is connected to the transmission clock signal SCK; the D end of the eleventh D trigger is connected with the data output end of the storage unit, the Q end of the eleventh D trigger is connected with the output selection unit, and the CK end of the eleventh D trigger is connected with the transmission clock signal SCK; the D end of the twelfth D trigger is connected with the data output end of the storage unit, the Q end of the twelfth D trigger is connected with the output selection unit, and the CK end of the twelfth D trigger is connected with the transmission clock signal SCK; the D end of the thirteenth D trigger is connected with the data output end of the storage unit, the Q end of the thirteenth D trigger is connected with the output selection unit, and the CK end of the thirteenth D trigger is connected with the transmission clock signal SCK; the D end of the fourteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fourteenth D trigger is connected with the output falling edge synchronization unit; the D end of the fifteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fifteenth D trigger is connected with the output falling edge synchronization unit; the D end of the sixteenth D trigger is connected with the data output end of the storage unit, and the Q end of the sixteenth D trigger is connected with the output falling edge synchronization unit; the D end of the seventeenth D trigger is connected with the data output end of the storage unit, and the Q end of the seventeenth D trigger is connected with the output falling edge synchronization unit.
8. The FLASH memory of the SPI interface for reading data at a high speed according to claim 1, wherein the output falling edge synchronization unit comprises an eighteenth D flip-flop, a nineteenth D flip-flop, a twentieth D flip-flop, and a twenty-first D flip-flop, wherein a D terminal of the eighteenth D flip-flop is connected to the output rising edge synchronization unit, a Q terminal of the eighteenth D flip-flop is connected to the output selection unit, and a CK terminal of the eighteenth D flip-flop is connected to the transmission clock signal SCK through an inverter; the D end of the nineteenth D trigger is connected with the output rising edge synchronization unit, the Q end of the nineteenth D trigger is connected with the output selection unit, and the CK end of the nineteenth D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the twentieth trigger is connected with the output rising edge synchronization unit, the Q end of the twentieth trigger is connected with the output selection unit, and the CK end of the twentieth trigger is connected with the transmission clock signal SCK through the phase inverter; the D end of the twenty-first D trigger is connected with the output rising edge synchronization unit, the Q end of the twenty-first D trigger is connected with the output selection unit, and the CK end of the twenty-first D trigger is connected with the transmission clock signal SCK through the phase inverter.
9. The FLASH memory of the SPI interface for reading data at a high speed according to claim 1, wherein when the external transmission clock signal SCK is at a high level, the output selection unit selects the data output transmitted from the output falling edge synchronization unit; and when the external transmission clock signal SCK is at a low level, the output selection unit selects the data transmitted by the output rising edge synchronization unit to output.
10. The FLASH memory of SPI interface for high speed reading of data according to any of claims 1 or 9, wherein said output selection unit comprises a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer, wherein the a input terminal of said first multiplexer is connected to the output rising edge synchronization unit, the B input terminal of said first multiplexer is connected to the output falling edge synchronization unit, the SEL terminal of said first multiplexer is connected to the transmission clock signal SCK, and the output terminal of said first multiplexer is connected to the HOLD terminal of the SPI interface module; the input end A of the second multiplexer is connected with the output rising edge synchronization unit, the input end B of the second multiplexer is connected with the output falling edge synchronization unit, the SEL end of the second multiplexer is connected with the transmission clock signal SCK, and the output end of the second multiplexer is connected with the WP end of the SPI interface module; the input end A of the third multi-path selector is connected with the output rising edge synchronization unit, the input end B of the third multi-path selector is connected with the output falling edge synchronization unit, the SEL end of the third multi-path selector is connected with the transmission clock signal SCK, and the output end of the third multi-path selector is connected with the SO end of the SPI interface module; the input end A of the fourth multiplexer is connected with the output rising edge synchronization unit, the input end B of the fourth multiplexer is connected with the output falling edge synchronization unit, the SEL end of the fourth multiplexer is connected with the transmission clock signal SCK, and the output end of the fourth multiplexer is connected with the SI end of the SPI interface module.
CN202011604951.1A 2020-12-30 2020-12-30 FLASH memory of SPI interface for reading data at high speed Active CN112542193B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011604951.1A CN112542193B (en) 2020-12-30 2020-12-30 FLASH memory of SPI interface for reading data at high speed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011604951.1A CN112542193B (en) 2020-12-30 2020-12-30 FLASH memory of SPI interface for reading data at high speed

Publications (2)

Publication Number Publication Date
CN112542193A true CN112542193A (en) 2021-03-23
CN112542193B CN112542193B (en) 2023-07-25

Family

ID=75017890

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011604951.1A Active CN112542193B (en) 2020-12-30 2020-12-30 FLASH memory of SPI interface for reading data at high speed

Country Status (1)

Country Link
CN (1) CN112542193B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116580742A (en) * 2023-07-14 2023-08-11 芯天下技术股份有限公司 NOR FLASH resetting method and device, memory chip and equipment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524112A (en) * 1992-06-29 1996-06-04 Sharp Kabushiki Kaisha Interface apparatus for transferring k*n-bit data packets via transmission of K discrete n-bit parallel words and method therefore
JPH09196983A (en) * 1995-11-13 1997-07-31 Matsushita Electric Ind Co Ltd Time counting circuit, pulse converting circuit, and fm demodulation circuit
GB9905513D0 (en) * 1998-09-01 1999-05-05 Samsung Electronics Co Ltd A high-speed dual port synchronous memory device
US20020031043A1 (en) * 2000-09-08 2002-03-14 Kabushiki Kaisha Toshiba Semiconductor memory device
US20070058478A1 (en) * 2005-09-06 2007-03-15 Nec Electronics Corporation Interface circuit
US20100118624A1 (en) * 2008-11-12 2010-05-13 Tetsuya Kaneko Read circuit for semiconductor memory device and semiconductor memory device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524112A (en) * 1992-06-29 1996-06-04 Sharp Kabushiki Kaisha Interface apparatus for transferring k*n-bit data packets via transmission of K discrete n-bit parallel words and method therefore
JPH09196983A (en) * 1995-11-13 1997-07-31 Matsushita Electric Ind Co Ltd Time counting circuit, pulse converting circuit, and fm demodulation circuit
GB9905513D0 (en) * 1998-09-01 1999-05-05 Samsung Electronics Co Ltd A high-speed dual port synchronous memory device
US20020031043A1 (en) * 2000-09-08 2002-03-14 Kabushiki Kaisha Toshiba Semiconductor memory device
US20070058478A1 (en) * 2005-09-06 2007-03-15 Nec Electronics Corporation Interface circuit
US20100118624A1 (en) * 2008-11-12 2010-05-13 Tetsuya Kaneko Read circuit for semiconductor memory device and semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116580742A (en) * 2023-07-14 2023-08-11 芯天下技术股份有限公司 NOR FLASH resetting method and device, memory chip and equipment
CN116580742B (en) * 2023-07-14 2023-09-26 芯天下技术股份有限公司 NOR FLASH resetting method and device, memory chip and equipment

Also Published As

Publication number Publication date
CN112542193B (en) 2023-07-25

Similar Documents

Publication Publication Date Title
CN111736517A (en) Synchronous acquisition and processing card system based on multichannel ADC and FPGA
CN102340316A (en) FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer
US20080279224A1 (en) Alignment and Deskew For Multiple Lanes of Serical Interconnect
CN106933772A (en) The SCI means of communication based on UART IP kernels
US6772251B1 (en) Bit interleaved data serial interface
KR20020032350A (en) Serial/parallel conversion circuit, data transfer control device and electronic equipment
CN104022775A (en) FIFO protocol based digital interface circuit for SerDes technology
CN209640846U (en) A kind of universal serial bus turns the conversion circuit of ahb bus
CN105786741B (en) SOC high-speed low-power-consumption bus and conversion method
CN112542193B (en) FLASH memory of SPI interface for reading data at high speed
CN114116563B (en) High-speed synchronous serial port module based on PCIE bus
US7796063B2 (en) Data transmission circuits and data transceiver systems
CN107832249B (en) System and method for three-wire realization and communication with peripheral equipment with SPI interface
CN107066419B (en) Scalable adaptive NxN channel data communication system
CN115328845B (en) Four-wire serial peripheral interface communication protocol design method
CN111210861B (en) Flash memory
CN115809210A (en) LVDS high-speed data switch based on FPGA
CN111506529B (en) High-speed SPI instruction response circuit applied to FLASH
KR100355295B1 (en) Interface device and method between channel card and if board in bts
CN203071936U (en) Data recording and playback device and system
KR100321981B1 (en) Apparatus for recompensing delay of clock
US10042810B2 (en) Host controller of high-speed data interface with clock-domain crossing
CN220188983U (en) Level conversion and switching device based on CPLD
CN110661687B (en) Full-communication double-bus exchange platform
CN110012369A (en) A kind of FC sonet card

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 518000 Room 101, building 10, Dayun software Town, 8288 Longgang Avenue, he'ao community, Yuanshan street, Longgang District, Shenzhen City, Guangdong Province

Applicant after: XTX Technology Inc.

Address before: 518000 1st floor, building 10, Dayun software Town, 8288 Longgang Avenue, Henggang street, Longgang District, Shenzhen City, Guangdong Province

Applicant before: Paragon Technology (Shenzhen) Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant