CN112542193B - FLASH memory of SPI interface for reading data at high speed - Google Patents

FLASH memory of SPI interface for reading data at high speed Download PDF

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CN112542193B
CN112542193B CN202011604951.1A CN202011604951A CN112542193B CN 112542193 B CN112542193 B CN 112542193B CN 202011604951 A CN202011604951 A CN 202011604951A CN 112542193 B CN112542193 B CN 112542193B
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trigger
output
data
clock signal
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CN112542193A (en
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刘佳庆
黎永健
蒋双泉
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Xtx Technology Inc
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Xtx Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a FLASH memory of SPI interface for reading data at high speed, which samples the input data signal at the rising edge and the falling edge of the transmission clock signal, can double the input data transmission rate without changing the frequency of the external clock signal, and simultaneously receives 4 lines of input data, the input rate of the two is 8 times of SCK frequency, and simultaneously, the data rate is reduced in the chip, the power consumption is reduced, and the subsequent processing is convenient; the two paths of data are synchronized through the output rising edge synchronizing unit and the output falling edge synchronizing unit, the output selecting unit selects the data output of the output falling edge synchronizing unit when the transmission clock signal SCK is at a high level, and the data output of the output rising edge synchronizing unit is selected when the transmission clock signal SCK is at a low level, so that the double rate of the data output is realized under the condition of not changing the clock frequency.

Description

FLASH memory of SPI interface for reading data at high speed
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a FLASH memory of an SPI interface for reading data at high speed.
Background
The FLASH generally adopts an SPI protocol instruction, has higher requirements on the speed of a FLASH read instruction, a circuit in a traditional mode adopts multi-line transmission to meet the high-speed requirements, and some designs adopt a dual-edge output DTR mode for data output in order to improve the speed, but many designs cannot perfectly combine the multi-line transmission and the dual-edge output DTR mode, so that the finally realized speed of read data is not as fast as imagination: only multi-line transmission is adopted, although the multi-line transmission can be double or quadruple rate transmission, the transmission is not carried out by using the falling edge of a transmission clock, and the speed is not optimal; while the mode with dual edge output does not use multi-line transmission, nor is it optimal.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
The invention aims to provide a FLASH memory of an SPI interface for reading data at high speed, which aims to solve the problem that the speed of a read instruction cannot meet the requirement because the prior FLASH cannot combine a DTR mode of multi-line transmission and double-edge output.
The technical scheme of the invention is as follows: a FLASH memory of an SPI interface for reading data at high speed, comprising:
the SPI interface module is used for receiving an external transmission clock signal SCK, inputting a data signal and outputting data of a memory unit in the FLASH memory;
an input rising edge synchronization unit for sampling the input data signal at the rising edge of the transmission clock signal SCK to obtain a first group of data;
the input falling edge synchronization unit samples the input data signal at the falling edge of the transmission clock signal SCK to obtain a second group of data;
a combining unit that receives the first set of data and the second set of data and combines the first set of data and the second set of data;
the synchronization unit is used for synchronizing the combined first group of data and the second group of data to obtain a synchronization result, and transmitting the synchronization result to the storage unit;
the storage unit outputs corresponding data according to the synchronization result transmitted by the synchronization unit;
an output rising edge synchronization unit for synchronizing the data output by the storage unit at the rising edge of the transmission clock signal SCK and connecting the high 4-bit data of the data output by the synchronized storage unit to the output selection unit; and a low 4-bit data connection output falling edge synchronization unit for connecting the data output by the storage unit;
the output falling edge synchronizing unit is used for receiving the low 4-bit data of the data output by the storage unit and transmitted by the output rising edge synchronizing unit, synchronizing the low 4-bit data at the falling edge of the transmission clock signal SCK, and simultaneously connecting the synchronized low 4-bit data with the output selecting unit;
and the output selection unit is used for selecting one of the synchronized high 4-bit data and low 4-bit data to be output to the SPI interface module according to the transmission clock signal SCK, and finally outputting the data through the SPI interface module.
The synchronous unit stores the synchronous result into the storage unit at the rising edge of the external transmission clock signal SCK; or the synchronization result is saved in the memory cell at the falling edge of the external transmission clock signal SCK.
The FLASH memory of the SPI interface for reading data at high speed, wherein the input rising edge synchronization unit comprises a first D trigger, a second D trigger, a third D trigger and a fourth D trigger, the D end of the first D trigger is connected with the HOLD end of the SPI interface module, the Q end of the first D trigger is connected with the combination unit, and the CK end of the first D trigger is connected with the transmission clock signal SCK; the D end of the second D trigger is connected with the WP end of the SPI interface module, the Q end of the second D trigger is connected with the combination unit, and the CK end of the second D trigger is connected with the transmission clock signal SCK; the D end of the third D trigger is connected with the SO end of the SPI interface module, the Q end of the third D trigger is connected with the combination unit, and the CK end of the third D trigger is connected with the transmission clock signal SCK; the D end of the fourth D trigger is connected with the SI end of the SPI interface module, the Q end of the fourth D trigger is connected with the combination unit, and the CK end of the fourth D trigger is connected with the transmission clock signal SCK.
The FLASH memory of the SPI interface for reading data at high speed, wherein the input falling edge synchronizing unit comprises a fifth D trigger, a sixth D trigger, a seventh D trigger and an eighth D trigger, the D end of the fifth D trigger is connected with the HOLD end of the SPI interface module, the Q end of the fifth D trigger is connected with the combining unit, and the CK end of the fifth D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the sixth D trigger is connected with the WP end of the SPI interface module, the Q end of the sixth D trigger is connected with the combination unit, and the CK end of the sixth D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the seventh D trigger is connected with the SO end of the SPI interface module, the Q end of the seventh D trigger is connected with the combination unit, and the CK end of the seventh D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the eighth D trigger is connected with the SI end of the SPI interface module, the Q end of the eighth D trigger is connected with the combination unit, and the CK end of the eighth D trigger is connected with the transmission clock signal SCK through the inverter.
And the combination unit adopts a buffer.
The synchronous unit adopts a ninth D trigger, the D end of the ninth D trigger is connected with the combination unit, the CK end of the ninth D trigger is connected with the transmission clock signal SCK, and the Q end of the ninth D trigger is connected with the storage unit; and the end D of the synchronization unit is connected with the end Q of the input rising edge synchronization unit and the end Q of the input falling edge synchronization unit through a buffer of the combination unit, and the end Q of the synchronization unit outputs the synchronization result to the storage unit.
The FLASH memory of the SPI interface for reading data at high speed, wherein the output rising edge synchronization unit comprises a tenth D trigger, an eleventh D trigger, a twelfth D trigger, a thirteenth D trigger, a fourteenth D trigger, a fifteenth D trigger, a sixteenth D trigger and a seventeenth D trigger, the D end of the tenth D trigger is connected with the data output end of the storage unit, the Q end of the tenth D trigger is connected with the output selection unit, and the CK end of the tenth D trigger is connected with the transmission clock signal SCK; the D end of the eleventh D trigger is connected with the data output end of the storage unit, the Q end of the eleventh D trigger is connected with the output selection unit, and the CK end of the eleventh D trigger is connected with the transmission clock signal SCK; the D end of the twelfth D trigger is connected with the data output end of the storage unit, the Q end of the twelfth D trigger is connected with the output selection unit, and the CK end of the twelfth D trigger is connected with the transmission clock signal SCK; the D end of the thirteenth D trigger is connected with the data output end of the storage unit, the Q end of the thirteenth D trigger is connected with the output selection unit, and the CK end of the thirteenth D trigger is connected with the transmission clock signal SCK; the D end of the fourteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fourteenth D trigger is connected with the output falling edge synchronization unit; the D end of the fifteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fifteenth D trigger is connected with the output falling edge synchronization unit; the D end of the sixteenth D trigger is connected with the data output end of the storage unit, and the Q end of the sixteenth D trigger is connected with the output falling edge synchronization unit; the D end of the seventeenth D trigger is connected with the data output end of the storage unit, and the Q end of the seventeenth D trigger is connected with the output falling edge synchronization unit.
The FLASH memory of the SPI interface for reading data at high speed, wherein the output falling edge synchronizing unit comprises an eighteenth D trigger, a nineteenth D trigger, a twentieth D trigger and a twenty first D trigger, the D end of the eighteenth D trigger is connected with the output rising edge synchronizing unit, the Q end of the eighteenth D trigger is connected with the output selecting unit, and the CK end of the eighteenth D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the nineteenth D trigger is connected with the output rising edge synchronous unit, the Q end of the nineteenth D trigger is connected with the output selection unit, and the CK end of the nineteenth D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the twenty-D trigger is connected with the output rising edge synchronous unit, the Q end of the twenty-D trigger is connected with the output selection unit, and the CK end of the twenty-D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the twenty-first D trigger is connected with the output rising edge synchronous unit, the Q end of the twenty-first D trigger is connected with the output selection unit, and the CK end of the twenty-first D trigger is connected with the transmission clock signal SCK through an inverter.
The output selecting unit selects the data output transmitted by the output falling edge synchronizing unit when the external transmission clock signal SCK is at a high level; when the external transmission clock signal SCK is at a low level, the output selecting unit selects the data output transmitted from the output rising edge synchronizing unit.
The FLASH memory of the SPI interface for reading data at high speed, wherein the output selection unit comprises a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer, wherein the input end A of the first multiplexer is connected with an output rising edge synchronization unit, the input end B of the first multiplexer is connected with an output falling edge synchronization unit, the SEL end of the first multiplexer is connected with a transmission clock signal SCK, and the output end of the first multiplexer is connected with the HOLD end of the SPI interface module; the input end A of the second multiplexer is connected with the rising edge synchronous unit, the input end B of the second multiplexer is connected with the falling edge synchronous unit, the SEL end of the second multiplexer is connected with the transmission clock signal SCK, and the output end of the second multiplexer is connected with the WP end of the SPI interface module; the input end A of the third multiplexer is connected with the rising edge synchronous unit, the input end B of the third multiplexer is connected with the falling edge synchronous unit, the SEL end of the third multiplexer is connected with the transmission clock signal SCK, and the output end of the third multiplexer is connected with the SO end of the SPI interface module; the input end A of the fourth multiplexer is connected with the rising edge synchronous unit, the input end B of the fourth multiplexer is connected with the falling edge synchronous unit, the SEL end of the fourth multiplexer is connected with the transmission clock signal SCK, and the output end of the fourth multiplexer is connected with the SI end of the SPI interface module.
The invention has the beneficial effects that: the invention provides a FLASH memory of an SPI interface for reading data at high speed, which is characterized in that an input rising edge synchronous unit, an input falling edge synchronous unit, a combination unit, a synchronous unit and a bidirectional SPI interface module are used for respectively sampling an input data signal at the rising edge and the falling edge of an external transmission clock signal SCK, so that the doubling of the transmission rate of the input data can be realized under the condition of not changing the frequency of the external clock signal; meanwhile, the data input by 4 lines are received, the input rate of the data input by 4 lines can be 8 times of the SCK frequency, meanwhile, the data rate is reduced in the chip, the power consumption is reduced, and the subsequent processing is convenient; according to the technical scheme, two paths of data are synchronized through the D trigger of the output rising edge synchronization unit and the D trigger of the output falling edge synchronization unit, when the transmission clock signal SCK is in a high level, the multiplexer MUX of the output selection unit selects the data output of the Q end of the D trigger of the output falling edge synchronization unit, when the transmission clock signal SCK is in a low level, the data output of the Q end of the D trigger of the output rising edge synchronization unit is selected, and double rate of the data output is realized under the condition that the clock frequency is not changed.
Drawings
Fig. 1 is a schematic diagram of the structure of a FLASH memory of an SPI interface for reading data at high speed in the present invention.
Fig. 2 is a schematic diagram of the structures of the input rising edge synchronization unit, the input falling edge synchronization unit, the combination unit, the synchronization unit and the storage unit in the present invention.
Fig. 3 is a schematic diagram of the structures of the memory unit, the output rising edge synchronization unit, the output falling edge synchronization unit, and the output selection unit in the present invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1 to 3, a FLASH memory of an SPI interface (generally referred to as a serial peripheral interface) for reading data at high speed includes:
the SPI interface module 1 is used for receiving an external transmission clock signal SCK, inputting a data signal and outputting data of the memory unit 6 in the FLASH memory;
an input rising edge synchronization unit 2 for sampling the input data signal at the rising edge of the transmission clock signal SCK to obtain a first set of data;
an input falling edge synchronizing unit 3, which samples the input data signal at the falling edge of the transmission clock signal SCK to obtain a second set of data;
a combining unit 4 that receives the first set of data and the second set of data and combines the first set of data and the second set of data;
the synchronization unit 5 synchronizes the combined first group of data and the second group of data to obtain a synchronization result, and transmits the synchronization result to the storage unit 6;
a storage unit 6 for outputting corresponding data according to the synchronization result transmitted by the synchronization unit 5;
an output rising edge synchronizing unit 7 for synchronizing the data output from the storage unit 6 at the rising edge of the transmission clock signal SCK and simultaneously connecting the high 4-bit data of the data output from the synchronized storage unit 6 to the output selecting unit 9; and a low 4-bit data connection output-output falling edge synchronization unit 8 for connecting the data output from the storage unit 6;
an output falling edge synchronizing unit 8 for receiving the low 4-bit data of the data output from the storage unit 6 and transmitted by the output rising edge synchronizing unit 7, synchronizing the low 4-bit data at the falling edge of the transmission clock signal SCK, and simultaneously connecting the synchronized low 4-bit data to the output selecting unit 9;
and the output selection unit 9 is configured to select one of the synchronized high 4-bit data and low 4-bit data according to the transmission clock signal SCK to output to the SPI interface module 1, and finally output the selected one through the SPI interface module 1.
In some embodiments, the synchronization unit 5 may store the synchronization result in the storage unit 6 on a rising edge of the external transmission clock signal SCK, or may store the synchronization result in the storage unit 6 on a falling edge of the external transmission clock signal SCK.
In some embodiments, the input rising edge synchronization unit 2 includes a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, where a D end of the first D flip-flop is connected to a HOLD end of the SPI interface module 1, a Q end of the first D flip-flop is connected to the combining unit 4, and a CK end of the first D flip-flop is connected to the transmission clock signal SCK; the D end of the second D trigger is connected with the WP end of the SPI interface module 1, the Q end of the second D trigger is connected with the combination unit 4, and the CK end of the second D trigger is connected with the transmission clock signal SCK; the D end of the third D trigger is connected with the SO end of the SPI interface module 1, the Q end of the third D trigger is connected with the combination unit 4, and the CK end of the third D trigger is connected with the transmission clock signal SCK; the D end of the fourth D trigger is connected with the SI end of the SPI interface module 1, the Q end of the fourth D trigger is connected with the combination unit 4, and the CK end of the fourth D trigger is connected with the transmission clock signal SCK.
In some specific embodiments, the input falling edge synchronization unit 3 includes a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and an eighth D flip-flop, where a D end of the fifth D flip-flop is connected to a HOLD end of the SPI interface module 1, a Q end of the fifth D flip-flop is connected to the combining unit 4, and a CK end of the fifth D flip-flop is connected to the transmission clock signal SCK through an inverter; the D end of the sixth D trigger is connected with the WP end of the SPI interface module 1, the Q end of the sixth D trigger is connected with the combination unit 4, and the CK end of the sixth D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the seventh D trigger is connected with the SO end of the SPI interface module 1, the Q end of the seventh D trigger is connected with the combination unit 4, and the CK end of the seventh D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the eighth D trigger is connected with the SI end of the SPI interface module 1, the Q end of the eighth D trigger is connected with the combination unit 4, and the CK end of the eighth D trigger is connected with the transmission clock signal SCK through an inverter.
In some embodiments, the combining unit 4 employs a buffer.
In some embodiments, the synchronization unit 5 adopts a ninth D flip-flop, a D end of the ninth D flip-flop is connected to the combining unit 4, a CK end of the ninth D flip-flop is connected to the transmission clock signal SCK, and a Q end of the ninth D flip-flop is connected to the storage unit 6; the D end of the synchronization unit 5 is connected with the Q ends of the input rising edge synchronization unit 2 and the input falling edge synchronization unit 3 through the buffer of the combination unit 4, and the Q end of the synchronization unit 5 outputs the synchronization result to the storage unit 6.
In the technical scheme, through the input rising edge synchronization unit 2, the input falling edge synchronization unit 3, the combination unit 4, the synchronization unit 5 and the bidirectional SPI interface module 1, the rising edge and the falling edge of an external transmission clock signal SCK are used for respectively sampling the input data signals, so that the data input rate of 8 times under a lower frequency clock is realized.
In this technical solution, the D flip-flop of the input rising edge synchronization unit 2 samples data at a rising edge of the transmission clock signal SCK, and the D flip-flop of the input falling edge synchronization unit 3 samples data at a falling edge of the transmission clock signal SCK, so that two sets of input data are synchronously output to the storage unit 6 at a rising edge of the external transmission clock signal SCK; therefore, it is possible to achieve a doubling of the transmission rate of input data without changing the frequency of the external clock signal; and simultaneously, the data input by 4 lines are accepted, the input rate of the data input by the 4 lines can be 8 times of the SCK frequency, and meanwhile, the data rate is reduced in the chip, so that the power consumption is reduced, and the subsequent processing is convenient.
In the technical scheme, the I/O interface of the serial interface flash memory is improved, so that double speed and external data can be adopted; other components of the bi-directional I/O serial output flash memory, transmission between the components, control implementation schemes, and connection schemes with the outside (such as high level Vcc, ground GND, chip select signals cs#, w# and hold#) may be the same as in the prior art, and will not be described herein.
In some specific embodiments, the output rising edge synchronization unit 7 includes a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, and a seventeenth D flip-flop, where a D terminal of the tenth D flip-flop is connected to the data output terminal of the storage unit 6, a Q terminal of the tenth D flip-flop is connected to the output selection unit 9, and a CK terminal of the tenth D flip-flop is connected to the transmission clock signal SCK; the D end of the eleventh D trigger is connected with the data output end of the storage unit 6, the Q end of the eleventh D trigger is connected with the output selection unit 9, and the CK end of the eleventh D trigger is connected with the transmission clock signal SCK; the D end of the twelfth D trigger is connected with the data output end of the storage unit 6, the Q end of the twelfth D trigger is connected with the output selection unit 9, and the CK end of the twelfth D trigger is connected with the transmission clock signal SCK; the D end of the thirteenth D trigger is connected with the data output end of the storage unit 6, the Q end of the thirteenth D trigger is connected with the output selection unit 9, and the CK end of the thirteenth D trigger is connected with the transmission clock signal SCK; the D end of the fourteenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the fourteenth D trigger is connected with the output falling edge synchronization unit 8; the D end of the fifteenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the fifteenth D trigger is connected with the output falling edge synchronization unit 8; the D end of the sixteenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the sixteenth D trigger is connected with the output falling edge synchronization unit 8; the D end of the seventeenth D trigger is connected with the data output end of the storage unit 6, and the Q end of the seventeenth D trigger is connected with the output falling edge synchronization unit 8.
In some specific embodiments, the output falling edge synchronization unit 8 includes an eighteenth D flip-flop, a nineteenth D flip-flop, a twentieth D flip-flop, and a twenty-first D flip-flop, where a D terminal of the eighteenth D flip-flop is connected to the output rising edge synchronization unit 7, a Q terminal of the eighteenth D flip-flop is connected to the output selection unit 9, and a CK terminal of the eighteenth D flip-flop is connected to the transmission clock signal SCK through an inverter; the D end of the nineteenth D trigger is connected with the output rising edge synchronizing unit 7, the Q end of the nineteenth D trigger is connected with the output selecting unit 9, and the CK end of the nineteenth D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the twenty-D trigger is connected with the output rising edge synchronizing unit 7, the Q end of the twenty-D trigger is connected with the output selecting unit 9, and the CK end of the twenty-D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the twenty-first D trigger is connected with the output rising edge synchronizing unit 7, the Q end of the twenty-first D trigger is connected with the output selecting unit 9, and the CK end of the twenty-first D trigger is connected with the transmission clock signal SCK through an inverter.
In some embodiments, the output selecting unit 9 includes a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer, where an a input terminal of the first multiplexer is connected to the output rising edge synchronizing unit 7, a B input terminal of the first multiplexer is connected to the output falling edge synchronizing unit 8, a SEL terminal of the first multiplexer is connected to the transmission clock signal SCK, and an output terminal of the first multiplexer is connected to the HOLD terminal of the SPI interface module 1; the input end A of the second multiplexer is connected with the rising edge output synchronous unit 7, the input end B of the second multiplexer is connected with the falling edge output synchronous unit 8, the SEL end of the second multiplexer is connected with the transmission clock signal SCK, and the output end of the second multiplexer is connected with the WP end of the SPI interface module 1; the input end A of the third multiplexer is connected with the rising edge output synchronization unit 7, the input end B of the third multiplexer is connected with the falling edge output synchronization unit 8, the SEL end of the third multiplexer is connected with the transmission clock signal SCK, and the output end of the third multiplexer is connected with the SO end of the SPI interface module 1; the input end A of the fourth multiplexer is connected with the rising edge output synchronization unit 7, the input end B of the fourth multiplexer is connected with the falling edge output synchronization unit 8, the SEL end of the fourth multiplexer is connected with the transmission clock signal SCK, and the output end of the fourth multiplexer is connected with the SI end of the SPI interface module 1.
When the external transmission clock signal SCK is at a high level, the output selecting unit 9 selects the data output of the D flip-flop Q end of the output falling edge synchronizing unit 8, and when the external transmission clock signal SCK is at a low level, selects the data output of the highest 4-bit D flip-flop Q end of the output rising edge synchronizing unit 7, and outputs the output data through the SPI interface module 1, respectively.
In the technical scheme, the D trigger of the output rising edge synchronization unit 7 and the D trigger of the output falling edge synchronization unit 8 synchronize two paths of data; the multiplexer MUX of the output selecting unit 9 selects the data output of the D flip-flop Q terminal of the output falling edge synchronizing unit 8 when the transmission clock signal SCK is at a high level, and selects the data output of the D flip-flop Q terminal of the output rising edge synchronizing unit 7 when the transmission clock signal SCK is at a low level; without changing the clock frequency, double rate of data output is achieved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A FLASH memory of an SPI interface for reading data at a high speed, comprising:
the SPI interface module is used for receiving an external transmission clock signal SCK, inputting a data signal and outputting data of a memory unit in the FLASH memory;
an input rising edge synchronization unit for sampling the input data signal at the rising edge of the transmission clock signal SCK to obtain a first group of data;
the input falling edge synchronization unit samples the input data signal at the falling edge of the transmission clock signal SCK to obtain a second group of data;
a combining unit that receives the first set of data and the second set of data and combines the first set of data and the second set of data;
the synchronization unit is used for synchronizing the combined first group of data and the second group of data to obtain a synchronization result, and transmitting the synchronization result to the storage unit;
the storage unit outputs corresponding data according to the synchronization result transmitted by the synchronization unit;
an output rising edge synchronization unit for synchronizing the data output by the storage unit at the rising edge of the transmission clock signal SCK and connecting the high 4-bit data of the data output by the synchronized storage unit to the output selection unit; and a low 4-bit data connection output falling edge synchronization unit for connecting the data output by the storage unit;
the output falling edge synchronizing unit is used for receiving the low 4-bit data of the data output by the storage unit and transmitted by the output rising edge synchronizing unit, synchronizing the low 4-bit data at the falling edge of the transmission clock signal SCK, and simultaneously connecting the synchronized low 4-bit data with the output selecting unit;
and the output selection unit is used for selecting one of the synchronized high 4-bit data and low 4-bit data to be output to the SPI interface module according to the transmission clock signal SCK, and finally outputting the data through the SPI interface module.
2. The FLASH memory of the SPI interface for high-speed reading of data according to claim 1, wherein said synchronizing unit saves said synchronizing result into said memory unit at a rising edge of said external transmission clock signal SCK; or the synchronization result is saved in the memory cell at the falling edge of the external transmission clock signal SCK.
3. The FLASH memory of the SPI interface for high-speed data reading according to claim 1, wherein the input rising edge synchronization unit comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, a D terminal of the first D flip-flop is connected to a HOLD terminal of the SPI interface module, a Q terminal of the first D flip-flop is connected to the combining unit, and a CK terminal of the first D flip-flop is connected to the transmission clock signal SCK; the D end of the second D trigger is connected with the WP end of the SPI interface module, the Q end of the second D trigger is connected with the combination unit, and the CK end of the second D trigger is connected with the transmission clock signal SCK; the D end of the third D trigger is connected with the SO end of the SPI interface module, the Q end of the third D trigger is connected with the combination unit, and the CK end of the third D trigger is connected with the transmission clock signal SCK; the D end of the fourth D trigger is connected with the SI end of the SPI interface module, the Q end of the fourth D trigger is connected with the combination unit, and the CK end of the fourth D trigger is connected with the transmission clock signal SCK.
4. The FLASH memory of the SPI interface for high-speed data reading according to claim 1, wherein the input falling edge synchronizing unit comprises a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and an eighth D flip-flop, a D terminal of the fifth D flip-flop being connected to a HOLD terminal of the SPI interface module, a Q terminal of the fifth D flip-flop being connected to the combining unit, a CK terminal of the fifth D flip-flop being connected to the transmission clock signal SCK through an inverter; the D end of the sixth D trigger is connected with the WP end of the SPI interface module, the Q end of the sixth D trigger is connected with the combination unit, and the CK end of the sixth D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the seventh D trigger is connected with the SO end of the SPI interface module, the Q end of the seventh D trigger is connected with the combination unit, and the CK end of the seventh D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the eighth D trigger is connected with the SI end of the SPI interface module, the Q end of the eighth D trigger is connected with the combination unit, and the CK end of the eighth D trigger is connected with the transmission clock signal SCK through the inverter.
5. FLASH memory of SPI interface for high speed reading of data according to claim 1, wherein said combining unit employs a buffer.
6. The FLASH memory of the SPI interface for high-speed data reading according to any one of claims 1, 2, and 5, wherein said synchronizing means is a ninth D flip-flop, a D terminal of the ninth D flip-flop is connected to said combining means, a CK terminal of the ninth D flip-flop is connected to said transmission clock signal SCK, and a Q terminal of the ninth D flip-flop is connected to said memory means; and the end D of the synchronization unit is connected with the end Q of the input rising edge synchronization unit and the end Q of the input falling edge synchronization unit through a buffer of the combination unit, and the end Q of the synchronization unit outputs the synchronization result to the storage unit.
7. The FLASH memory of the SPI interface for high-speed data reading according to claim 1, wherein the output rising edge synchronizing unit comprises a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, and a seventeenth D flip-flop, a D terminal of the tenth D flip-flop being connected to a data output terminal of the memory unit, a Q terminal of the tenth D flip-flop being connected to the output selecting unit, a CK terminal of the tenth D flip-flop being connected to the transmission clock signal SCK; the D end of the eleventh D trigger is connected with the data output end of the storage unit, the Q end of the eleventh D trigger is connected with the output selection unit, and the CK end of the eleventh D trigger is connected with the transmission clock signal SCK; the D end of the twelfth D trigger is connected with the data output end of the storage unit, the Q end of the twelfth D trigger is connected with the output selection unit, and the CK end of the twelfth D trigger is connected with the transmission clock signal SCK; the D end of the thirteenth D trigger is connected with the data output end of the storage unit, the Q end of the thirteenth D trigger is connected with the output selection unit, and the CK end of the thirteenth D trigger is connected with the transmission clock signal SCK; the D end of the fourteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fourteenth D trigger is connected with the output falling edge synchronization unit; the D end of the fifteenth D trigger is connected with the data output end of the storage unit, and the Q end of the fifteenth D trigger is connected with the output falling edge synchronization unit; the D end of the sixteenth D trigger is connected with the data output end of the storage unit, and the Q end of the sixteenth D trigger is connected with the output falling edge synchronization unit; the D end of the seventeenth D trigger is connected with the data output end of the storage unit, and the Q end of the seventeenth D trigger is connected with the output falling edge synchronization unit.
8. The FLASH memory of the SPI interface for high-speed data reading according to claim 1, wherein the output falling edge synchronizing unit comprises an eighteenth D flip-flop, a nineteenth D flip-flop, a twentieth D flip-flop, and a twenty-first D flip-flop, a D terminal of the eighteenth D flip-flop being connected to the output rising edge synchronizing unit, a Q terminal of the eighteenth D flip-flop being connected to the output selecting unit, a CK terminal of the eighteenth D flip-flop being connected to the transmission clock signal SCK through an inverter; the D end of the nineteenth D trigger is connected with the output rising edge synchronous unit, the Q end of the nineteenth D trigger is connected with the output selection unit, and the CK end of the nineteenth D trigger is connected with the transmission clock signal SCK through an inverter; the D end of the twenty-D trigger is connected with the output rising edge synchronous unit, the Q end of the twenty-D trigger is connected with the output selection unit, and the CK end of the twenty-D trigger is connected with the transmission clock signal SCK through the inverter; the D end of the twenty-first D trigger is connected with the output rising edge synchronous unit, the Q end of the twenty-first D trigger is connected with the output selection unit, and the CK end of the twenty-first D trigger is connected with the transmission clock signal SCK through an inverter.
9. The FLASH memory of the SPI interface for high-speed data reading according to claim 1, wherein when said external transmission clock signal SCK is at a high level, an output selecting unit selects the data output transmitted from said output falling edge synchronizing unit; when the external transmission clock signal SCK is at a low level, the output selecting unit selects the data output transmitted from the output rising edge synchronizing unit.
10. The FLASH memory of the SPI interface for high-speed data reading according to any one of claims 1 or 9, wherein said output selecting unit comprises a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer, an a input terminal of said first multiplexer being connected to said output rising edge synchronizing unit, a B input terminal of said first multiplexer being connected to said output falling edge synchronizing unit, a SEL terminal of said first multiplexer being connected to said transmission clock signal SCK, an output terminal of said first multiplexer being connected to said HOLD terminal of said SPI interface module; the input end A of the second multiplexer is connected with the rising edge synchronous unit, the input end B of the second multiplexer is connected with the falling edge synchronous unit, the SEL end of the second multiplexer is connected with the transmission clock signal SCK, and the output end of the second multiplexer is connected with the WP end of the SPI interface module; the input end A of the third multiplexer is connected with the rising edge synchronous unit, the input end B of the third multiplexer is connected with the falling edge synchronous unit, the SEL end of the third multiplexer is connected with the transmission clock signal SCK, and the output end of the third multiplexer is connected with the SO end of the SPI interface module; the input end A of the fourth multiplexer is connected with the rising edge synchronous unit, the input end B of the fourth multiplexer is connected with the falling edge synchronous unit, the SEL end of the fourth multiplexer is connected with the transmission clock signal SCK, and the output end of the fourth multiplexer is connected with the SI end of the SPI interface module.
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