CN112540952B - System on chip with on-chip parallel interface - Google Patents
System on chip with on-chip parallel interface Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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Abstract
The invention relates to a system on chip with an on-chip parallel interface, which comprises an MCU (microprogrammed control Unit) kernel and an FPGA (field programmable gate array) module which are interacted through a system bus, wherein at least one parallel interface is constructed in the chip by utilizing programmable logic resources of the FPGA module, each parallel interface comprises more than two parallel channels, and the number of the parallel channels and the data width of each parallel channel are dynamically configured through the MCU kernel. The system on chip adopts the parallel interface arranged in the chip to transmit data, is expected to obtain higher transmission rate, improves the application flexibility of the system on chip, can dynamically configure the number of parallel channels of the parallel interface and the data width of each parallel channel according to the requirement, is convenient for a user to use, and is convenient for meeting diversified data transmission requirements.
Description
Technical Field
The invention relates to the field of FPGA development, in particular to a system on a chip with an on-chip parallel interface.
Background
The functions and performances of traditional FPGA (Field Programmable Gate Array) and CPU (central processing unit) discrete devices are increasingly difficult to meet the increasingly large and diversified data processing requirements. In order to meet the requirements of performance, expandability and integration, the industry provides a system on chip (SoC) architecture which integrates the advantages of an FPGA and a CPU and is realized based on an FPGA and an MCU (Micro-controller Unit), and by connecting the MCU, a memory, external equipment and the like with an FPGA core, the external equipment can be freely expanded according to different application scenarios, so that the SoC architecture has good expandability and meets the requirements of different application fields, and has become a technical hotspot.
The communication interface between the MCU and the external equipment comprises a serial interface and a parallel interface, the serial interface adopts a serial communication mode, a communication line is simple, but data can be transmitted by one bit, and the transmission speed is slow. The parallel interface adopts a parallel communication mode, information is transmitted on a plurality of data lines in bytes or words, data is transmitted simultaneously, the data transmission is faster compared with a serial interface under the frequency of a simultaneous clock, and the parallel data basically does not require a fixed format compared with the format specified by a serial data interface, so that the data transmission is simpler.
In order to optimize the system-on-chip design realized based on the MCU and the FPGA, improve the data transmission performance of the system-on-chip and improve the application flexibility of the system-on-chip, the invention provides the system-on-chip with the on-chip parallel interface.
Disclosure of Invention
The invention provides a system on chip with an on-chip parallel interface, which is realized based on the resources of an MCU (microprogrammed control Unit) and an FPGA (field programmable Gate array), and can realize higher transmission rate and higher application flexibility by utilizing the parallel interface built in the chip.
The system on chip with the parallel interfaces on chip provided by the invention comprises an MCU core and an FPGA module which are interacted through a system bus, wherein at least one parallel interface is constructed in the chip by utilizing programmable logic resources of the FPGA module, each parallel interface comprises more than two parallel channels, and the number of the parallel channels and the data width of each parallel channel are dynamically configured through the MCU core.
Optionally, the parallel interface includes a bus interface unit connected to the system bus, and the bus interface unit obtains configuration information about the parallel channels sent by the MCU core through the system bus, and configures each of the parallel channels through programmable logic resources of the FPGA module.
Optionally, the parallel interface includes a parallel interface controller unit connected to the bus interface unit, the parallel interface controller unit includes a plurality of registers, an address of each register is mapped to an address storage space of the MCU core, and the configuration information about the parallel channel acquired by the bus interface unit is mapped to a corresponding register for storage.
Optionally, the parallel interface includes a parallel channel interface corresponding to each parallel channel, each parallel channel interface communicates with an external device of the MCU core according to a parallel interface protocol, and the parallel interface controller unit maps information stored in each register to configuration information for each parallel channel interface.
Optionally, the parallel interface controller unit includes a register read-write sequential logic, the register read-write sequential logic receives address information of the register output by the bus interface unit to select a corresponding register, and the register read-write sequential logic also receives configuration information about the parallel channel and maps the configuration information to the register of the corresponding address.
Optionally, the parallel interface controller unit includes a parallel port configuration register corresponding to each parallel channel in the parallel interface, where the parallel port configuration register is used to store information of data width allocated to the corresponding parallel channel by the MCU core; and the number of parallel port configuration registers corresponding to the same parallel interface is the number of parallel channels in the parallel interface.
Optionally, the parallel interface controller unit further includes a parallel port control register, a parallel port state register, a parallel port input register, and a parallel port output register corresponding to each parallel channel in the parallel interface, where the parallel port control register is configured to store control information when data is read or written through a corresponding parallel channel interface, the parallel port state register is configured to store state information of the corresponding parallel channel interface, the parallel port input register is configured to store data read from the corresponding parallel channel interface, and the parallel port output register is configured to store data to be written into the corresponding parallel channel interface.
Optionally, the parallel interface controller unit further includes a clock frequency division register corresponding to each parallel channel in the parallel interface, and the clock frequency division register is connected to the clock signal of the MCU core and is used to store a clock frequency division coefficient for the corresponding parallel channel interface.
Optionally, the parallel interface includes a clock generator unit connected to the parallel interface controller unit, and the clock generator unit is configured to obtain a clock frequency division coefficient output by the parallel interface controller unit and a clock signal of the MCU core, and generate a frequency division clock.
Optionally, the parallel interface includes a data receiving and sending unit connected to the parallel interface controller unit, and the data receiving and sending unit is configured to obtain data from the parallel interface controller unit under the control of the MCU core and process the data into data matched with the data width of each of the parallel channels and the frequency division clock.
The system on chip with the parallel interfaces in the chip provided by the invention adopts the parallel interfaces arranged in the chip to carry out data transmission, is expected to obtain higher transmission rate, improves the application flexibility of the system on chip, and can dynamically configure the number of the parallel channels of the parallel interfaces and the data width of each parallel channel according to the requirements, thereby being convenient for users to use and meeting the diversified data transmission requirements.
Drawings
FIG. 1 is a block diagram of a system on chip with an on-chip parallel interface according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a bus interface unit according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a parallel interface controller unit according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a clock generator unit according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a data receiving and transmitting unit in an embodiment of the present invention.
FIG. 6 is a flowchart illustrating a system-on-chip configuration parallel interface with an on-chip parallel interface according to an embodiment of the present invention.
Description of reference numerals:
10-a system on a chip; 100-MCU kernel; 200-FPGA module; 110 — a system bus; 210-a bus interface unit; 211-bus data logic analysis part; 212-logical buffer portion; 220-a parallel interface controller unit; 230-a clock generator unit; 240-data receiving transmitter unit.
Detailed Description
The system on chip with on-chip parallel interface of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The embodiment of the invention relates to a system on chip with an on-chip parallel interface, which utilizes the advantage that the transmission rate of serial interface data is higher under the same clock frequency compared with a parallel interface, and constructs the parallel interface in the system on chip realized based on an MCU and an FPGA, so that the system on chip not only has the advantages of the MCU and the FPGA, but also can realize higher transmission rate, thereby having higher application flexibility. The following is a detailed description.
The system on chip with the parallel interfaces on chip comprises an MCU core and an FPGA module which are interacted through a system bus, wherein at least one parallel interface is constructed in the chip by utilizing programmable logic resources of the FPGA module, each parallel interface comprises more than two parallel channels, and the number of the parallel channels and the data width of each parallel channel are dynamically configured through the MCU core. The system on chip makes full use of the programmable characteristic of FPGA, realizes a parallel interface with a plurality of parallel channels based on FPGA logic resources, the parallel channels can be used as channels for data transmission between an MCU kernel and external equipment (referring to the external equipment of the MCU kernel, specifically, the internal equipment or the external equipment of the chip), and the number of the parallel channels and the data width of each parallel channel in each parallel channel are dynamically configured through the MCU kernel by the programmable characteristic of FPGA, so that a user can adjust the specific channel number of each parallel interface and the data width of each channel from the software level of the MCU kernel, compared with the parallel interface with fixed channel number and fixed channel data width, the system on chip adopting the embodiment of the invention can select the parallel interface design most suitable for the current data transmission mode according to the data transmission requirement and the contents such as system power consumption, size and the like, has great flexibility.
FIG. 1 is a block diagram of a system on chip with an on-chip parallel interface according to an embodiment of the present invention. Referring to fig. 1, in one embodiment, the system on a chip 10 includes an MCU core 100 and an FPGA module 200, which interact with each other via a system bus 110.
Specifically, the MCU core 100 and the FPGA module 200 may be integrated in the same chip. Programmable logic resources in the form of an FPGA are formed on the chip and are connected with the MCU core 100 as an FPGA module 200, and the MCU core 100 may be a soft core or a hard core. The programmable logic resources of the FPGA module 200 mainly include a programmable LCB (Logical Control Block, a logic Control Block such as a lookup table, an adder, a register, a multiplexer, and the like), a clock network resource, a clock processing unit, a Block random access memory (Block RAM), a DSP (digital signal processing) core, an interface resource, and the like. It can be understood that, according to the functional structure of the system on chip described in the embodiment of the present application, a person skilled in the art can write a functional module by using a hardware description language (such as Verilog HDL) by using a method disclosed in the art, and perform steps such as simulation and synthesis, so as to convert the parallel interface implemented by using FPGA resources in the embodiment of the present invention into an FPGA circuit, which is known by those skilled in the art, and this embodiment will not be described in detail. In addition, the system Bus for enabling the MCU core 100 and the FPGA module 200 to interact may adopt Advanced High Performance Bus (AHB), wishbone Bus (WB Bus for short), Avalon Bus and other Bus types disclosed in the art.
Referring to fig. 1, in an embodiment, the parallel interface built in a chip by using the programmable logic resources of the FPGA module 200 may include a bus interface unit 210 connected to the system bus 110, a parallel interface controller unit 220 connected to the bus interface unit 210, a clock generator unit 230 connected to the parallel interface controller unit 220, and a data receiving and transmitting unit 240, and the parallel interface includes parallel channel interfaces (e.g., a parallel channel interface 1, a parallel channel interface 2, a parallel channel interface 3, a parallel channel interface.
Specifically, in the parallel interface, the bus interface unit 210 is configured to obtain, through the system bus 210, configuration information about parallel channels of the parallel interface, which is sent by the MCU core 100, and configure each parallel channel through the programmable logic resource of the FPGA module 200. The parallel interface controller unit 220 includes a plurality of registers, an address of each register is mapped to an address storage space of the MCU core 100, and the configuration information about the parallel channels of the respective parallel interfaces acquired by the bus interface unit 210 can be mapped to the corresponding registers for storage. In the parallel interfaces, each parallel channel interface communicates with an external device of the MCU core 100 according to a parallel interface protocol, and the parallel interface controller unit 220 maps information stored in its internal register to configuration information for each parallel channel interface, so as to implement configuration of the parallel channels. The system on chip according to the embodiment of the present invention is further described with reference to fig. 2 to 6.
Fig. 2 is a schematic structural diagram of a bus interface unit according to an embodiment of the present invention. Referring to fig. 2, after receiving an operation command of the MCU core 100, the bus interface unit 210 may analyze information sent from the system bus 110 according to a bus protocol, obtain information on the system bus 110, and send the information to the parallel interface controller unit 210. Specifically, the bus interface unit 210 may calculate an access address of a parallel interface to be configured or perform data transmission by decoding an address signal on the system bus 110. After the access address of the parallel interface is obtained, the control signal of the system bus 110 is analyzed, and according to the control information obtained by analysis, the number of parallel channels of the parallel interface corresponding to the access address and the data width of each parallel channel are configured to complete the configuration of the parallel interface.
As an example, the instructions transmitted from the system bus 110 of the MCU core 100 that the bus interface unit 210 can parse include an instruction about configuring the number of parallel channels and an instruction about configuring the data width of each parallel channel. After the configuration of the number of parallel channels of the parallel interface and the data width of each parallel channel is completed, the configured parallel interface may be used to perform data transmission operations, such as reading data or writing data (i.e., read-write operations). When performing read and write operations, the instructions on the system bus 110 that can be resolved by the bus interface unit 210 include a read data instruction for each parallel channel or a write data instruction for each parallel channel, and the like.
Referring to fig. 2, in an embodiment, the bus interface unit 210 includes a bus data logic analysis portion 211 and a logic buffer portion 212, where the bus data logic analysis portion 211 is directly connected to the system bus 110 and is configured to analyze data (or instructions) on the system bus 110 according to a bus protocol and extract operation information, and the logic buffer portion 212 includes a plurality of buffer logics and is configured to store information sent from the bus data logic analysis portion 211, buffer the information through corresponding buffer logics, and send the information to a unit at a subsequent stage (here, the parallel interface controller unit 220). In the data reading operation, the data of the parallel interface controller unit 220 may also be buffered by corresponding buffer logic under the control of the MCU core 100 and then sent to the bus data logic analysis portion 211, and further sent to the MCU core 100 through the system bus 110.
The form of data sent from the system bus 110 may include address, data and control, and each type of data may be buffered by a corresponding logic buffer and output to the parallel interface controller unit 220. The buffering logic provided in the logic buffer portion 212 may include address logic buffers, data logic buffers, and control logic buffers. The address logic buffer is configured to buffer address information, and may specifically include address information of a register corresponding to the parallel interface to be configured in the parallel interface controller unit 220, and an address of each register is mapped to a storage address space accessible by the MCU core 100, so that configuration information, read/write control information, and data for the parallel interface may be transferred by configuring a set of registers corresponding to the parallel interface to be configured. Through address logic buffering, address information of a corresponding register in the parallel interface controller unit 220 is saved, and the address information may be transmitted to the parallel interface controller unit 220 under the control of the MCU core 100. The data logic buffer is used for buffering data information, for example, when data writing operation is performed, the bus interface unit 210 sends data to be transmitted through the parallel interface from the system bus 110 to the data logic buffer for storage, and the data is further sent to the parallel interface controller unit 220 under the control of the MCU core 100, and then sent to an external device through the parallel channel interface. In a read data operation, the data logic buffer may hold data to be transmitted to the MCU core 100 from the parallel interface controller unit 220, and upload to the system bus through the bus data logic analyzing portion 211 under the control of the MCU core 100. The control logic buffer is used for buffering the control information sent on the system bus 110, and may store the control information sent by the bus data logic analysis portion 211, and send the buffered control information to the parallel interface controller unit 220. The control information is used to control a read operation or a write operation performed through the parallel interface.
Fig. 3 is a schematic structural diagram of a parallel interface controller unit according to an embodiment of the present invention. Referring to fig. 3, in the above system on chip 10, in an embodiment, the parallel interface that is built in a chip by using the programmable logic resources of the FPGA module 200 includes a parallel interface controller unit 220 connected to the bus interface unit 210, where the parallel interface controller unit 220 includes a plurality of registers, an address of each register is mapped to an address storage space of the MCU core 100, and the configuration information about the parallel channel of the parallel interface, which is acquired by the bus interface unit 210, is mapped to a corresponding register for storage. Thus, the parallel interface controller unit 220 may map the functions of data read/write, channel number configuration, channel data width configuration, and the like for each parallel interface to corresponding registers, such as the parallel port control register, the parallel port status register, the parallel port configuration register, the parallel port input register (storing data read from an external device), the parallel port output register (storing data written to an external device), and the clock division register in fig. 3. Through the bus interface unit 210, the register corresponding to each parallel interface is mapped to the address storage space of the MCU core 100, and then the read, write, channel number configuration, channel data width configuration, state control, and control of clock division of the parallel interface may be performed under the control of the MCU core 100.
Specifically, the parallel interface controller unit 220 includes a register read/write sequential logic, which receives address information of the register output by the bus interface unit 210 to select a corresponding register, and also receives configuration information about the parallel channel interface and maps the configuration information to the register of a corresponding address. The register read-write sequential logic may be reset by a reset signal connected to MCU core 100.
The parallel interface controller unit 220 includes a parallel port configuration register (e.g., parallel port configuration registers (1-n) in fig. 3), which corresponds to each parallel channel in the parallel interface and is used to store information of the data width allocated to the corresponding parallel channel by the MCU core 100. For each parallel channel of each parallel interface of the system on chip 10, a parallel port configuration register is corresponding to the parallel interface controller unit 220. For the same parallel interface, the number of the configured parallel port configuration registers is the number of the parallel channels, that is, the number of the parallel port configuration registers corresponding to the same parallel interface is the number of the parallel channels in the parallel interface. In one embodiment, parallel interface controller unit 220 also includes a dedicated register to store the configured number of parallel channels in the parallel interface. In this embodiment, if the MCU core 100 sends an instruction for configuring the number of parallel channels of the parallel interface through the system bus 110, the parallel port configuration registers of a corresponding number are configured according to the number of channels, and information of the data width is sent for each parallel port configuration register.
The parallel interface controller unit 220 further includes a parallel control register, a parallel state register, a parallel input register, and a parallel output register, which are provided corresponding to each of the parallel channel interfaces (i.e., the parallel channel interface 1, the parallel channel interface 2,. the parallel channel interface n, n is an integer greater than or equal to 2 shown in fig. 1), the parallel control register is configured to store control information when data is read or written through the corresponding parallel channel interface, the parallel state register is configured to store state information of the corresponding parallel channel interface, the parallel output register is configured to store data to be written into the corresponding parallel channel interface, and the parallel input register is configured to store data to be read from the corresponding parallel channel interface. The bus interface unit 210 may map data stored in the parallel port input register of the parallel interface controller unit 220 onto the system bus 110 in a read data operation, and the bus interface module unit 210 may map data of the system bus 110 onto the parallel port output register of the parallel interface controller unit 220 in a write data operation. Specifically, if the MCU core 100 sends a read data command through the system bus 110, the data transmitted from each parallel channel interface of the parallel interface is read through each parallel port input register. If the MCU core 100 sends a write data command through the system bus 110, corresponding data is sent to each parallel channel interface of the parallel interface through each parallel port output register. The parallel interface controller unit 220 receives the instruction and data transmitted by the bus interface unit 210, and maps the data of the bus in corresponding registers through internal register read-write sequential logic, where different registers have different functions, and the register operation can not only control the number of parallel interfaces, the number of parallel channels in each parallel interface, but also control the bit width of the data transmitted by the parallel interfaces at one time.
In order to cooperate with the transmission of parallel data, referring to fig. 3, the parallel interface controller unit 220 further has a clock dividing register (e.g., the clock dividing registers (1-n) in fig. 3) inside, the clock dividing register controls the dividing coefficient (or dividing ratio) of the clock divider (fig. 4) according to the set data rate of the parallel interface transmission, and the output clock dividing coefficient is provided to the next stage unit (the clock generator unit 230 in this embodiment) under the control of the MCU core 100 to generate the divided clock. The clock division register may be disposed corresponding to each of the parallel channel interfaces, and the clock division register is connected to a clock signal of the MCU core 100.
Fig. 4 is a schematic structural diagram of a clock generator unit according to an embodiment of the present invention. Referring to fig. 4, in an embodiment, in the system on chip 10, the parallel interface built in the chip by using the programmable logic resources of the FPGA module 200 includes a clock generator unit 230 connected to the parallel interface controller unit 220, where the clock generator unit 230 is configured to obtain a clock frequency division coefficient output by the parallel interface controller unit 220 and a clock signal of the MCU core 100 to generate a frequency division clock. Specifically, the clock generator unit 230 is connected to a clock signal and a reset signal of the MCU core 100, and further obtains a clock frequency division coefficient generated by a clock frequency division register in the parallel interface controller unit 220, and generates a corresponding frequency division clock through the clock frequency divider, where each of the parallel channel interfaces of the parallel interface performs data communication with an external device of the MCU core 100 according to the frequency division clock. The bus clock provided by the MCU core 100 is divided into frequencies required by parallel port data transmission and sent to the parallel channel interfaces of the corresponding parallel interfaces, and the divided clock is output to the parallel channel interfaces (the parallel channel interfaces may be connected to an input/output interface (I/O) on the FPGA chip through a logic connection line inside the FPGA module 200, and the parallel peripheral of the MCU core 100 is connected to the I/O port), so that the divided clock can drive the clocks of the external devices connected to the parallel interfaces, and the related data exchange is performed under the divided clock.
Fig. 5 is a schematic structural diagram of a data receiving and transmitting unit in an embodiment of the present invention. Referring to fig. 5, in the system on chip 10, the parallel interface built in the chip by using the programmable logic resource of the FPGA module 200 includes a data receiving and sending unit 240 connected to the parallel interface controller unit 220, where the data receiving and sending unit 240 is configured to, under the control of the MCU core 100, process the data output by the parallel interface controller unit 220 into data matching the data width of each parallel channel and the frequency division clock, that is, convert the data transmitted by the parallel interface controller unit 220 into data that can be received by the parallel interface, for example, data with different widths configured according to the parallel interface bit width. The data receiving/transmitting unit 240 includes a register data transceiving parallel port transceiving functional part, which is connected to the MCU reset signal to facilitate reset processing and to the frequency division clock to configure data according to the frequency division clock. The register data transceiving to parallel port transceiving function part may process data received from each parallel channel interface, convert the data into a parallel port receiving value, and send the parallel port receiving value to a corresponding parallel port input register in the parallel interface controller unit 220. The register data transceiving parallel port transceiving functional section may process data (parallel port transmission value) transmitted from each parallel port input register in the parallel interface controller unit 220, and convert the data into data that can be processed by each parallel channel interface in the same parallel interface.
The data transceiver unit 240 may also buffer the data transmitted by the parallel interface controller unit 220 to meet the rate matching requirement of the parallel interface peripheral. The data receiver/transmitter unit 240 is connected to each parallel channel interface of the corresponding parallel interface, and the data receiver/transmitter unit 240 transmits data under the divided clock through the parallel channel interface by setting the data to a format matching the divided clock output from the clock generator unit 230.
FIG. 6 is a flowchart illustrating a system-on-chip configuration parallel interface with an on-chip parallel interface according to an embodiment of the present invention. Referring to fig. 1 to 6, configuring a parallel interface using a system on chip having an on-chip parallel interface of the present embodiment may include, as an example, the following processes:
step one, scanning a system bus 110 of an MCU (microprogrammed control Unit) kernel 100, judging whether the system bus 110 is enabled (can be understood as whether the MCU kernel 100 sends a task aiming at an on-chip parallel interface), if the system bus 110 is not enabled, continuing to execute the step of scanning the system bus 110 until the system bus 100 is enabled, and if the system bus 110 is enabled, executing the step two;
step two, judging whether the initialization of the parallel channel of the on-chip parallel interface is finished, if not, continuing to execute the step of scanning the system bus 110 to obtain a specific configuration command (for example, the specific configuration command comprises the number of the parallel channels, the data width of each parallel channel and the address information of a register used for the configuration) of the parallel channel of the parallel interface of the MCU kernel 100, and after obtaining the corresponding configuration command, dynamically configuring the parallel channel of the parallel interface by utilizing FPGA programmable logic resources according to the configuration command;
in the second step, if the number and data width of the parallel channels have been configured, it may be further determined whether the corresponding clock frequency division initialization is completed for the parallel interface configured for the parallel channel, if the clock frequency division initialization is not completed, the step of scanning the system bus 110 is executed to obtain a configuration instruction (for example, including clock distribution coefficients corresponding to different parallel channels and address information of a register used for the configuration) of the MCU core 100 for the clock frequency division coefficient of each parallel channel, and then the clock frequency division coefficient and the frequency division clock of the parallel channel are set by using the FPGA programmable logic resource according to the configuration instruction, the first step and the second step may be executed by the bus interface unit 210 under the control of the MCU core 100, and in addition, in the application process of the system on chip, if the parallel channel design of the on-chip parallel interface is to be dynamically adjusted, the step one and the step two need to be executed again;
and step three, performing register operation (which can be performed by the parallel interface controller unit 220 under the control of the MCU core 100) according to the type of operation to be performed (such as parallel port configuration, clock frequency division configuration, read/write data configuration, etc.).
After the third step, the FPGA programmable logic resource may be subsequently used to map the configuration command and data information (i.e. information stored in the register) of the MCU core 100 for the parallel interface into the configuration of the corresponding parallel channel interface, and when the parallel interface is used for communication, the frequency division clock and the corresponding synchronous data processing (executed by the clock generator unit 230 and the data receiver/transmitter unit 240) are generated to transmit the corresponding data and clock from each parallel channel interface to the external device, so that the function of the MCU core 100 of the system-on-chip 10 communicating with the external device can be realized by using the on-chip parallel interface dynamically configured by the above method.
The system on chip with the parallel interfaces in the chip provided by the invention adopts the parallel interfaces arranged in the chip to carry out data transmission, is expected to obtain higher transmission rate, improves the application flexibility of the system on chip, and can dynamically configure the number of the parallel channels of the parallel interfaces and the data width of each parallel channel according to the requirements, thereby being convenient for users to use and meeting the diversified data transmission requirements.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (9)
1. The system on chip with the parallel interfaces on the chip is characterized by comprising an MCU (microprogrammed control Unit) core and an FPGA (field programmable gate array) module which are interacted through a system bus, wherein at least one parallel interface is constructed in the chip by utilizing programmable logic resources of the FPGA module, each parallel interface comprises more than two parallel channels, and the number of the parallel channels and the data width of each parallel channel are dynamically configured through the MCU core; the parallel interface comprises a parallel interface controller unit, the parallel interface controller unit comprises parallel port configuration registers which correspond to each parallel channel and are used for storing information of data width distributed to the corresponding parallel channel by the MCU kernel, and the number of the parallel port configuration registers corresponding to the same parallel interface is the number of the parallel channels in the parallel interface.
2. The system on a chip of claim 1, wherein the parallel interface comprises a bus interface unit connected to the system bus, and the bus interface unit obtains configuration information about the parallel channels sent by the MCU core through the system bus and configures each of the parallel channels through programmable logic resources of the FPGA module.
3. The system on chip of claim 2, wherein the parallel interface controller unit is connected to the bus interface unit, the parallel interface controller unit includes a plurality of registers, an address of each register is mapped to an address storage space of the MCU core, and the configuration information about the parallel channels acquired by the bus interface unit is mapped to a corresponding register for storage.
4. The system on a chip of claim 3, wherein the parallel interface includes a parallel channel interface provided corresponding to each of the parallel channels, each of the parallel channel interfaces communicating with an external device of the MCU core in accordance with a parallel interface protocol, the parallel interface controller unit mapping information stored in each of the registers to configuration information for each of the parallel channel interfaces.
5. The system on a chip of claim 4, wherein the parallel interface controller unit includes register read and write timing logic, the register read and write timing logic receiving address information of the registers output by the bus interface unit to select the corresponding registers, the register read and write timing logic further receiving configuration information about the parallel channels and mapping to the registers of the corresponding addresses.
6. The system on a chip of claim 4, wherein the parallel interface controller unit further includes a parallel port control register corresponding to each of the parallel channels in the parallel interface, a parallel port status register for storing control information when data is read from or written to the corresponding parallel channel interface, a parallel port input register for storing data read from the corresponding parallel channel interface, and a parallel port output register for storing data to be written to the corresponding parallel channel interface.
7. The system on a chip of claim 4, wherein the parallel interface controller unit further comprises a clock divide register corresponding to each of the parallel channels within the parallel interface, the clock divide register being connected to a clock signal of the MCU core and being used to store a clock divide coefficient for the corresponding parallel channel interface.
8. The system on a chip of claim 7, wherein the parallel interface comprises a clock generator unit connected to the parallel interface controller unit, the clock generator unit configured to obtain a clock division coefficient output by the parallel interface controller unit and a clock signal of the MCU core, and generate a divided clock.
9. The system on a chip of claim 8, wherein the parallel interface includes a data receiving transmitter unit connected to the parallel interface controller unit, the data receiving transmitter unit for acquiring data from the parallel interface controller unit and processing the data into data matching a data width of each of the parallel channels and the divided clock under control of the MCU core.
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