CN113703843B - Register data processing method, device and memory - Google Patents
Register data processing method, device and memory Download PDFInfo
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- CN113703843B CN113703843B CN202111124071.9A CN202111124071A CN113703843B CN 113703843 B CN113703843 B CN 113703843B CN 202111124071 A CN202111124071 A CN 202111124071A CN 113703843 B CN113703843 B CN 113703843B
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The embodiment of the invention provides a register data processing method, a device and a memory, wherein after receiving a first data message sent by an upper computer through a service data channel, FPGA equipment analyzes the first data message to obtain register operation information contained in the first data message. And further performing read-write operation on the register according to the register operation information, and transmitting the read target data to the upper computer, thereby realizing the read-write operation on the register data. Compared with the prior art that a single channel transmits a message for processing the register data, the method and the device have the advantages that the channel is multiplexed through the service data and the register operation data, so that the utilization rate of channel resources is improved, the interface resources of the FPGA are saved, and the development work of an upper computer is prevented from being increased.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method, an apparatus, and a memory for processing register data.
Background
Currently, a field programmable gate array (Field Programmable Gate Array, abbreviated as FPGA) is widely applied to various industries, and has the advantages of high programmable flexibility, short development period, high parallel computing efficiency and the like.
The function of an internal register of the FPGA is one of important functions of development and application, is interconnected with other devices, can effectively obtain real information of the reaction device, and can also control the function realization of the device, and the data processing of the register is usually realized by connecting an upper computer.
In the prior art, the upper computer is generally connected with the FPGA through an independent transmission channel so as to read and write the register data of the upper computer, but the independent channel wastes the interface resource of the FPGA and causes the development work of the upper computer to be increased.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a method, an apparatus, and a memory for processing register data, so as to improve the problems existing in the prior art.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides a register data processing method, including:
receiving a first data message sent by an upper computer through a service data channel;
analyzing the first data message to obtain register operation information contained in the first data message;
and performing read-write operation on the register according to the register operation information.
With reference to the first aspect, in a first possible implementation manner, the step of parsing the first data packet to obtain register operation information included in the first data packet includes:
analyzing a first target field of the first data message to obtain the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
With reference to the first aspect, in a second possible implementation manner, the step of performing a read-write operation on the register according to the register operation information includes:
judging the operation type of the register operation information;
if the operation type is a reading operation, reading target data of the register and sending the target data to an upper computer;
and if the operation type is a writing operation, writing the writing data corresponding to the writing operation into the register.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the register operation information further includes an operation address, and the step of reading target data of the register and sending the target data to an upper computer includes:
when the operation address is a target reading address, reading target data corresponding to the register according to the target reading address;
sending a second data message to the upper computer, wherein a second target field of the second data message stores the target data;
the step of writing the write data corresponding to the write operation into the register includes:
and when the operation address is a target write address, writing the write data into the register according to the target write address.
In a second aspect, an embodiment of the present invention provides another register data processing method, including:
generating a first data message containing register operation information, wherein the register operation information is operation information for performing read-write operation on a register;
and sending the first data message to a register through a service data channel.
With reference to the second aspect, in a first possible implementation manner, the generating a first data packet including register operation information includes:
generating a first data message containing a first target field according to the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
With reference to the second aspect, in a second possible implementation manner, the method further includes:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message stores target data of the register corresponding to a reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
In a third aspect, an embodiment of the present invention provides a register data processing apparatus, including:
the receiving module is used for receiving a first data message sent by the upper computer through the service data channel, and the register operation information is operation information for performing read-write operation on the register;
the analysis module is used for analyzing the first data message to obtain register operation information contained in the first data message;
and the processing module is used for performing read-write operation on the register according to the register operation information.
With reference to the third aspect, in a first possible implementation manner, the processing module is further configured to;
judging the operation type of the register operation information;
and sending a second data message to the upper computer, wherein a second target field of the second data message stores target data of the register corresponding to the reading operation.
In a fourth aspect, an embodiment of the present invention provides another register data processing apparatus, including:
the control module is used for generating a first data message containing register operation information, wherein the register operation information is operation information for performing read-write operation on a register;
and the sending module is used for sending the first data message to the register through the service data channel.
With reference to the fourth aspect, in a possible implementation manner, the control module is further configured to:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message is used for storing target data of the register corresponding to a reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
In a fifth aspect, an embodiment of the present invention provides a memory, where a computer program is stored, where the computer program is executed to implement a register data processing method according to any one of the possible implementation manners of the first aspect or the second aspect.
According to the register data processing method, device and memory provided by the embodiment of the invention, after the FPGA equipment receives the first data message sent by the upper computer through the service data channel, the first data message is analyzed, and register operation information contained in the first data message is obtained. And further performing read-write operation on the register according to the register operation information, and transmitting the read target data to the upper computer, thereby realizing the read-write operation on the register data. The embodiment of the invention has the beneficial effects that: compared with the prior art that a single channel transmits a message for processing the register data, the method and the device have the advantages that the channel is multiplexed through the service data and the register operation data, so that the utilization rate of channel resources is improved, the interface resources of the FPGA are saved, and the development work of an upper computer is prevented from being increased.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of data transmission between a host computer and an FPGA device in the prior art;
FIG. 2 is a schematic diagram of data transmission between an upper computer and an FPGA device according to the present invention;
FIG. 3 is a flowchart of a register data processing method according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
fig. 10 is a signaling interaction schematic diagram of an upper computer and FPGA equipment according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a functional module of a register data processing apparatus according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a functional block diagram of another register data processing apparatus according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
Fig. 1 is a diagram showing data interaction between a host computer 10 and an FPGA device 20 according to the prior art.
Optionally, the specific type of the upper computer 10 is not limited, and may be set according to actual application requirements, and may be a computer or a single chip microcomputer that directly sends an operation instruction. For example, in an alternative example, the host computer 10 may be: desktop computers, smart phones, tablets, notebooks, etc.
Referring to fig. 1, in the prior art: when processing the service data, the upper computer 10 and the FPGA device 20 are connected by a service data channel, so as to transmit the related message of the service data information to the service data processing unit 21; when processing register data, a separate transmission channel is usually connected between the upper computer 10 and the FPGA device 20, so as to transmit the relevant message of the register data processing information to the register 22.
For example, when the FPGA is applied in a mass spectrometer, a service data channel is used to transmit ion intensity data collected by an Analog-to-DigitalConverter, ADC; the register data processing information is transferred using a separate transfer channel to enable writing configuration parameters or control commands to registers or reading status information (e.g., scan abort information).
However, in the scheme shown in fig. 1, when the register data of the FPGA device 20 is processed, since a separate transmission channel is used to connect the upper computer 10, the FPGA device 20 needs to separately design an interface. For example, in the prior art, the upper computer 10 performs read-write control and information storage on the resources of the block random access memory (Block Random Access Memory, BRAM) or the ready random access memory (RandomAccess Memory, RAM) such as the static random access memory (Static Random Access Memory, SRAM) inside the FPGA through a separate channel, which results in wasting the interface resources of the FPGA and increasing the development work of the upper computer 10. In addition, if the channel for transmitting the read-write control information is a high-speed channel, for example, when a gigabit high-speed port is used, the data polled per second is less than 1kb, which causes the waste of high-speed channel resources; in the case of a low-speed channel, such as a universal asynchronous receiver Transmitter (UniversalAsynchronous Receiver/Transmitter, UART), for a scenario requiring relatively large amount of polling status information, the effect of real-time monitoring may not be achieved because of the low-speed channel's poor timeliness.
Therefore, in order to solve the above technical problems, the core solution idea of the register data processing method provided by the present invention is specifically that fig. 2 is a data interaction diagram of the upper computer 10 and the FPGA device 20 in the present invention, see fig. 2:
the upper computer 10 and the FPGA equipment 20 are connected through a service data channel, and related messages of service data information and register operation information are transmitted through the service data channel.
Thereby realizing channel multiplexing, improving the utilization rate of channel resources, saving the interface resources of the FPGA equipment 20 and avoiding the increase of development work of the upper computer 10.
It will be appreciated that the configuration shown in fig. 1 and 2 is illustrative only and that FPGA device 20 may include more or fewer components than those shown in fig. 1 and 2 or have a different configuration and is not limited in this regard.
Based on the above data interaction diagram of the upper computer 10 and the FPGA device 20 in fig. 2, an embodiment of the present invention provides a possible implementation manner to implement a read-write operation on register data, and the embodiment of the present application is described below by taking the FPGA device 20 as an execution body, specifically, fig. 3 is a schematic flow diagram of a register data processing method provided in the embodiment of the present invention, and referring to fig. 3, the method includes the steps of:
step S300, a first data message sent by an upper computer through a service data channel is received.
It should be noted that, the service data channel is a channel for transmitting data at a high speed commonly used by the FPGA device 20, related messages of service data information and register operation information are all transmitted through the service data channel, and the first data message includes service data information and/or register operation information, which may have the following three cases:
case 1: the first data message only comprises service data information;
case 2: the first data message only contains register operation information;
case 3: the first data message contains service data information and register operation information.
In an alternative example, the traffic data channel may be a high speed channel. Such as ethernet channels or Peripheral Component Interconnect Express (PCIE) standard PeripheralComponent Interconnect Express, PCIE express channels. It should be noted that this example is only an example, and the specific implementation manner is not limited herein.
Step S301, parse the first data packet to obtain register operation information included in the first data packet.
It can be understood that the specific parsing mode is not limited, and any one of the existing message parsing methods can be adopted, or when a new or improved protocol is adopted, a parsing scheme meeting the requirements of the protocol is adopted.
Step S302, performing read-write operation on the register according to the register operation information.
According to the register data processing method provided by the embodiment of the invention, after the FPGA equipment receives the first data message sent by the upper computer through the service data channel, the first data message is analyzed, and the register operation information contained in the first data message is obtained. And further, according to the register operation information, the register is subjected to read-write operation, so that the read-write operation of the register data is realized. The invention multiplexes the channel through the service data and the register operation data, improves the utilization rate of channel resources, saves the interface resources of the FPGA and avoids the increase of development work of an upper computer.
Accordingly, the register operation information includes an operation type, an operation address, and write data.
With continued reference to fig. 2, it should be noted that the register 22 may be custom designed according to requirements, and is formed by designing slice LUTs logic resources inside the FPGA device 20, and the number of the registers 22 and the bit width of the stored data may be custom defined according to actual requirements, and the specific design may be implemented using verilog language programming. The number of required registers is large, the data bit width is large, and the required slice LUTs logic resources are large. And the portability and the modification flexibility of the custom design register are high, and the custom design register can be transplanted to other devices for use after the adaptive modification.
It is understood that registers 22 include readable and writable registers and read-only registers. The readable and writable register is characterized in that it can be either read or written. Read-only registers are characterized by only reading register data and not writing.
It will be appreciated that reading data from a readable and writable register is typically used to determine whether the write data is normally written. Reading data from a read-only register is typically querying for certain information states, such as: the FPGA device 20 is connected with a fan, the upper computer 10 needs to know the working state of the fan, send a first data message to the FPGA device 20, read the information of the register related to the fan to obtain the working state of the register, and send the read information back to the upper computer 10. It should be noted that this example is only an example, and the specific implementation manner is not limited herein.
The write operation is generally to perform corresponding signal configuration or function control on the inside, for example: the FPGA device 20 is connected with a digital display tube, the upper computer 10 can send a first data message to the FPGA device 20 to control the digital display tube to display a corresponding number, or the FPGA device 20 is connected with a switch, and the upper computer 10 can send the first data message to the FPGA device 20 to control the on-off state of the switch. It should be noted that this example is only an example, and the specific implementation manner is not limited herein.
Further, in the case that the first data packet includes register operation information, in order to obtain the register operation information in the packet, with respect to step S301 in fig. 3, a possible implementation manner is provided in the embodiment of the present invention to obtain the register operation information, specifically, on the basis of fig. 3, fig. 4 is a schematic flow diagram of another register data processing method provided in the embodiment of the present invention, referring to fig. 4, in which the sub-steps in step S301 include:
step S301-1, analyzing a first target field of a first data message to obtain register operation information.
It is understood that the first target field is used to store register operation information corresponding to a read/write operation. Taking a PCIE high-speed channel as an example, for an original service data packet, the first target field may be obtained by multiplexing a custom field of the packet, for example, the first target field is a certain 5 consecutive bytes in the first data packet, where the first byte represents an operation type, 1 is a write operation, 2 is a read operation, and the other is a no operation; the second and third bytes represent the operation address, the bit width of which is 16 bits; the fourth and fifth bytes are writing data, and the data bit width is 16 bits. It should be noted that this example is only an example, and the specific implementation manner is not limited herein.
Optionally, in the case that the first data packet includes register operation information, in order to read data of a register or write data into the register, for step S302 in fig. 3, a possible implementation manner is provided in an embodiment of the present invention to implement reading and writing of register data, specifically, on the basis of fig. 3, fig. 5 is a schematic flow diagram of another register data processing method provided in the embodiment of the present invention, referring to fig. 5, and sub-steps of step S302 include:
step S302-1, judging the operation type of the register operation information.
In step S302-2, if the operation type is a read operation, the target data of the register is read and sent to the host computer.
In one possible implementation, when the operation type is a read operation, the write data of the register operation information is ignored, and the write data portion of the first target field is typically filled with all 0 s.
Step S302-3, if the operation type is a write operation, writing the write data corresponding to the write operation into the register.
It will be appreciated that when the operation type is no operation, no operation is performed on the register data.
Optionally, in order to read the target data of the register corresponding to the operation address or write the target data into the register corresponding to the operation address, for step S302-2 and step S302-3 in fig. 5, a possible implementation manner is provided in the embodiment of the present invention to achieve the above purpose, specifically, on the basis of fig. 5, fig. 6 is a schematic flow diagram of another register data processing method provided in the embodiment of the present invention, referring to fig. 6, the substeps of step S302-2 include:
and step S302-21, when the operation address is a target reading address, reading target data corresponding to the register according to the target reading address.
Step S302-22, a second data message is sent to the upper computer.
Wherein the second target field of the second data packet is used for storing target data.
Taking PCIE high speed channel as an example, for its original service data packet, the second target field may be obtained by multiplexing the custom field of the packet, for example, multiplexing the first byte and the second byte of the custom field as the second target field, so as to store the target data. It should be noted that this example is only an example, and the specific implementation manner is not limited herein.
Substeps of step S302-3, comprising:
step S302-31, when the operation address is the target write address, writing the write data into the register according to the target write address.
It will be appreciated that the operation addresses are of both the target read address and the target write address types. When the operation type is a read operation, the operation address is a target read address, and when the operation type is a write operation, the operation address is a target write address.
According to the register data processing method provided by the embodiment of the invention, after the FPGA equipment receives the first data message sent by the upper computer through the service data channel, the first data message is analyzed, and the register operation information contained in the first data message is obtained. And further performing read-write operation on the register according to the register operation information, and transmitting the read target data to the upper computer, thereby realizing the read-write operation on the register data. Compared with the prior art that a single channel transmits a message for processing the register data, the method and the device have the advantages that the channel is multiplexed through the service data and the register operation data, so that the utilization rate of channel resources is improved, the interface resources of the FPGA are saved, and the development work of an upper computer is prevented from being increased.
Referring to the above, the execution method of the upper computer 10 in fig. 2 is described below. The present invention provides a possible implementation manner to realize that the upper computer 10 controls the register to perform read-write operation, specifically, fig. 7 is a schematic flow chart of another register data processing method provided in the embodiment of the present invention, referring to fig. 7, the method steps include:
step S400, a first data message containing register operation information is generated.
It is understood that the register operation information is operation information for performing read-write operation on the register.
Step S401, send the first data packet to the register 22 through the service data channel.
According to the register data processing method provided by the embodiment of the invention, after the upper computer generates the first data message containing the register operation information, the upper computer sends the first data message to the register through the service data channel so as to realize the read-write operation of the upper computer control register. Compared with the prior art that a single channel transmits a message for processing the register data, the method and the device have the advantages that the channel is multiplexed through the service data and the register operation data, so that the utilization rate of channel resources is improved, the interface resources of the FPGA are saved, and the development work of an upper computer is prevented from being increased.
Further, in order to put register operation information into a certain field of the first data packet, for step S400 in fig. 7, a possible implementation manner is provided in the embodiment of the present invention, specifically, fig. 8 is a schematic flow diagram of another register data processing method provided in the embodiment of the present invention on the basis of fig. 7, referring to fig. 8, and the substeps of step S400 include:
step S400-1, a first data message containing a first target field is generated according to the register operation information.
It is understood that the first target field is for storing register operation information corresponding to a read-write operation.
Further, in order to obtain the target data of the read register, an embodiment of the present invention provides a possible implementation manner, and specifically, on the basis of fig. 7, fig. 9 is a schematic flow chart of another register data processing method provided by the embodiment of the present invention, referring to fig. 9, after step S401, the steps further include:
step S402, receiving a second data message sent by the register through the service data channel.
It will be appreciated that the second destination field of the second data packet stores the destination data of the register corresponding to the read operation.
Step S403, analyzing the second target field of the second data packet to obtain the target data of the register.
According to the register data processing method provided by the embodiment of the invention, after the upper computer generates the first data message containing the register operation information, the upper computer sends the first data message to the register through the service data channel and receives the read register target data, so that the upper computer can control the register to perform read-write operation. Compared with the prior art that a single channel transmits a message for processing the register data, the method and the device have the advantages that the channel is multiplexed through the service data and the register operation data, so that the utilization rate of channel resources is improved, the interface resources of the FPGA are saved, and the development work of an upper computer is prevented from being increased.
Optionally, in order to better illustrate the implementation manner of the present application, taking the foregoing read-write control of the register data of the FPGA device 20 by the upper computer 10 in fig. 2 as an example in combination with the foregoing flow of the method executed by the upper computer 10 and the FPGA device 20, an implementation manner of interaction between the upper computer 10 and the FPGA device 20 is provided, specifically, fig. 10 is a schematic signaling interaction diagram of the upper computer 10 and the FPGA device 20, and referring to fig. 10, the flow includes:
step 1, an upper computer generates a first data message containing register operation information;
step 2, the upper computer sends a first data message to the FPGA equipment;
step 3, the FPGA equipment analyzes a first target field of the first data message to obtain register operation information;
step 4, the FPGA equipment determines the operation type of the register operation information;
step 5, if the reading operation is performed, searching a target reading address, reading target data, generating a second data message according to the target data, and sending the second data message to the upper computer; the upper computer analyzes a second target field of the second data message to obtain target data;
and step 6, if the write operation is performed, searching a target write address, and writing the write data into the register.
In connection with fig. 11, the embodiment of the present invention further provides a register data processing apparatus 500, which can be applied to the FPGA device 20 described above. It should be noted that the basic principle and the technical effects thereof are the same as those of the corresponding method embodiments, and for brevity, reference may be made to the corresponding contents of the method embodiments. The register data processing apparatus may include a receiving module 510, a parsing module 520, and a processing module 530.
The receiving module 510 is configured to receive a first data packet sent by the upper computer through the service data channel.
In this embodiment, the receiving module 510 may be configured to perform step S300 shown in fig. 3.
The parsing module 520 is configured to parse the first data packet to obtain register operation information included in the first data packet.
In this embodiment, the parsing module 520 may be used to perform step S301 shown in fig. 3, and the related content of the parsing module 520 may refer to the foregoing detailed description of step S301.
And the processing module 530 is configured to perform read-write operation on the register according to the register operation information.
In this embodiment, the processing module 530 may be configured to perform step S302 shown in fig. 3, and the related content of the parsing module may refer to the foregoing detailed description of step S302.
Further, the processing module 530 of the register data processing apparatus 500 is further configured to:
judging the operation type of the register operation information;
and sending the second data message to the upper computer.
The second target field of the second data packet stores target data of a register corresponding to the read operation.
In connection with fig. 12, another register data processing apparatus 600 is provided in the embodiment of the present invention, which can be applied to the above-mentioned upper computer 10. It should be noted that the basic principle and the technical effects thereof are the same as those of the corresponding method embodiments, and for brevity, reference may be made to the corresponding contents of the method embodiments. The register data processing apparatus may include a control module 610 and a transmitting module 620.
The control module 610 is configured to generate a first data packet including register operation information.
The register operation information is operation information for performing read-write operation on the register.
The sending module 620 is configured to send the first data packet to the register through the service data channel.
Further, the control module 610 of the register data processing apparatus 600 is further configured to:
receiving a second data message sent by the register through a service data channel;
and analyzing a second target field of the second data message to obtain target data of the register.
The second target field of the second data packet is used for storing target data of a register corresponding to the read operation.
The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (DigitalDingnal Processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a System-on-a-Chip (SoC for short).
Further, based on the above register data processing method, in the embodiment of the present application, there is further provided a memory, on which a computer program is stored, which is executed by a processor when executed, to implement the above method embodiment.
Alternatively, when the memory is provided in the FPGA device in the above embodiment, it may be used to store the program corresponding to the respective method flows in fig. 3 to 6 to achieve the corresponding effects. When the memory is disposed in the upper computer in the above embodiment, it may be used to store the program corresponding to the corresponding method flows in fig. 7 to fig. 9, so as to achieve the corresponding effects.
In summary, the method, device and memory for processing register data provided in the embodiments of the present invention may perform read-write control on register data through an upper computer, where the method includes: after receiving a first data message sent by an upper computer through a service data channel, the FPGA equipment analyzes the first data message to obtain register operation information contained in the first data message. And further, according to the register operation information, the register is subjected to read-write operation, so that the read-write operation of the register data is realized. Compared with the prior art that a single channel transmits a message for processing the register data, the method and the device have the advantages that the channel is multiplexed through the service data and the register operation data, so that the utilization rate of channel resources is improved, the interface resources of the FPGA are saved, and the development work of an upper computer is prevented from being increased.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The register data processing method is characterized by being applied to FPGA equipment, wherein the FPGA equipment and an upper computer are communicated through a service data channel, and the FPGA equipment comprises a register; the method comprises the following steps:
receiving a first data message sent by the upper computer through a service data channel;
analyzing the first data message to obtain register operation information contained in the first data message; the register operation information comprises an operation type and write-in data;
if the operation type is a read operation and the write data is all 0, reading target data of the register and sending the target data to the upper computer;
and if the operation type is a write operation, writing the write data into the register.
2. The method of claim 1, wherein the step of parsing the first data message to obtain register operation information included in the first data message comprises:
analyzing a first target field of the first data message to obtain the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
3. The method of claim 1, wherein the register operation information further includes an operation address, and the step of reading target data of the register and transmitting the target data to an upper computer includes:
when the operation address is a target reading address, reading target data corresponding to the register according to the target reading address;
sending a second data message to the upper computer, wherein a second target field of the second data message stores the target data;
the step of writing the write data corresponding to the write operation into the register includes:
and when the operation address is a target write address, writing the write data into the register according to the target write address.
4. The register data processing method is characterized by being applied to an upper computer, wherein the upper computer is communicated with FPGA equipment through a service data channel, and the FPGA equipment comprises a register; the method comprises the following steps:
generating a first data message containing register operation information, wherein the register operation information comprises an operation type and write-in data;
sending the first data message to the FPGA equipment through a service data channel so that the FPGA equipment analyzes the first data message to obtain the register operation information; when the operation type is a reading operation and the writing data is all 0, the FPGA equipment reads target data of the register and sends the target data to the upper computer; and when the operation type is a write operation, the FPGA equipment writes the write data into the register.
5. The method of claim 4, wherein generating the first data message containing register operation information comprises:
generating a first data message containing a first target field according to the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
6. The method of claim 4, wherein the method further comprises:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message is used for storing target data of the register corresponding to a reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
7. The register data processing device is characterized by being applied to FPGA equipment, wherein the FPGA equipment and an upper computer are communicated through a service data channel, and the FPGA equipment comprises a register; the device comprises:
the receiving module is used for receiving a first data message sent by the upper computer through a service data channel;
the analysis module is used for analyzing the first data message to obtain register operation information contained in the first data message; the register operation information comprises an operation type and write-in data;
the processing module is used for reading target data of the register and sending the target data to the upper computer when the operation type is a reading operation and the writing data is all 0;
and the processing module is also used for writing the write data into the register when the operation type is write operation.
8. The register data processing device is characterized by being applied to an upper computer, wherein the upper computer is communicated with FPGA equipment through a service data channel, and the FPGA equipment comprises a register; the device comprises:
the control module is used for generating a first data message containing register operation information, wherein the register operation information comprises an operation type and write-in data;
the sending module is used for sending the first data message to the FPGA equipment through a service data channel so that the FPGA equipment analyzes the first data message to obtain the register operation information; when the operation type is a reading operation and the writing data is all 0, the FPGA equipment reads target data of the register and sends the target data to the upper computer; and when the operation type is a write operation, the FPGA equipment writes the write data into the register.
9. The apparatus of claim 8, wherein the control module is further to:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message is used for storing target data of the register corresponding to a reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
10. A memory having stored thereon a computer program which when executed implements the register data processing method of any of the preceding method claims 1-3 or the register data processing method of any of the preceding claims 4-6.
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| CN114201421B (en) * | 2022-02-17 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Data stream processing method, storage control node and readable storage medium |
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