CN115470163A - Control method, control device, control equipment and storage medium for DMA transmission - Google Patents
Control method, control device, control equipment and storage medium for DMA transmission Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The application relates to the technical field of chip data transmission, and particularly discloses a control method, a control device, control equipment and a storage medium for DMA transmission. The multichannel DMA controller can process a plurality of external equipment requests at one time, does not need to be initialized and configured once again in each transmission, optimizes the area utilization condition of the DMA controller, can transmit a large amount of data more quickly, obviously improves the data transmission efficiency of a chip, and further optimizes the performance of a chip system.
Description
Technical Field
The present application relates to the field of chip data transmission technologies, and in particular, to a method, a device, and a storage medium for controlling DMA transmission.
Background
Direct Memory Access (DMA) is a high-speed transmission operation that allows data to be directly read and written between an external device and a Memory, and between the Memory and the Memory, and allows hardware devices of different speeds to communicate without relying on a large amount of interrupt load of a Central Processing Unit (CPU). Otherwise, the CPU needs to copy each piece of data from the source to the register and then write them back to the new place again. During this time, the CPU cannot perform other tasks. DMA transfers copy data from one address space to another, requiring the CPU to initiate the transfer, which itself is performed and completed by the DMA controller. When the DMA executes the transmission task, the CPU can execute other tasks, and therefore the delay of the CPU task is avoided to a certain extent.
FIG. 1 is a diagram of DMA data transfer.
As shown in fig. 1, since the DMA controller 101 needs to directly manage the bus between the peripheral device 102 and the local memory 103 when implementing the DMA transfer, the CPU 104 gives the bus control right to the DMA controller 101 before the DMA transfer, and the DMA controller 101 returns the bus control right to the CPU 104 immediately after the DMA transfer is finished. Therefore, a complete DMA transfer process must go through 4 steps of DMA request, DMA response, DMA transfer and DMA ending. Each time a DMA transfer is performed, the CPU 104 needs to issue a transfer command to the DMA controller 101 to initiate the DMA transfer (notify the DMA controller 101 of the transceiving address and give the DMA controller 101 the bus control right), receive the transfer completion information fed back by the DMA controller 101, and check whether the data transferred this time is correct.
With the high-speed development of the chip industry, the number of external devices and input/output ports which can be mounted on a system is increased, and the single-channel DMA transmission can only carry out data transmission on a pair of master and slave devices at a time, which cannot meet the requirements of people on the performance of the chip system.
Improving the DMA transfer efficiency is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a control method, a control device, control equipment and a storage medium for DMA transmission, which are used for improving the DMA transmission efficiency and optimizing the performance of a chip system.
In order to solve the above technical problem, the present application provides a DMA transfer control method, which is based on a DMA controller, and includes:
after receiving the channel enabling signal, acquiring the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel;
executing each transmission task in sequence according to each corresponding relation;
and after each transmission task is executed, sending feedback information to a local CPU.
Optionally, the sequentially executing each transmission task according to each corresponding relationship specifically includes:
determining a current working data channel;
processing a plurality of transmission tasks corresponding to the current working data channel in a time-sharing manner by using a multiplexer;
and switching the next data channel into the current working data channel, and returning to the step of processing a plurality of transmission tasks corresponding to the current working data channel by utilizing a multiplexer in a time-sharing manner until all the transmission tasks are completed.
Optionally, according to each corresponding relationship, each transmission task is sequentially executed, specifically:
and executing each transmission task in sequence according to the preset priority of each data channel and each corresponding relation.
Optionally, before executing the transmission task, the method further includes:
and controlling a peripheral bus connected with the external equipment and a high-level high-performance bus connected with the local CPU to carry out control signal synchronization according to the clock frequency of the external equipment corresponding to the transmission task.
Optionally, the executing the transmission task specifically includes:
and executing the transmission task by adopting a chain transmission mode.
Optionally, the executing the transmission task specifically includes:
and in the process of transmitting the source data of the transmission task to the destination end, caching the source data by adopting a cache space corresponding to the data channel.
Optionally, the buffer space is a FIFO space with a preset size.
In order to solve the above technical problem, the present application further provides a DMA transfer control method, which includes, based on a CPU:
when a transmission requirement between external equipment and a local memory is generated, generating a transmission task corresponding to the address of the external equipment and the address of the local memory;
enabling a DMA controller, and distributing a corresponding data channel for each transmission task so as to sequentially execute each transmission task through the DMA controller;
and after receiving feedback information of the DMA controller that each transmission task is executed completely, executing a checking process of the data written in the local memory.
In order to solve the above technical problem, the present application further provides a DMA transfer control device, which is based on a DMA controller, and includes:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel after receiving a channel enabling signal;
a transmission unit, configured to sequentially execute each transmission task according to each correspondence;
and the feedback unit is used for sending feedback information to the local CPU after the execution of each transmission task is finished.
In order to solve the above technical problem, the present application further provides a DMA transfer control apparatus, which includes, based on a CPU:
the device comprises a generating unit, a processing unit and a processing unit, wherein the generating unit is used for generating a transmission task corresponding to the address of the external equipment and the address of the local memory when a transmission requirement between the external equipment and the local memory is generated;
the distribution unit is used for enabling the DMA controller and distributing corresponding data channels to the transmission tasks so as to sequentially execute the transmission tasks through the DMA controller;
and the checking unit is used for executing a checking process of the data written in the local memory after receiving the feedback information of the DMA controller that the execution of each transmission task is finished.
In order to solve the above technical problem, the present application further provides a DMA transfer control device, including:
a memory for storing a computer program;
a processor for executing the computer program, wherein the computer program, when executed by the processor, implements the steps of the DMA transfer control method according to any one of the above.
In order to solve the above technical problem, the present application further provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the DMA transfer control method according to any one of the above aspects.
The DMA transmission control method is realized based on a DMA controller, after a channel enabling signal is received, the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel is obtained, then each transmission task is executed in sequence according to the corresponding relation, and after each transmission task is executed, feedback information is sent to a local CPU. The DMA transmission control method provided by the application realizes a multi-channel DMA controller, can process a plurality of external equipment requests at one time, does not need to initialize and configure the DMA controller once again in each transmission, optimizes the area utilization condition of the DMA controller, can transmit a large amount of data more quickly, obviously improves the data transmission efficiency of a chip, and further optimizes the performance of a chip system.
The present application further provides a control device, a control device and a storage medium for DMA transmission, which have the above beneficial effects and are not described herein again.
Drawings
In order to clearly illustrate the embodiments or technical solutions of the present application, the drawings used in the embodiments or technical solutions of the present application will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram of DMA data transfer;
fig. 2 is a flowchart of a DMA transfer control method according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a DMA transfer control apparatus according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a DMA transfer control device according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a control method, a control device and a storage medium for DMA transmission, which are used for improving the DMA transmission efficiency and optimizing the performance of a chip system.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Example one
Fig. 2 is a flowchart of a DMA transfer control method according to an embodiment of the present application.
As shown in fig. 2, based on a DMA controller, the DMA transfer control method provided in the embodiment of the present application includes:
s201: and after receiving the channel enabling signal, acquiring the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel.
S202: and executing the transmission tasks in sequence according to the corresponding relations.
S203: and after each transmission task is executed, sending feedback information to the local CPU.
It should be noted that the DMA transfer control method provided in the embodiment of the present application may be implemented based on a hardware circuit of an existing DMA controller, or may be implemented by modifying a hardware circuit of an existing DMA controller. Generally, an existing DMA controller has a hardware circuit for implementing a plurality of data channels, which is not developed and applied, and the embodiment of the present application optimizes an area utilization condition of the DMA controller by fully utilizing the hardware circuit of the DMA controller to implement the plurality of data channels.
The DMA controller is also a programmable controller in nature, and the device where the DMA controller is located may be a master device or a slave device, but in the DMA transfer control method provided in the embodiment of the present application, it is not necessary to distinguish whether an external device is a master device or a slave device, and only a source address and a destination address corresponding to each transfer task need to be determined.
The specific configuration of each part function of the DMA controller is realized by configuring the register of the DMA controller. The register configuration module that implements the DMA controller is pre-programmed to centrally handle configuration commands from parties to the DMA controller. The DMA controller comprises a plurality of registers, each register has a unique address, the register configuration module uses the address to address, and the configuration information is written into the corresponding register, so that the initialization of the DMA controller can be completed.
In a specific implementation, for S201, after the configuration, the DMA controller may provide a plurality of data channels, and sequentially execute transmission tasks after receiving initialization of each data channel by the local CPU at one time. For example, n data channels are designed, at least the transmission tasks of n external devices can be responded to simultaneously.
For S202, the DMA controller configures the transceiving addresses of the data channels according to the correspondence between the addresses of the external devices and the local memory addresses in the currently received transmission task, so as to sequentially execute the transmission tasks corresponding to the external devices. The transmission tasks of different data channels can be realized by designing the transmission module in the DMA controller in advance.
In order to ensure the smooth data transmission, a mode control module can be implemented in the DMA controller in advance through programming, so as to monitor the transmission state of the data stream of each data channel in real time after the data channel is enabled and data starts to be transmitted, and control data cache and the like in the data transmission process according to the register configuration information of the DMA controller. I.e. the control of other functional modules in the DMA controller can be implemented in this mode control module.
Since only one transmission task of the external device can be executed at a time, the priority of each data channel can be preset to control the priority of the transmission task, which is convenient for management. Then S202: and sequentially executing each transmission task according to each corresponding relation, specifically: and executing each transmission task in sequence according to the preset priority of each data channel and each corresponding relation. Specifically, each data channel of the DMA controller may be numbered in advance, the numbers are overlapped from 0, the priority of the data channel with the smaller number is higher, and the arbitration module is designed to control the data transmission bus to sequentially start the transmission of each data channel according to the priority of the data channel. The arbitration module realizes the functions that priority polling arbitration is carried out on all data channels before enabling the data channels each time, only the data channel winning arbitration can start to execute a transmission task, and when the data channel with a small number and the data channel with a large number compete at the same time, the data channel with a small number can compete successfully. After the arbitration module selects a certain data channel, the state represented by the data displayed in the register needs to be confirmed, and the transmission task can be continuously executed only when the last transmission task is completely finished.
On this basis, in order to implement priority control on transmission tasks with different degrees of importance, the CPU may prioritize transmission requests received within a preset time period (or after transmission requests occupying all data channels are received cumulatively) according to the degree of importance, and allocate a data channel with a high priority to a transmission task with a higher priority. And the DMA controller controls the data channels to sequentially execute transmission tasks according to the priority sequence.
In order to adapt to the transmission tasks of the external devices with different operating frequencies, the operating frequency of the data bus to be transmitted and received needs to be adjusted to the frequency required by the external devices. Before executing the transmission task, the method for controlling DMA transmission provided in the embodiment of the present application further includes: and according to the clock frequency of the external equipment corresponding to the transmission task, controlling A Peripheral Bus (APB) connected with the external equipment and an Advanced High Performance Bus (AHB) connected with the local CPU to carry out control signal synchronization. Specifically, the synchronization of the control signals under different clock domains between the peripheral bus and the advanced high performance bus can be achieved by designing a synchronization module in the DMA controller in advance using a pulse-level synchronizer, and the synchronization module is controlled by the mode control module.
In the transmission process, in order to improve the data transmission efficiency and avoid data loss, a buffer space is arranged in the DMA controller to buffer the data from the source end to the destination end. For convenience of management, in the method for controlling DMA transfer provided in the embodiment of the present application, the transfer task executed in S202 may specifically be: and in the process of transmitting the source end data of the transmission task to the destination end, caching the source end data by adopting a cache space corresponding to the data channel. The buffer space may be implemented by a First In First Out (FIFO), and a FIFO space with a preset size (e.g. 4 bytes) may be allocated to each data channel in advance. The data caching function can be realized by pre-programming an FIFO control module in the DMA controller, and the FIFO control module is controlled by the mode control module to switch the FIFO states (such as a writing state, a full writing state, a data read-away state and the like).
For step S203, after all transmission tasks allocated by the CPU this time are executed, feedback information is sent to the CPU, so that the CPU checks the correctness of the received data in the local memory and then executes subsequent operations. It is understood that if the DMA controller fails to execute a certain transfer task, the CPU may be fed back the information of the transfer failure.
In order to implement the control method for DMA transfer provided in the embodiments of the present application, verilog code programming may be employed on the DMA controller to implement functions of each part and even functions of each part module.
The method for controlling DMA transmission provided in the embodiment of the present application is implemented based on a DMA controller, and includes obtaining a correspondence between addresses of each external device and local memory addresses in transmission tasks corresponding to each data channel after receiving a channel enable signal, then sequentially executing each transmission task according to the correspondence, and sending feedback information to a local CPU after each transmission task is executed. The DMA transmission control method provided by the embodiment of the application realizes a multi-channel DMA controller, can process a plurality of external equipment requests at one time, does not need to initialize and configure the DMA controller once again in each transmission, optimizes the utilization condition of the area of the DMA controller, can transmit a large amount of data more quickly, obviously improves the data transmission efficiency of a chip, and further optimizes the performance of a chip system.
Example two
On the basis of the above embodiments, since the hardware circuit of the DMA controller is usually provided with a multiplexer, each data selection channel can process a plurality of transmission tasks on the basis of designing a plurality of data channels. Alternatively, the DMA controller is designed to have 4 independent data channels, each of which can execute 4 transfer tasks, that is, the DMA controller can execute 16 transfer tasks after each initialization, and the CPU can respond to 16 peripheral requests at a time.
Then, in S202, each transmission task is sequentially executed, which may specifically include:
determining a current working data channel;
processing a plurality of transmission tasks corresponding to the current working data channel in a time-sharing manner by using a multiplexer;
and switching the next data channel into the current working data channel, and returning to the step of processing a plurality of transmission tasks corresponding to the current working data channel by utilizing the multi-path selector in a time-sharing manner until all the transmission tasks are completed.
In specific implementation, each data channel may be enabled in sequence according to the priority of the data channel, and the multiplexer may be controlled to gate the address of each external device to the corresponding local memory address according to a fixed sequence, so as to process each transmission task in a time-sharing manner.
The control of the multiplexer for each data channel can be realized by programming the channel selection module in advance in the DMA controller.
It will be appreciated that other numbers of data channels may be designed, and that each data channel may correspond to other numbers of transfer tasks, depending on the hardware circuitry of the DMA controller.
EXAMPLE III
On the basis of the foregoing embodiment, to further improve the chip data transmission efficiency, in the DMA transmission control method provided in the embodiment of the present application, the transmission task is executed, which may specifically be: and executing the transmission task by adopting a chain transmission mode.
If the chain transmission mode is not adopted, one data channel can only transmit one continuous physical memory block at a time, and if the next memory block needs to be transmitted, the memory must be reinitialized, the DMA register is configured, and the DMA controller is started again.
In order to further improve the chip transmission efficiency, the DMA transmission control method provided in this embodiment of the present application may further implement a chain transmission mode based on a transmission module implemented by pre-programming under the condition that a FIFO space with a preset size is pre-allocated for each data channel, execute a transmission task in a chain transmission manner, continuously transmit a plurality of memory blocks after initializing the data channel, and request the DMA to complete an interrupt until completing transmission of all the memory blocks, that is, a large amount of data may be transmitted once after each start, thereby improving the data transmission efficiency.
Example four
On the basis of the detailed description of the various embodiments corresponding to the DMA transfer control method implemented by the DMA controller, the present application also discloses a CPU-implemented DMA transfer control method corresponding to the DMA transfer control method described above.
Based on a CPU, the method for controlling DMA transfer provided in the embodiments of the present application includes:
when a transmission requirement between the external equipment and the local memory is generated, generating a transmission task corresponding to the address of the external equipment and the address of the local memory;
enabling the DMA controller, and distributing corresponding data channels for each transmission task so as to sequentially execute each transmission task through the DMA controller;
and after receiving feedback information of the DMA controller that each transmission task is executed completely, executing a checking process of the data written in the local memory.
According to the control method for DMA transmission based on the CPU, the corresponding transmission tasks are generated according to the transmission requirements between the external devices and the local memory, the corresponding data transmission channels are distributed for the transmission tasks after the DMA controller is enabled, then only the feedback information fed back by the DMA controller and used for completing the execution of the transmission tasks needs to be waited, and the operation of checking the correctness of data in the local memory is executed after the feedback information is received.
On the basis of the above detailed description of the various embodiments corresponding to the control method of DMA transfer, the present application also discloses a control device, an apparatus and a storage medium of DMA transfer corresponding to the above method.
EXAMPLE five
Fig. 3 is a schematic structural diagram of a DMA transfer control device according to an embodiment of the present disclosure.
As shown in fig. 3, based on the DMA controller, the DMA transfer control apparatus provided in the embodiment of the present application includes:
an obtaining unit 301, configured to obtain, after receiving the channel enable signal, a correspondence between an address of each external device and a local memory address in a transmission task corresponding to each data channel;
a transmission unit 302, configured to sequentially execute each transmission task according to each corresponding relationship;
and a feedback unit 303, configured to send feedback information to the local CPU after each transmission task is executed.
Further, the transmission unit 302 specifically includes:
the determining subunit is used for determining the current working data channel;
the switching subunit is used for processing a plurality of transmission tasks corresponding to the current working data channel in a time-sharing manner by utilizing the multiplexer; and switching the next data channel into the current working data channel, and returning to the step of processing a plurality of transmission tasks corresponding to the current working data channel by utilizing the multi-path selector in a time-sharing manner until all the transmission tasks are completed.
Further, the transmission unit 302 sequentially executes each transmission task, specifically: and executing each transmission task in sequence according to the preset priority of each data channel and each corresponding relation.
Further, the device for controlling DMA transfer provided in the embodiment of the present application may further include:
and the synchronization unit is used for controlling a peripheral bus connected with the external equipment and a high-level high-performance bus connected with the local CPU to carry out control signal synchronization according to the clock frequency of the external equipment corresponding to the transmission task before executing the transmission task.
Further, the transmission unit 302 executes a transmission task, specifically: and executing the transmission task by adopting a chain transmission mode.
Further, the transmission unit 302 executes a transmission task, specifically: and in the process of transmitting the source end data of the transmission task to the destination end, caching the source end data by adopting a cache space corresponding to the data channel.
Further, the buffer space is a FIFO space of a preset size.
Since the embodiment of the apparatus portion and the embodiment of the method portion correspond to each other, please refer to the description of the embodiment of the method portion for the embodiment of the apparatus portion, and details are not repeated here.
The control device for DMA transmission provided by the embodiment of the application is realized based on a DMA controller, the design acquisition unit acquires the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel after receiving the channel enabling signal, then the transmission unit executes each transmission task in sequence according to the corresponding relation, and the feedback unit sends feedback information to the local CPU after each transmission task is executed. The DMA transmission control method provided by the embodiment of the application realizes a multi-channel DMA controller, can process a plurality of external equipment requests at one time, does not need to initialize and configure the DMA controller once again in each transmission, optimizes the utilization condition of the area of the DMA controller, can transmit a large amount of data more quickly, obviously improves the data transmission efficiency of a chip, and further optimizes the performance of a chip system.
Example six
Based on the CPU, another DMA transfer control apparatus provided in the embodiment of the present application includes: the method comprises the following steps:
the device comprises a generating unit, a processing unit and a processing unit, wherein the generating unit is used for generating a transmission task corresponding to the address of the external equipment and the address of the local memory when a transmission requirement between the external equipment and the local memory is generated;
the distribution unit is used for enabling the DMA controller and distributing corresponding data channels for the transmission tasks so as to sequentially execute the transmission tasks through the DMA controller;
and the checking unit is used for executing a checking process of the data written in the local memory after receiving the feedback information of the DMA controller that the execution of each transmission task is finished.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
The DMA transmission control device provided by the embodiment of the application is realized based on a CPU, a design generation unit generates a plurality of corresponding transmission tasks according to transmission requirements between a plurality of external devices and a local memory, a distribution unit is utilized to distribute corresponding data transmission channels for each transmission task after a DMA controller is enabled, a check unit waits for feedback information fed back by the DMA controller and used for finishing execution of each transmission task, and the feedback information is received and then executed to the local memory to check data correctness and other operations.
EXAMPLE seven
Fig. 4 is a schematic structural diagram of a control device for DMA transfer according to an embodiment of the present application.
As shown in fig. 4, the control device for DMA transfer provided in the embodiment of the present application includes:
a memory 410 for storing a computer program 411;
a processor 420 for executing a computer program 411, the computer program 411 implementing the steps of the method for controlling DMA transfer according to any one of the above embodiments when executed by the processor 420.
Processor 420 may include one or more processing cores, such as a 3-core processor, an 8-core processor, and so forth. Processor 420 may be implemented in hardware using at least one of a Digital Signal Processing (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). Processor 420 may also include a main processor, which is a processor for Processing data in a wake state and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 420 may be integrated with a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content that the display screen needs to display. In some embodiments, processor 420 may also include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
Memory 410 may include one or more storage media, which may be non-transitory. Memory 410 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 410 is at least used for storing the following computer program 411, wherein after the computer program 411 is loaded and executed by the processor 420, the relevant steps in the control method for DMA transfer disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored by the memory 410 may also include an operating system 412, data 413, and the like, which may be stored in a transient or persistent manner. Operating system 412 may be Windows, among others. The data 413 may include, but is not limited to, data involved in the above-described methods.
In some embodiments, the control device for DMA transfers may also include a display 430, a power supply 440, a communication interface 450, an input output interface 460, a sensor 470, and a communication bus 480.
Those skilled in the art will appreciate that the configuration shown in fig. 4 does not constitute a definition of a control device for DMA transfers and may include more or fewer components than those shown.
The control device for DMA transmission provided in the embodiment of the present application includes a memory and a processor, where the processor can implement the control method for DMA transmission as described above when executing a program stored in the memory, after receiving a channel enable signal, obtain a correspondence between an address of each external device and a local memory address in a transmission task corresponding to each data channel, then sequentially execute each transmission task according to the correspondence, and after each transmission task is completely executed, send feedback information to a local CPU. The DMA transmission control method provided by the application realizes a multi-channel DMA controller, can process a plurality of external equipment requests at one time, does not need to initialize and configure the DMA controller once again in each transmission, optimizes the area utilization condition of the DMA controller, can transmit a large amount of data more quickly, obviously improves the data transmission efficiency of a chip, and further optimizes the performance of a chip system. .
Example eight
It should be noted that the above-described embodiments of the apparatus and device are merely illustrative, for example, the division of modules is only one division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, indirect coupling or communication connection between devices or modules, and may be in an electrical, mechanical or other form. Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions.
To this end, an embodiment of the present application further provides a storage medium, where a computer program is stored, and the computer program, when executed by a processor, implements the steps of the control method such as DMA transfer.
The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory ROM (Read-Only Memory), a Random Access Memory RAM (Random Access Memory), a magnetic disk, or an optical disk.
The computer program included in the storage medium provided in this embodiment is capable of implementing the steps of the DMA transmission control method described above when executed by the processor, and after receiving the channel enable signal, obtains a correspondence between an address of each external device and a local memory address in a transmission task corresponding to each data channel, then sequentially executes each transmission task according to the correspondence, and after each transmission task is executed, sends feedback information to the local CPU. The DMA transmission control method provided by the application realizes a multichannel DMA controller, can process a plurality of external equipment requests at one time, does not need to initialize and configure the DMA controller once again in each transmission, optimizes the utilization condition of the area of the DMA controller, can transmit a large amount of data more quickly, obviously improves the data transmission efficiency of a chip, and further optimizes the performance of a chip system.
The foregoing detailed description has provided a DMA transfer control method, control apparatus, control device, and storage medium. The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device, the equipment and the storage medium disclosed by the embodiment correspond to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It should also be noted that, in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (12)
1. A DMA transfer control method is characterized in that based on a DMA controller, the method comprises the following steps:
after receiving the channel enabling signal, acquiring the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel;
executing each transmission task in sequence according to each corresponding relation;
and after each transmission task is executed, sending feedback information to a local CPU.
2. The control method according to claim 1, wherein the executing each of the transmission tasks in sequence according to each of the corresponding relationships specifically includes:
determining a current working data channel;
processing a plurality of transmission tasks corresponding to the current working data channel in a time-sharing manner by using a multiplexer;
and switching the next data channel into the current working data channel, and returning to the step of processing the plurality of transmission tasks corresponding to the current working data channel by utilizing a multi-path selector in a time-sharing manner until all the transmission tasks are completed.
3. The control method according to claim 1, wherein each of the transmission tasks is executed in sequence according to each of the correspondence relationships, specifically:
and executing each transmission task in sequence according to the preset priority of each data channel and each corresponding relation.
4. The control method of claim 1, further comprising, prior to executing the transmission task:
and controlling a peripheral bus connected with the external equipment and a high-level high-performance bus connected with the local CPU to carry out control signal synchronization according to the clock frequency of the external equipment corresponding to the transmission task.
5. The control method according to claim 1, wherein executing the transmission task specifically is:
and executing the transmission task by adopting a chain transmission mode.
6. The control method according to claim 1, wherein executing the transmission task specifically is:
and in the process of transmitting the source data of the transmission task to the destination end, caching the source data by adopting a cache space corresponding to the data channel.
7. The control method according to claim 6, wherein the buffer space is a FIFO space of a predetermined size.
8. A DMA transmission control method is characterized by comprising the following steps based on a CPU:
when a transmission requirement between external equipment and a local memory is generated, generating a transmission task corresponding to the address of the external equipment and the address of the local memory;
enabling a DMA controller, and distributing a corresponding data channel for each transmission task so as to sequentially execute each transmission task through the DMA controller;
and after receiving feedback information of the DMA controller that the execution of each transmission task is finished, executing a checking process of the data written in the local memory.
9. A DMA transfer control apparatus, based on a DMA controller, comprising:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring the corresponding relation between the address of each external device and the local memory address in the transmission task corresponding to each data channel after receiving a channel enabling signal;
a transmission unit, configured to sequentially execute each transmission task according to each corresponding relationship;
and the feedback unit is used for sending feedback information to the local CPU after each transmission task is executed.
10. A DMA transfer control apparatus, based on a CPU, comprising:
the generating unit is used for generating a transmission task corresponding to the address of the external equipment and the address of the local memory when a transmission requirement between the external equipment and the local memory is generated;
the distribution unit is used for enabling the DMA controller and distributing corresponding data channels for the transmission tasks so as to sequentially execute the transmission tasks through the DMA controller;
and the checking unit is used for executing a checking process of the data written in the local memory after receiving the feedback information of the DMA controller that the execution of each transmission task is finished.
11. A DMA transfer control apparatus, comprising:
a memory for storing a computer program;
processor for executing the computer program, which computer program, when executed by the processor, carries out the steps of the method of controlling a DMA transfer according to any one of claims 1 to 7.
12. A storage medium having stored thereon a computer program, characterized in that the computer program, when being executed by a processor, carries out the steps of the method of controlling a DMA transfer according to any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115622678A (en) * | 2022-12-21 | 2023-01-17 | 深圳曦华科技有限公司 | Batch data transmission method and device based on vehicle-mounted chip and storage medium |
| CN117807016A (en) * | 2024-03-01 | 2024-04-02 | 上海励驰半导体有限公司 | Communication method, device and storage medium for multi-core heterogeneous system and external device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115622678A (en) * | 2022-12-21 | 2023-01-17 | 深圳曦华科技有限公司 | Batch data transmission method and device based on vehicle-mounted chip and storage medium |
| CN117807016A (en) * | 2024-03-01 | 2024-04-02 | 上海励驰半导体有限公司 | Communication method, device and storage medium for multi-core heterogeneous system and external device |
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