CN114721987A - Multi-channel interface circuit based on MCU and FPGA SoC framework - Google Patents
Multi-channel interface circuit based on MCU and FPGA SoC framework Download PDFInfo
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- CN114721987A CN114721987A CN202210158972.8A CN202210158972A CN114721987A CN 114721987 A CN114721987 A CN 114721987A CN 202210158972 A CN202210158972 A CN 202210158972A CN 114721987 A CN114721987 A CN 114721987A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to a multi-channel interface circuit based on MCU and FPGA SoC architecture, comprising: the system comprises a bus interface module, an interface control module and an interface access module which are connected in sequence, wherein the bus interface module is connected with the MCU through a system bus, and the interface access module is connected with external equipment; the interface control module is used for mapping interface information set by a user to the bus interface module and controlling the bus interface module to map the interface information to the MCU; the bus interface module is used for obtaining interface configuration data according to a received system bus signal, and the system bus signal is generated by the MCU according to the interface information; the interface control module is also used for controlling the interface access module to realize data transmission with external equipment according to the interface configuration data. The multi-channel interface circuit based on the MCU and FPGA SoC framework enhances the expansibility and the universality of the MCU and the FPGA SoC, reduces the complexity of interface design and improves the flexibility of interface design and application.
Description
Technical Field
The invention belongs to the technical field of a system on chip of an FPGA (field programmable gate array) core, and particularly relates to a multi-path interface circuit based on an MCU (microprogrammed control unit) and an FPGA SoC (system on chip) framework.
Background
The System on Chip (SoC) architectures of an MCU (Microcontroller Unit) and an FPGA (Field-Programmable Gate Array) refer to a System on Chip in which a general MCU, a memory, an external device, and the like are connected to a domestic FPGA to form an MCU controller and an FPGA core. The MCU needs to interact with the external device through the relevant interface. Common interfaces are mainly divided into two categories: the parallel interface is used for simultaneously transmitting each bit of data; a serial interface refers to the sequential transfer of one bit of data.
In one interface design based on the FPGA and the MCU, for example, the RAM in the FPGA is read and written through an interface bus, the addressing range is 0-255, wherein the FPGA design adopts Verilog HDL language, and the singlechip design is completed by C language. In the technical scheme, the data transmission channel of the MCU system is insufficient, high-speed transmission of a large amount of data cannot be realized, the interface specificity is strong, the application scene is fixed, and the flexibility is not high.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a multi-interface circuit based on an MCU and an FPGA SoC framework. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a multi-channel interface circuit based on MCU and FPGA SoC architecture, comprising: a bus interface module, an interface control module and an interface access module which are connected in sequence, wherein,
the bus interface module is connected with the MCU through a system bus, and the interface access module is connected with external equipment;
the interface control module is used for mapping interface information set by a user to the bus interface module and controlling the bus interface module to map the interface information to the MCU;
the bus interface module is used for obtaining interface configuration data according to a received system bus signal, and the system bus signal is generated by the MCU according to the interface information;
the interface control module is also used for controlling the interface access module and the external equipment to realize data transmission according to the interface configuration data.
In an embodiment of the present invention, the interface information includes the number of interface paths, the data bit width of the path, and data read-write information.
In one embodiment of the invention, the bus interface module comprises a register unit.
In an embodiment of the present invention, the interface control module is specifically configured to:
mapping the interface information set by a user to the register unit;
and controlling the bus interface module to map the register unit to the MCU.
In one embodiment of the present invention, the system bus signals include address signals, control signals and data signals, the control signals being read data enable signals or write data enable signals.
In an embodiment of the present invention, the bus interface module is specifically configured to:
acquiring a multi-channel interface access address according to an address signal of a received system bus signal;
and analyzing a control signal of a system bus signal according to the multi-channel interface access address to obtain interface configuration data.
In an embodiment of the present invention, the interface configuration data includes control data, read/write data, a number of lanes configuring the interface, and a data bit width of each lane.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the multi-channel interface circuit based on the MCU and the FPGA SoC framework, the interface information set by a user is mapped to the MCU, and the MCU generates a system bus signal according to the interface information, so that the management of the MCU on the number of channels of the multi-channel interface and the data bit width of each channel is realized;
2. the multi-channel interface circuit based on the MCU and FPGA SoC framework enhances the expansibility and the universality of the MCU and the FPGA SoC, reduces the complexity of interface design and improves the flexibility of interface design and application.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a block diagram of a multi-interface circuit based on MCU and FPGA SoC architecture according to an embodiment of the present invention;
fig. 2 is a block diagram of another multi-interface circuit based on MCU and FPGA SoC architecture according to an embodiment of the present invention.
Detailed Description
In order to further explain the technical means and effects of the present invention adopted to achieve the predetermined invention purpose, the following describes in detail a multi-channel interface circuit based on MCU and FPGA SoC architecture according to the present invention with reference to the accompanying drawings and the detailed embodiments.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
The multi-channel interface circuit based on the MCU and the FPGA SoC framework is mainly realized based on domestic FPGA logic resources. Referring to fig. 1 and fig. 2 in combination, fig. 1 is a block diagram of a multi-interface circuit based on an MCU and an FPGA SoC architecture according to an embodiment of the present invention; fig. 2 is a block diagram of another multi-interface circuit based on MCU and FPGA SoC architecture according to an embodiment of the present invention. As shown in the figure, the multi-interface circuit based on the MCU and the FPGA SoC architecture of the present embodiment includes a bus interface module 1, an interface control module 2, and an interface access module 3. The bus interface module 1, the interface control module 2 and the interface access module 3 are connected in sequence, the bus interface module 1 is connected with the MCU through a system bus, and the interface access module 3 is connected with external equipment.
The interface control module 2 is used for mapping interface information set by a user to the bus interface module 1 and controlling the bus interface module 1 to map the interface information to the MCU; the bus interface module 1 is used for obtaining interface configuration data according to a received system bus signal, and the system bus signal is generated by the MCU according to the interface information; the interface control module 2 is also used for controlling the interface access module 3 to realize data transmission with external equipment according to the interface configuration data.
In this embodiment, the interface information includes the number of interface paths, the data bit width of the path, and the data read/write information. Specifically, the data read-write information is operation information for transmitting write data or read data for a path set by a user.
In the multi-channel interface circuit based on the MCU and the FPGA SoC architecture of this embodiment, interface information set by a user is mapped to the MCU, the MCU generates a system bus signal according to the interface information, and the MCU implements management of the number of channels of the multi-channel interface and the bit width of data of each channel through the interface control module.
Further, the bus interface module 1 comprises a register unit.
Specifically, the interface control module 2 is specifically configured to: mapping interface information set by a user to a register unit; the control bus interface module 1 maps the register unit to the MCU.
In this embodiment, optionally, the register unit includes a configuration register, a read-write register, a control register, and a status register. The interface control module 2 maps the interface information set by the user into the corresponding register. For example, if the number of interface paths set by the user is 1, the interface control module 2 writes 1 in the configuration register.
Further, optionally, in this embodiment, the control bus interface module 1 maps the register unit to a kernel address storage space of the MCU.
In the present embodiment, the system bus signals include address signals, control signals, and data signals. The control signal is a read data enable signal or a write data enable signal, and the data signal is read data or write data.
Specifically, the bus interface module 1 is specifically configured to: acquiring a multi-channel interface access address according to an address signal of a received system bus signal; and analyzing the control signal of the system bus signal according to the multi-channel interface access address to obtain interface configuration data.
In this embodiment, the interface configuration data includes control data, read/write data, the number of lanes configuring the interface, and the data bit width of each lane.
Further, the interface control module 2 is configured to control the interface access module 3 to implement data transmission with an external device according to the control data, the read-write data, the number of accesses configuring an interface, and the data bit width of each access.
In this embodiment, the interface path module 3 implements functions such as the number of paths of the interface path, the data bit width of each path, and data reading and writing based on FPGA logic resources.
It should be noted that, in this embodiment, the external device may be one or more.
Further, the working process of the multi-interface circuit based on the MCU and the FPGA SoC architecture of this embodiment is specifically described as follows:
firstly, the interface control module 2 maps the number of channels of the interface channel module 3, the data bit width of each channel and the data read-write information set by a user to a configuration register, a read-write register, a control register and a status register of the bus interface module 1, and then maps the registers to an MCU kernel address storage space through the bus interface module 1. And the MCU generates a system bus signal according to the number of the channels set by the user, the data bit width of each channel and the data read-write information. The system bus signals comprise address signals, control signals and data signals, wherein the control signals are read data enable signals or write data enable signals, and the data signals are read data or write data. The bus interface module 1 obtains a multi-channel interface access address through an address signal of a system bus signal, analyzes a control signal of the system bus signal according to the multi-channel interface access address, and then controls the interface access module 3 to complete the configuration of the multi-channel interface according to the obtained control data, read-write data, the number of the configured interfaces and the data bit width of each channel, so that the management of the MCU kernel on the multi-channel interface is realized.
Optionally, if the number of lanes of the interface lane module set by the user is multiple, and the data bit width of each lane is multiple bits, the MCU may use a parallel interface to implement high-speed data transmission with the external device through the multi-lane interface circuit of this embodiment. If the number of the channels of the interface channel module set by the user is 1 and the data bit width of each channel is 1 bit, the MCU can use the serial interface to transmit data to the external device through the multi-channel interface circuit of this embodiment.
The multi-channel interface circuit based on the MCU and FPGA SoC framework of the embodiment enhances the expansibility and the universality of the MCU and the FPGA SoC, reduces the complexity of interface design, improves the flexibility of interface design and application, and simultaneously realizes the high-efficiency transmission of data.
It should be noted that, in this document, the terms "comprises", "comprising" or any other variation are intended to cover a non-exclusive inclusion, so that an article or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. The utility model provides a multichannel interface circuit based on MCU and FPGA SoC framework which characterized in that includes: a bus interface module, an interface control module and an interface access module which are connected in sequence, wherein,
the bus interface module is connected with the MCU through a system bus, and the interface access module is connected with external equipment;
the interface control module is used for mapping interface information set by a user to the bus interface module and controlling the bus interface module to map the interface information to the MCU;
the bus interface module is used for obtaining interface configuration data according to a received system bus signal, and the system bus signal is generated by the MCU according to the interface information;
the interface control module is also used for controlling the interface access module and the external equipment to realize data transmission according to the interface configuration data.
2. The multi-interface circuit based on the MCU and FPGA SoC architecture as recited in claim 1, wherein the interface information includes interface path number, path data bit width, and data read-write information.
3. The multi-interface circuit based on the MCU and FPGA SoC architecture as recited in claim 1, wherein the bus interface module comprises a register unit.
4. The multi-interface circuit based on the MCU and FPGA SoC architecture of claim 3, wherein the interface control module is specifically configured to:
mapping the interface information set by a user to the register unit;
and controlling the bus interface module to map the register unit to the MCU.
5. The multi-channel interface circuit based on the MCU and FPGA SoC architecture as claimed in claim 1, wherein the system bus signals comprise address signals, control signals and data signals, and the control signals are read data enable signals or write data enable signals.
6. The multi-interface circuit based on the MCU and FPGA SoC architecture of claim 5, wherein the bus interface module is specifically configured to:
acquiring a multi-channel interface access address according to an address signal of a received system bus signal;
and analyzing a control signal of a system bus signal according to the multi-channel interface access address to obtain interface configuration data.
7. The multi-channel interface circuit based on the MCU and FPGA SoC architecture as recited in claim 6, wherein the interface configuration data comprises control data, read-write data, the number of channels configuring the interface, and the data bit width of each channel.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116383107A (en) * | 2023-06-06 | 2023-07-04 | 成都立思方信息技术有限公司 | Flexibly-expandable signal receiving and transmitting system |
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2022
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