CN112117330A - 一种改善深槽超结mosfet耐压的器件结构及其工艺方法 - Google Patents

一种改善深槽超结mosfet耐压的器件结构及其工艺方法 Download PDF

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CN112117330A
CN112117330A CN202010994103.XA CN202010994103A CN112117330A CN 112117330 A CN112117330 A CN 112117330A CN 202010994103 A CN202010994103 A CN 202010994103A CN 112117330 A CN112117330 A CN 112117330A
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薛璐
何军
胡兴正
刘海波
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Nanjing Huaruiwei Integrated Circuit Co ltd
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Abstract

本发明公开了一种改善深槽超结MOSFET耐压的器件结构及其工艺方法,通过在外延中的多次注入,改变器件从底部到表面的N型杂质浓度,减小器件底部的N型杂质浓度,增加器件表面的N型杂质浓度,使器件底部和表面的N型杂质与P型杂质的比例均达到1:1。本发明可以解决传统深槽型超结MOSFET受工艺影响导致的耐压不稳及偏低的问题。

Description

一种改善深槽超结MOSFET耐压的器件结构及其工艺方法
技术领域
本发明属于半导体器件工艺领域,特别涉及了一种深槽超结MOSFET器件结构及其工艺方法。
背景技术
如图1所示,普通深槽超结MOS功率管的剖面图由于其工艺方法的特征,深槽刻蚀后形成深槽形貌是带有一定倾角的,且由于Pitch越做越小,倾角会越来越大,这样会导致深槽回填P型外延后,形成的P-pillar区域底部P与外延的N严重不平衡,致使电场集中、电压骤降。
发明内容
为了解决上述背景技术提到的技术问题,本发明提出了一种改善深槽超结MOSFET耐压的器件结构及其工艺方法。
为了实现上述技术目的,本发明的技术方案为:
一种改善深槽超结MOSFET耐压的器件结构,通过在外延中的多次注入,改变器件从底部到表面的N型杂质浓度,减小器件底部的N型杂质浓度,增加器件表面的N型杂质浓度,使器件底部和表面的N型杂质与P型杂质的比例均达到1:1。
一种改善深槽超结MOSFET耐压的器件结构的工艺方法,包括以下步骤:
(1)采用N型(100)晶向作为外延片的衬底,掺杂砷元素或锑元素,在衬底上生长一层初始外延;
(2)在初始外延上生长一层中间外延,进行三次N型杂质P普注,三次注入的能量分别为60、150、300KeV,注入的剂量为1E12~3E12;此步骤根据耐压需求重复多次;
(3)在中间外延上生长一层表面外延;
(4)在外延片上普长一层氧化层,作为JFET注入的掩蔽层;然后进行JFET光刻和JFET注入,注入的能量为60Kev~80Kev,注入的剂量为1E12~3E12,注入元素为磷元素;
(5)依次进行Hard mask淀积、Trench光刻及刻蚀;然后生长一层牺牲氧化层并去除,将Trench表面缺陷或颗粒去除;然后进行Trench内EPI回填,形成器件P/N结构;
(6)在有源区进行Body光刻、注入和退火,形成P-body结区域;注入的能量为100Kev~140Kev,注入的剂量为4E13~6E13,注入的元素为硼元素,退火的温度为1100℃,退火的时间为30~180分钟;
(7)生长一层场氧化层并进行光刻,对有源区进行曝光和腐蚀,除终端区域外,其余有源区氧化层全部去除;
(8)生长一层栅氧化层,沉积多晶并进行掺杂;然后进行多晶光刻和刻蚀;
(9)依次进行NP光刻、NP注入及NP推阱,形成主MOS管源区;注入的能量为60Kev~120Kev,注入的剂量为5E15~1E16,注入的元素为砷元素,推阱的温度为950℃,推阱的时间为30分钟;
(10)沉积介质,然后进行孔光刻及腐蚀,形成孔接触;
(11)沉积金属,然后光刻腐蚀金属,形成MOS的栅区和源区;
(12)减薄衬底背面,再在衬底背面蒸发Ti-Ni-Ag合金。
进一步地,在步骤(1)中,初始外延的电阻率为1~3Ω.cm;在步骤(2)中,中间外延的电阻率为10~30Ω.cm;在步骤(3)中,表面外延的电阻率为1~3Ω.cm。
进一步地,在步骤(4)中,生长的氧化层厚度为300~500埃;在步骤(7)中,生长的场氧化层厚度为8000~12000埃;在步骤(8)中,生长的栅氧化层厚度为700~1200埃,生长的多晶厚度为6000-8000埃。
进一步地,在步骤(10)中,所述介质为硼磷硅玻璃,介质的厚度为10000埃。
进一步地,在步骤(11)中,所述金属为铝,金属的厚度为4um。
进一步地,在步骤(11)与步骤(12)之间,通过钝化层沉积、光刻、腐蚀,形成MOS栅极和源极的开口区以及采样MOS管源极的开口区。
进一步地,所述钝化层采用氮化硅,钝化层的厚度为7000-12000埃。
采用上述技术方案带来的有益效果:
本发明设计的改善深槽超结MOSFET耐压的器件结构及其制备工艺,通过在外延中的多次注入,改变了从底部到表面的N型杂质浓度,可以解决传统深槽型超结MOSFET受工艺影响导致的耐压不稳及偏低的问题,且随着Pitch的越做越小,此结构的优势会越来越明显。
附图说明
图1是传统深槽超结MOS功率管的剖面图;
图2是本发明设计的深槽超结MOS功率管的剖面图;
图3是本发明制备工艺步骤1后的示意图;
图4是本发明制备工艺步骤2后的示意图;
图5是本发明制备工艺步骤3后的示意图;
图6是本发明制备工艺步骤4后的示意图;
图7是本发明制备工艺步骤5后的示意图;
图8是本发明制备工艺步骤6后的示意图;
图9是本发明制备工艺步骤7后的示意图;
图10是本发明制备工艺步骤8后的示意图;
图11是本发明制备工艺步骤9后的示意图;
图12是本发明制备工艺步骤10后的示意图;
图13是本发明制备工艺步骤11后的示意图。
具体实施方式
以下将结合附图,对本发明的技术方案进行详细说明。
本发明设计了一种改善深槽超结MOSFET耐压的器件结构,如图2所示,通过在外延中的多次注入,改变器件从底部到表面的N型杂质浓度,减小器件底部的N型杂质浓度,增加器件表面的N型杂质浓度,使器件底部和表面的N型杂质与P型杂质的比例均达到1:1,可以得到稳定且更高的耐压。
上述改善深槽超结MOSFET耐压的器件结构的工艺流程如下:
1.初始外延准备:外延片的衬底采用N型(100)晶向,砷元素或锑元素掺杂,电阻率通常为0.001~0.005Ω.cm.选择不同的外延电阻率和厚度,可得到不同的器件耐压。通常电阻率为1~3Ω.cm,先生长一层7um的外延,如图3所示;
2.中间外延生长:生长电阻率为10~30Ω.cm,厚度为5~6um外延,进行三次N型杂质P普注,能量分别为60、150、300KeV,剂量为1E12~3E12;此过程根据不同耐压需求,重复6~8次;如图4所示;
3.表面外延准备:生长电阻率为1-3Ω.cm,厚度为5um外延,如图5所示;外延总厚度达到45-60um,器件耐压可以达到500V-800V;
4.JFET光刻&imp:在外延片上普长一层300埃-500埃的氧化层,用于JFET注入的掩蔽层。然后JFET光刻,然后JFET注入,注入的能量:60Kev~80Kev,剂量:1E12~3E12,磷元素。该步骤的目的是对CELL中JFET区进行掺杂,如图6所示;
5.Trench光刻刻蚀及P型外延回填:Hard mask(氧化层)淀积,Trench光刻,刻蚀,再生长一层牺牲氧化并去除,将Trench表面缺陷或颗粒等去除;之后进行Trench内EPI回填,形成CoolMOS器件P/N结构,如图7所示;
6.Body光刻、注入和退火:在有源区进行选择性曝光后进行注入,注入剂量:4E13~6E13,注入能量:100Kev-140Kev,注入元素:硼;然后BODY退火,温度:1100℃,时间:30-180分钟,形成P-body结区域;如图8所示;
7.场氧生长、光刻、腐蚀:生长一层8000~12000埃的氧化层,并进行光刻,对有源区曝光和腐蚀,除终端区域外,其余有源区氧化层全部去除;如图9所示;
8.栅氧,沉积多晶及多晶掺杂、光刻、刻蚀:生长栅氧化层,厚度一般为700-1200埃,沉积多晶厚度6000-8000埃并进行掺杂;然后进行多晶光刻和刻蚀,如图10所示;
9.NP光刻,NP注入,NP推进,形成主MOS管源区:NP注入剂量:5E15~1E16,注入能量:60Kev-120Kev,注入元素:砷;NP推阱温度:950℃,时间:30分钟;如图11所示;
10.生成介质,孔光刻,孔腐蚀:沉积介质BPSG(硼磷硅玻璃)10000埃,然后开孔,形成孔接触,如图12所示;
11.溅射metal,metal光刻,腐蚀:沉积4um铝,然后光刻腐蚀铝,形成MOS的栅区和源区,如图13所示;
12.钝化层沉积,钝化层光刻,腐蚀:沉积钝化层氮化硅7000-12000埃,然后光刻腐蚀,形成Gate和Source的开口区;钝化层工艺是可选项,可作业或也可不作业;
13.背面Ti-Ni-Ag:减薄衬底背面到200um-300um,再在衬底背面蒸发Ti-Ni-Ag(钛-镍-银)合金。
实施例仅为说明本发明的技术思想,不能以此限定本发明的保护范围,凡是按照本发明提出的技术思想,在技术方案基础上所做的任何改动,均落入本发明保护范围之内。

Claims (8)

1.一种改善深槽超结MOSFET耐压的器件结构,其特征在于:通过在外延中的多次注入,改变器件从底部到表面的N型杂质浓度,减小器件底部的N型杂质浓度,增加器件表面的N型杂质浓度,使器件底部和表面的N型杂质与P型杂质的比例均达到1:1。
2.一种改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:包括以下步骤:
(1)采用N型(100)晶向作为外延片的衬底,掺杂砷元素或锑元素,在衬底上生长一层初始外延;
(2)在初始外延上生长一层中间外延,进行三次N型杂质P普注,三次注入的能量分别为60、150、300KeV,注入的剂量为1E12~3E12;此步骤根据耐压需求重复多次;
(3)在中间外延上生长一层表面外延;
(4)在外延片上普长一层氧化层,作为JFET注入的掩蔽层;然后进行JFET光刻和JFET注入,注入的能量为60Kev~80Kev,注入的剂量为1E12~3E12,注入元素为磷元素;
(5)依次进行Hard mask淀积、Trench光刻及刻蚀;然后生长一层牺牲氧化层并去除,将Trench表面缺陷或颗粒去除;然后进行Trench内EPI回填,形成器件P/N结构;
(6)在有源区进行Body光刻、注入和退火,形成P-body结区域;注入的能量为100Kev~140Kev,注入的剂量为4E13~6E13,注入的元素为硼元素,退火的温度为1100℃,退火的时间为30~180分钟;
(7)生长一层场氧化层并进行光刻,对有源区进行曝光和腐蚀,除终端区域外,其余有源区氧化层全部去除;
(8)生长一层栅氧化层,沉积多晶并进行掺杂;然后进行多晶光刻和刻蚀;
(9)依次进行NP光刻、NP注入及NP推阱,形成主MOS管源区;注入的能量为60Kev~120Kev,注入的剂量为5E15~1E16,注入的元素为砷元素,推阱的温度为950℃,推阱的时间为30分钟;
(10)沉积介质,然后进行孔光刻及腐蚀,形成孔接触;
(11)沉积金属,然后光刻腐蚀金属,形成MOS的栅区和源区;
(12)减薄衬底背面,再在衬底背面蒸发Ti-Ni-Ag合金。
3.根据权利要求2所述改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:在步骤(1)中,初始外延的电阻率为1~3Ω.cm;在步骤(2)中,中间外延的电阻率为10~30Ω.cm;在步骤(3)中,表面外延的电阻率为1~3Ω.cm。
4.根据权利要求2所述改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:在步骤(4)中,生长的氧化层厚度为300~500埃;在步骤(7)中,生长的场氧化层厚度为8000~12000埃;在步骤(8)中,生长的栅氧化层厚度为700~1200埃,生长的多晶厚度为6000-8000埃。
5.根据权利要求2所述改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:在步骤(10)中,所述介质为硼磷硅玻璃,介质的厚度为10000埃。
6.根据权利要求2所述改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:在步骤(11)中,所述金属为铝,金属的厚度为4um。
7.根据权利要求2所述改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:在步骤(11)与步骤(12)之间,通过钝化层沉积、光刻、腐蚀,形成MOS栅极和源极的开口区以及采样MOS管源极的开口区。
8.根据权利要求7所述改善深槽超结MOSFET耐压的器件结构的工艺方法,其特征在于:所述钝化层采用氮化硅,钝化层的厚度为7000-12000埃。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007036793A2 (en) * 2005-09-30 2007-04-05 Analog Power Limited Power mosfets and methods of making same
US20070290267A1 (en) * 2006-06-15 2007-12-20 Fuji Electric Holdings Co., Ltd Semiconductor device and method of manufacturing the same
CN102479806A (zh) * 2010-11-22 2012-05-30 上海华虹Nec电子有限公司 超级结半导体器件及其制作方法
CN102479805A (zh) * 2010-11-30 2012-05-30 比亚迪股份有限公司 一种超级结半导体元件及其制造方法
CN103065966A (zh) * 2011-10-21 2013-04-24 上海华虹Nec电子有限公司 一种超级结的制备工艺方法
CN103681779A (zh) * 2012-09-11 2014-03-26 无锡华润上华半导体有限公司 一种场效应晶体管结构及其制作方法
US20180061936A1 (en) * 2016-08-23 2018-03-01 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN111223915A (zh) * 2020-01-16 2020-06-02 无锡新洁能股份有限公司 多次外延超结器件结构及其制造方法
CN111668292A (zh) * 2020-07-09 2020-09-15 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件及其制造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007036793A2 (en) * 2005-09-30 2007-04-05 Analog Power Limited Power mosfets and methods of making same
US20070290267A1 (en) * 2006-06-15 2007-12-20 Fuji Electric Holdings Co., Ltd Semiconductor device and method of manufacturing the same
CN102479806A (zh) * 2010-11-22 2012-05-30 上海华虹Nec电子有限公司 超级结半导体器件及其制作方法
CN102479805A (zh) * 2010-11-30 2012-05-30 比亚迪股份有限公司 一种超级结半导体元件及其制造方法
CN103065966A (zh) * 2011-10-21 2013-04-24 上海华虹Nec电子有限公司 一种超级结的制备工艺方法
CN103681779A (zh) * 2012-09-11 2014-03-26 无锡华润上华半导体有限公司 一种场效应晶体管结构及其制作方法
US20180061936A1 (en) * 2016-08-23 2018-03-01 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN111223915A (zh) * 2020-01-16 2020-06-02 无锡新洁能股份有限公司 多次外延超结器件结构及其制造方法
CN111668292A (zh) * 2020-07-09 2020-09-15 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件及其制造方法

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