CN111971793A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN111971793A
CN111971793A CN201880092357.3A CN201880092357A CN111971793A CN 111971793 A CN111971793 A CN 111971793A CN 201880092357 A CN201880092357 A CN 201880092357A CN 111971793 A CN111971793 A CN 111971793A
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wiring
semiconductor
semiconductor module
pad
module according
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CN201880092357.3A
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CN111971793B (zh
Inventor
中田洋辅
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

在基座板(1)的主面配置有半导体元件(4a～4d)和配线用元件(5)。第1导线(11a～11e)对外部电极(7a～7e)与配线用元件(5)的第1中继焊盘(8a～8e)进行连接。第2导线(12a～12e)对半导体元件(4a～4d)的焊盘(13a～13e)与配线用元件(5)的第2中继焊盘(9a～9e)进行连接。树脂(15)对半导体元件(4a～4d)、配线用元件(5)以及第1导线、第2导线(11a～11e、12a～12e)进行封装。第2导线(12a～12e)比第1导线(11a～11e)细。焊盘(13a～13e)比第1中继焊盘(8a～8e)小。

Description

半导体模块
技术领域
本发明涉及一种半导体模块。
背景技术
使用在多个半导体元件的焊盘处键合导线而对多个半导体元件进行并行驱动的半导体模块(例如，参照专利文献1)。
专利文献1：国际公开第2014/046058号
发明内容
就通过环氧类树脂等进行封装的半导体模块而言，由于树脂流入而使导线漂动。因此，为了确保制造性和可靠性，难以使导线细化。但是，如果导线直径粗，则需要使被进行导线的键合的半导体元件的焊盘也变大，存在半导体元件的有效面积减少的问题。
本发明就是为了解决上述课题而提出的，其目的在于，得到一种半导体模块，其能够确保制造性和可靠性并且增加半导体元件的有效面积。
本发明所涉及的半导体模块的特征在于，具有：基座板；半导体元件，其配置于所述基座板之上，具有焊盘；外部电极；配线用元件，其配置于所述基座板之上，具有第1中继焊盘、第2中继焊盘和配线，该第2中继焊盘配置得比所述第1中继焊盘更靠近所述焊盘，该配线对所述第1中继焊盘以及所述第2中继焊盘进行连接；第1导线，其对所述外部电极与所述第1中继焊盘进行连接；第2导线，其对所述焊盘与所述第2中继焊盘进行连接；以及树脂，其对所述半导体元件、所述配线用元件以及所述第1导线、所述第2导线进行封装，所述第2导线比所述第1导线细，所述焊盘小于所述第1中继焊盘。
发明的效果
在本发明中，通过使用配线用元件，能够缩短半导体元件的焊盘与配线用元件的中继焊盘之间的距离，因此即使将连接两者的导线变细，也能够保证导线强度。另外，能够使对细导线进行键合的半导体元件的焊盘变小。由此，能够确保制造性和可靠性并且增加半导体元件的有效面积。
附图说明
图1是表示实施方式1所涉及的半导体模块的俯视图。
图2是沿图1的I-II的剖面图。
图3是表示实施方式1所涉及的配线用元件的俯视图。
图4是沿图3的I-II的剖面图。
图5是将图3的通过虚线包围的区域放大后的俯视图。
图6是表示实施方式2所涉及的半导体模块的剖面图。
具体实施方式
参照附图，对实施方式所涉及的半导体模块进行说明。对于相同或者对应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是表示实施方式1所涉及的半导体模块的俯视图。图2是沿图1的I-II的剖面图。图3是表示实施方式1所涉及的配线用元件的俯视图。
在作为基座板的绝缘基板1的上表面形成电路图案2而构成电极基板。在绝缘基板1的下表面形成有用于经由例如油脂或者焊料与冷却器连接的金属层3。金属层3不限于是平坦的，也可以形成有针鳍(pin fin)状或者叶片状的能够直接冷却的部分。
在处于同一平面之上的电路图案2之上配置半导体元件4a～4d和配线用元件5，通过例如焊料等接合材料6进行接合。在半导体元件4a～4d和配线用元件5的背面，分别形成有用于焊接于电路图案2的金属膜。该金属膜例如以镍为主要材料。在配线用元件5附近配置有外部电极7a～7e。
半导体元件4a～4d是MOSFET。不限于此，半导体元件4a～4d也可以是同样作为开关用元件的IGBT或者作为续流用元件的SBD等能够通电的元件。作为续流用元件，也可以不使用SBD，而使用MOSFET的体二极管。不管是什么情况，为了降低通电损耗，都通过磨削等方法调整为耐压保持等所需的足够的厚度。另一方面，在配线用元件5没有形成晶体管或者二极管等器件。
在配线用元件5的上表面，在外部电极7a～7e附近配置有中继焊盘8a～8e。中继焊盘9a～9e配置得比中继焊盘8a～8e更靠近半导体元件4a～4d的焊盘13a～13e。配线10a～10e分别对中继焊盘8a～8e与中继焊盘9a～9e进行连接。导线11a～11e分别对外部电极7a～7e与中继焊盘8a～8e进行连接。导线12a～12e分别对半导体元件4a～4d的焊盘13a～13e与中继焊盘9a～9e进行连接。
板状导体14通过焊料等接合材料6与多个半导体元件4a～4d的表面电极即源极电极接合。在多个半导体元件4a～4d的表面电极，为了进行焊接，形成有例如以镍为主要材料的金属膜。此外，为了防止板状导体14与导线键合工具之间的干扰，必须在半导体元件4a～4d与配线用元件5的导线键合后对板状导体14进行接合。
为了使元件以及电极与外部气体绝缘，树脂15对半导体元件4a～4d、配线用元件5以及导线11a～11e、12a～12e进行封装。树脂15例如通过向树脂壳体内注入环氧类树脂而固化，或者向模具压入传递模塑树脂而固化来形成。通过使用树脂15，能够提高耐湿性、耐振动性、针对冷热循环的可靠性。
这里，外部电极7a～7e由壳体或者引线框固定，配置于封装件的外侧。因此，配线用元件5与外部电极7a～7e的距离远。与该外部电极7a～7e连接的导线11a～11e长，线环高度变高。因此，为了具有不会随树脂15而漂动的刚性，需要使导线11a～11e***。导线11a～11e例如是直径为200μm的铝线。通过使用廉价的铝作为导线11a～11e的主要材料，即使导线直径***，也能够抑制材料费的高涨。另外，由于能够灵活运用现有的导线键合装置，因此也容易与现有的制造设备共存。
导线12a～12e例如是直径为30μm的金导线。通过使用金作为导线12a～12e的主要材料，即使导线直径变细，也能够抑制连接不良以及因氧化引起的耐久性的劣化。此外，虽然金的材料费高，但由于缩短了导线12a～12e的长度，所以能够抑制成本的增加。这样，导线12a～12e比导线11a～11e细。但是，导线直径仅是一个例子，需要根据导线的引绕长度、注入的封装树脂的粘度、流速、流入方向等进行适当调整。进行细导线12a～12e的键合的半导体元件4a～4d的焊盘13a～13e以及中继焊盘9a～9e比进行粗导线11a～11e的键合的中继焊盘8a～8e小。
图4是沿图3的I-II的剖面图。在基板16之上形成有绝缘层17。在绝缘层17之上形成有中继焊盘8a～8e、9a～9e和配线10a～10e。覆盖膜18覆盖多根配线10a～10e。由此，即使减小配线间距离也能够保证绝缘性。因此，能够缩小配线用元件5的尺寸，所以能够进一步降低制造成本，能够使半导体模块小型化。另外，覆盖膜18的主要材料是聚酰亚胺。由此，能够通过现有的晶片工艺廉价且稳定地进行制造，能够保证制造成本和可靠性。而且，聚酰亚胺与环氧类树脂封装材料的相容性也好。
图5是将图3的通过虚线包围的区域放大后的俯视图。多个中继焊盘8e分别与多个半导体元件4a～4d的栅极连接。配线10e分别与多个中继焊盘8e连接。多个栅极电阻19分别连接于多个中继焊盘8e与配线10e之间。即使由于半导体元件4a～4d的晶片工艺的偏差而使半导体元件4a～4d的阈值电压偏离目标值，也能够通过调整栅极电阻19的电阻值来抵消阈值电压的偏离量。具体地说，对应的半导体元件4a～4d的阈值电压越高，栅极电阻19的电阻值设定得越低。由此，就根据阈值电压对半导体元件进行分级选择(ranked selection)的半导体模块而言，能够消除多个半导体元件的阈值电压的偏差，均一地驱动多个半导体元件4a～4d。其结果，在对多个半导体元件4a～4d进行并行驱动时，不会产生电流不平衡，并且能够使分级选择出的每个半导体模块的通断特性尽量相同。
栅极电阻19是由以硅为主要成分的材料构成的多晶硅电阻膜。例如，在同样地沉积了多晶硅膜后，通过照相制版处理和蚀刻处理，图案化为任意的形状，从而形成栅极电阻用多晶硅膜。这样，由于多晶硅电阻膜能够通过现有的晶片工艺形成于同一芯片之上，因此能够容易地实现均质的栅极电阻。例如对光刻掩模进行切换，对栅极电阻19所用的硅膜的尺寸进行变更，对栅极电阻19的电阻值进行调整。或者，通过对栅极电阻19所用的硅膜的杂质浓度进行调整，或者利用激光光线等对栅极电阻19所用的硅膜进行微调，从而能够对栅极电阻19的电阻值进行调整。
在本实施方式中，通过使用配线用元件5，能够缩短半导体元件4a～4d的焊盘13a～13e与配线用元件5的中继焊盘9a～9e之间的距离，因此即使将连接两者的导线12a～12e变细，也能够保证导线强度。另外，能够减小对细导线12a～12e进行键合的半导体元件4a～4d的焊盘13a～13e。由此，能够确保制造性和可靠性并且增加半导体元件4a～4d的有效面积。通过增加半导体元件4a～4d的有效面积，能够实现高输出化、低成本化。
另外，绝缘基板1之上的电路图案2与半导体元件4a～4d的下表面的漏极(功率端子)连接，是被施加高电压的强电部。在该强电部之上形成有配线用元件5的基板16。在基板16之上形成有热氧化膜等绝缘层17，在其之上形成有中继焊盘8a～8e、9a～9e和配线10a～10e。通过该绝缘层17能够确保强电部与配线10a～10e等的绝缘性，提高可靠性。此外，由于以往在陶瓷基板之上形成了强电部和信号配线，因此为了确保两者的绝缘距离而必须增大配线间距离。与此相对，在本实施方式中，由于通过配线用元件5的纵向构造实现了与强电部的绝缘，所以基板16的上表面的配线间距离仅是控制电源电压程度的绝缘所需要的距离即可。由此，配线布局的自由度增大，能够以最短距离连接导线。
与半导体元件4a～4d的栅极连接的配线10e和与源极连接的配线10d配置成环状。其他配线10a～10c配置于其内侧。由此，能够使配线用元件5小型化。另外，在与不具有感测元件的半导体元件4a～4d的连接中，能够尽量缩短导线12a～12e的距离，因此能够改善制造成品率。此外，有时环状的配线10d、10e的环路由于主电流的变化而产生电动势，流过感应电流而使半导体元件4a～4d误动作。因此，也可以使环状的配线10d、10e的一部分断开。由此，能够避免形成环路，尽量降低来自主电流的感应。
通过使用板状导体14，与导线键合相比，能够降低配线电阻和电感。由于通过本实施方式能够减小焊盘13a～13e，因此能够增大与板状导体14的接合面积而降低配线电阻和电感。
另外，通过使配线用元件5小型化，从而能够使配置多个半导体元件4a～4d的空间充裕，增大布局设计的自由度，因此能够使多个半导体元件4a～4d靠近配置。其结果，能够缩小与多个半导体元件4a～4d连接的板状导体14的尺寸。由此，能够在降低板状导体14的部件加工费、材料费的同时，通过电感等的降低效果来降低半导体元件4a～4d的损耗。并且，能够降低由板状导体14与半导体元件4a～4d等周边部件的线膨胀系数差引起的应力，还能够提高可靠性。另外，板状导体14也可以覆盖配线用元件5。由此，能够简化主电流电路的配线，能够使半导体模块小型化，能够改善制造成本、电气特性、可靠性。
另外，通过使导线12a～12e变细，能够降低线环高度。因此，即使在板状导体14将半导体元件4a～4d和导线12a～12e的连接部覆盖的情况下，也能够使导线12a～12e与板状导体14之间的间隙最小化。因此，无需极端地增加半导体模块的厚度，就能够避免导线12a～12e与板状导体14短路。
半导体元件4b具有感测用元件。通过该感测用元件，能够准确且逐次地掌握半导体元件4b的状态。由此，能够使保护电路在正确的定时(timing)动作，能够降低半导体模块的损耗，提高可靠性。
感测元件具有：温度感测二极管，其对半导体元件的温度进行检测；以及电流感测元件，其以固定的分流比对流过半导体元件的电流值进行检测。半导体元件4b的焊盘13a与电流感测元件连接，焊盘13b、13c分别与温度感测二极管的阳极和阴极连接。此外，通过使连接于阴极的焊盘13c与连接于源极的焊盘13d短路，能够削减焊盘数量。
在为了半导体模块的小型化而密集地配置了多个半导体元件4a～4d的情况下，配置于绝缘基板1内侧的半导体元件的温度容易上升。因此，优选地，与不具有感测用元件的半导体元件4a、4c、4d相比，将具有感测用元件的半导体元件4b配置于绝缘基板1的内侧。
半导体元件4a～4d具有碳化硅或者氮化镓等化合物半导体基板。由于化合物半导体的材料费和加工费高，所以根据本实施方式，通过增加半导体元件的有效面积，从而能够降低产品成本。
在配线用元件5具有硅基板的情况下，能够通过现有的晶片工艺容易地形成，能够通过与半导体元件4a～4d相同的方法进行组装。因此，能够降低制造成本。另外，由于通过使用照相制版工艺能够微细地形成复杂的配线，因此能够使配线用元件5小型化。由此，能够缩短主电流配线长度而降低主电流配线的电感，因此能够降低对SiC等半导体元件进行驱动时的通断损耗。并且，能够在尽可能靠近的状态下对配线用元件5内的配线、特别是与栅极连接的配线10e和与源极连接的配线10d进行引绕。因此，能够尽量抑制来自主电流的感应，能够防止半导体元件4a～4d的误动作。特别是，在具有除了配线10d、10e以外的配线的配线用元件5的情况下形成复杂的配线，但能够容易地使配线10d、10e之间的配线环路最小化。另外，通过将靠近配置的配线10d、10e以环状引绕，能够对多个半导体元件实现等长配线。
另外，基板16也可以是由GaAs等材料构成的半绝缘性基板。在该情况下，能够在基板16之上直接形成中继焊盘8a～8e、9a～9e和配线10a～10e，不需要使基板16和配线10a～10e等绝缘的绝缘层17。因此，能够缩短配线用元件5的制造工艺，降低制造成本。此外，作为配线用元件5也可以使用印刷基板。通过使用廉价的印刷基板，能够降低部件成本。
优选地，通过半导体元件加工工艺的磨削等对元件的厚度进行调整，使得焊盘13a～13e与中继焊盘9a～9e之间的高度差小于或等于100μm。通过使得焊盘高度一致，能够缩短导线12a～12e，因此，能够防止细导线12a～12e在注入封装树脂时漂动。
实施方式2.
图6是表示实施方式2所涉及的半导体模块的剖面图。在本实施方式中，使用导体板20作为基座板。半导体元件4a～4d和配线用元件5配置于导体板20的同一平面之上。导体板20是由例如以铜为主要材料构成的散热器。散热器通过与下表面接合的绝缘片或者绝缘板而与空冷鳍片或者水冷鳍片等冷却框体绝缘。这些绝缘体和散热器可以直接接合，也可以经由散热脂等接合。
通过使用导体板20，即使在有效面积比较小的半导体元件4a～4d的情况下，也能够有效地使热扩散，能够降低热阻，提高半导体损耗的通电性能、可靠性。特别是，以碳化硅等为主要材料的半导体元件4a～4d难以大面积化，需要更有效地使热扩散，因此本实施方式特别有效。
另外，由于难以在导体板20之上形成配线，所以以往大多使引线框等具有配线的作用。因此，妨碍半导体模块的小型化，由于引线框的形成或者组装等的公差，配线短路，制造成品率和可靠性降低。与此相对，在本实施方式中，通过使用配线用元件5，从而能够在导体板20之上配置配线，因此能够解决这些问题。其他结构以及效果与实施方式1相同。
标号的说明
1绝缘基板(基座板)，2电路图案(强电部)，4a～4d半导体元件，5配线用元件，7a～7e外部电极，8a～8e、9a～9e中继焊盘，10a～10e配线，11a～11e、12a～12e导线，13a～13e焊盘，14板状导体，15树脂，16基板，17绝缘层，18覆盖膜，19栅极电阻，20导体板(基座板)。

Claims (18)

1.一种半导体模块，其特征在于，具有：
基座板；
半导体元件，其配置于所述基座板之上，具有焊盘；
外部电极；
配线用元件，其配置于所述基座板之上，具有第1中继焊盘、第2中继焊盘和配线，该第2中继焊盘配置得比所述第1中继焊盘更靠近所述焊盘，该配线对所述第1中继焊盘以及所述第2中继焊盘进行连接；
第1导线，其对所述外部电极与所述第1中继焊盘进行连接；
第2导线，其对所述焊盘与所述第2中继焊盘进行连接；以及
树脂，其对所述半导体元件、所述配线用元件以及所述第1导线、所述第2导线进行封装，
所述第2导线比所述第1导线细，
所述焊盘小于所述第1中继焊盘。
2.根据权利要求1所述的半导体模块，其特征在于，
还具有强电部，该强电部形成于所述基座板之上，与所述半导体元件的下表面的功率端子连接，
所述配线用元件还具有形成于所述强电部之上的基板和形成于所述基板之上的绝缘层，
在所述绝缘层之上形成有所述第1中继焊盘及所述第2中继焊盘、所述配线。
3.根据权利要求1所述的半导体模块，其特征在于，
所述基座板是导体板。
4.根据权利要求1至3中任一项所述的半导体模块，其特征在于，
所述配线具有：
第1配线，其配置成环状；以及
第2配线，其配置于所述第1配线的内侧。
5.根据权利要求4所述的半导体模块，其特征在于，
环状的所述第1配线的一部分断开。
6.根据权利要求1至5中任一项所述的半导体模块，其特征在于，
所述半导体元件具有多个晶体管，
所述第2中继焊盘具有分别与所述多个晶体管的栅极连接的多个焊盘，
在所述多个焊盘与所述配线之间分别连接有多个栅极电阻，
对应的所述半导体元件的阈值电压越高，所述栅极电阻的电阻值越低。
7.根据权利要求6所述的半导体模块，其特征在于，
所述栅极电阻由以硅为主要成分的材料构成。
8.根据权利要求1至7中任一项所述的半导体模块，其特征在于，
所述半导体元件具有：
第1半导体元件，其具有感测用元件；以及
第2半导体元件，其不具有感测用元件，
所述第1半导体元件与所述第2半导体元件相比配置于所述基座板的内侧。
9.根据权利要求1至8中任一项所述的半导体模块，其特征在于，
还具有与所述半导体元件的表面电极接合的板状导体。
10.根据权利要求1至9中任一项所述的半导体模块，其特征在于，
所述配线用元件具有覆盖所述配线的覆盖膜。
11.根据权利要求10所述的半导体模块，其特征在于，
所述覆盖膜的主要材料是聚酰亚胺。
12.根据权利要求1至11中任一项所述的半导体模块，其特征在于，
所述半导体元件具有化合物半导体基板。
13.根据权利要求1至12中任一项所述的半导体模块，其特征在于，
所述配线用元件具有硅基板。
14.根据权利要求1至12中任一项所述的半导体模块，其特征在于，
所述配线用元件具有半绝缘性基板。
15.根据权利要求1至12中任一项所述的半导体模块，其特征在于，
所述配线用元件是印刷基板。
16.根据权利要求1至15中任一项所述的半导体模块，其特征在于，
所述第2导线的主要材料是金。
17.根据权利要求1至16中任一项所述的半导体模块，其特征在于，
所述第1导线的主要材料是铝。
18.根据权利要求1至17中任一项所述的半导体模块，其特征在于，
所述焊盘与所述第2中继焊盘的高度差小于或等于100μm。
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