CN111883581A - 一种新型平面栅mos型半导体功率器件及其制造方法 - Google Patents
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Abstract
本发明公开了一种新型平面栅MOS型半导体功率器件及其制造方法,具有:半导体衬底;阱区,半导体衬底内设有阱区,阱区露出半导体衬底的上表面;源区,设置在阱区内,源区露出阱区的上表面;氧化层,设置在半导体衬底的上表面上,氧化层的第一端延伸到阱区和源区的上表面上;栅电极,设置在氧化层的上表面上,栅电极的第一端上设有斜面台阶;绝缘氧化层,设置在栅电极的上表面上,绝缘氧化层的第一端延伸到源区的上表面上;金属层,设置在绝缘氧化层的上表面上,金属层的第一端延伸到阱区和源区的上表面上,提升平面栅器件在应用中电压电流波形的稳定性。
Description
技术领域
本发明属于半导体技术领域,尤其涉及一种新型平面栅MOS型半导体功率器件及其制造方法。
背景技术
MOSFET,IGBT等MOS型半导体功率器件,有着开关速度快,开关损耗低,控制电路简单等优点,在电力电子领域中有着广泛的应用。其栅极结构主要有平面栅和沟槽栅两种,其中平面栅结构由于制作工艺简单,鲁棒性高等特点,在很多高可靠性要求的产品中有着广泛的应用。
在实现本发明的过程中,发明人发现现有技术至少存在以下问题:常见平面栅MOS型半导体功率器件结构中,栅电极G和源极电极金属S之间的绝缘是通过绝缘氧化层绝缘介质隔离来实现,由于栅电极的厚度通常需要比较厚(比如通常用到1um)以保证良好的导电能力,故形成的栅电极台阶比较高,绝缘介质层膜层端部塌陷比较明显,导致栅电极G和源极电极金属S之间的绝缘层厚度变薄,降低绝缘能力。特别是为了提升平面栅器件在应用中电压电流波形的稳定性,要求绝缘氧化层的厚度尽可能薄,以增大GE输入电容,此时绝缘介质层膜层端部厚度非常薄,导致GS之间漏电或者的耐压能力不足。
发明内容
本发明所要解决的技术问题是提供一种提升平面栅器件在应用中电压电流波形的稳定性的新型平面栅MOS型半导体功率器件及其制造方法。
为了解决上述技术问题,本发明所采用的技术方案是:一种新型平面栅MOS型半导体功率器件,具有:
半导体衬底;
阱区,所述半导体衬底内设有阱区,所述阱区露出所述半导体衬底的上表面;
源区,设置在所述阱区内,所述源区露出所述阱区的上表面;
氧化层,设置在半导体衬底的上表面上,所述氧化层的端部延伸到所述阱区和源区的上表面上;
栅电极,设置在所述氧化层的上表面上,所述栅电极的端部上设有斜面台阶;
绝缘氧化层,设置在所述栅电极的上表面上,所述绝缘氧化层的端部延伸到所述源区的上表面上;
金属层,设置在所述绝缘氧化层的上表面上,所述金属层的端部延伸到所述阱区和源区的上表面上。
所述栅电极为多晶硅层。
所述金属层为源极电极。
所述半导体衬底具有N型掺杂。
所述多晶硅层具有N型掺杂。
所述栅电极的第一端的底部为垂直台阶,栅电极的端部的上部为斜面台阶,所述源区为N型掺杂,所述阱区为P型掺杂。
一种上述的新型平面栅MOS型半导体功率器件的制造方法,包括如下步骤:
1)提供一种具有N型掺杂的半导体衬底;
2)在N型半导体衬底的上表面热氧化生长一层氧化层;
3)在氧化层表面沉积一层多晶硅层,多晶硅层进行N型掺杂;
4)在氧化层表面涂覆光刻,并曝光显影,将部分多晶硅层暴露出来;
5)将暴露出来的多晶硅层的端部蚀刻掉,形成了斜面台阶;
6)将暴露出的端部剩余的多晶硅层和氧化层蚀刻干净,形成底部的垂直台阶;
7)去除多晶硅层上方剩余的光刻胶层;
8)通过离子注入和扩散方法,在半导体衬底体内、去除了多晶硅层的区域,掺杂阱区和源区;
9)在阱区、源区和多晶硅层上沉积绝缘氧化层,并进行高温退火回流;
10)在绝缘氧化层表面涂覆光刻胶,并曝光显影,选择性蚀刻绝缘氧化层,将部分阱区和源区表面露出;
11)在绝缘氧化层上沉积金属层,形成源极电极。
上述第6)步中,利用各项异性的干法蚀刻,将暴露出的端部剩余的多晶硅层和氧化层蚀刻干净,形成底部的垂直台阶。
上述第8)步中,通过离子注入和扩散方法,在半导体衬底体内、去除了多晶硅层的区域,选择性掺杂源区和形成P性的阱区。
上述技术方案中的一个技术方案具有如下优点或有益效果,栅电极层台阶不是一个很高陡峭的垂直台阶,而是一个缓变台阶加一个很小的垂直台阶结合,台阶上层部分是一个缓变的斜面台阶,台阶下层部分是近似垂直的台阶。由于该缓变台阶大大降低了台阶处的陡峭成都,绝缘氧化层回流时的塌陷减缓,A处厚度的厚度不会明显变薄,确保了栅电极和金属层之间的绝缘隔离,避免GS漏电或者耐压能力不足。同时,由于栅电极仅仅是台阶边缘附近厚度变薄,不会牺牲栅电极的导电性能。
附图说明
图1为本发明实施例中提供的新型平面栅MOS型半导体功率器件的结构示意图;
上述图中的标记均为:201、半导体衬底,202、阱区,203、源区,204、氧化层,多晶硅层、栅电极,206、绝缘氧化层,207、金属层。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明实施方式作进一步地详细描述。
实施例一
参见图1,一种新型平面栅MOS型半导体功率器件,具有:
半导体衬底201;
阱区202,半导体衬底201内设有阱区202,阱区202露出半导体衬底201的上表面;
源区203,设置在阱区202内,源区203露出阱区202的上表面;
氧化层204,设置在半导体衬底201的上表面上,氧化层204的端部延伸到阱区202和源区203的上表面上;
栅电极205,设置在氧化层204的上表面上,栅电极205的端部上设有斜面台阶;
绝缘氧化层206,设置在栅电极205的上表面上,绝缘氧化层206的端部延伸到源区203的上表面上;
金属层207,设置在绝缘氧化层206的上表面上,金属层207的端部延伸到阱区202和源区203的上表面上。
栅电极205为多晶硅层。金属层207为源极电极。
半导体衬底201具有N型掺杂。多晶硅层具有N型掺杂。源区203为N型掺杂,阱区202为P型掺杂。
栅电极205的端部的底部为垂直台阶,栅电极205的端部的上部为斜面台阶,
栅电极205层上层缓变的斜面台阶高度占据栅电极205层的50%至90%,斜面角度可为30°~60°范围,下层垂直台阶的高度占据栅电极205层厚度的10%~50%。
实施例二
一种上述的新型平面栅MOS型半导体功率器件的制造方法,包括如下步骤:
1.提供一种具有N型掺杂的半导体衬底201;
2.在N型半导体衬底201的上表面热氧化生长一层氧化层204;
3.在氧化层204表面沉积一层多晶硅层多晶硅层,多晶硅层进行N型掺杂。
4.在氧化层204表面涂覆光刻,并曝光显影,将多晶硅层选择性的暴露出来。
5.利用各项同性蚀刻,将暴露出来的多晶硅层大部分蚀刻掉,形成了缓变的斜面台阶
6.利用各项异性的干法蚀刻,将暴露出的剩余多晶硅层和蚀刻干净,形成底部的垂直台阶;
7.去除多晶硅层上方剩余的光刻胶层
8.通过离子注入和扩散方法,在半导体衬底201体内,去除了多晶硅层的区域,选择性掺杂形成P性的阱区202和源区203。
9.沉积绝缘氧化层206,并进行高温退火回流;
10.在绝缘氧化层206表面涂覆光刻胶,并曝光显影,选择性蚀刻绝缘氧化层206层,将部分阱区202和源区203表面露出。
11.沉积金属层207,形成源极电极s。
第5步利用各项同性蚀刻方法,在多晶硅层上层形成缓变的斜面台阶,从而避免绝缘氧化层206塌陷引起的厚度变薄,第6步用各项异性方法蚀刻,在多晶硅层下层形成垂直台阶,便于精准的控制多晶硅层的边缘位置,与设计的掩膜图形高度一致,保证产品结构和性能的一致性。
采用上述的方案后,栅电极205层台阶不是一个很高陡峭的垂直台阶,而是一个缓变台阶加一个很小的垂直台阶结合,台阶上层部分是一个缓变的斜面台阶,台阶下层部分是近似垂直的台阶。由于该缓变台阶大大降低了台阶处的陡峭成都,绝缘氧化层206回流时的塌陷减缓,A处厚度的厚度不会明显变薄,确保了栅电极205和金属层207之间的绝缘隔离,避免GS漏电或者耐压能力不足。同时,由于栅电极205仅仅是台阶边缘附近厚度变薄,不会牺牲栅电极205的导电性能。
上面结合附图对本发明进行了示例性描述,显然本发明具体实现并不受上述方式的限制,只要采用了本发明的方法构思和技术方案进行的各种非实质性的改进,或未经改进将本发明的构思和技术方案直接应用于其它场合的,均在本发明的保护范围之内。
Claims (10)
1.一种新型平面栅MOS型半导体功率器件,其特征在于,具有:
半导体衬底;
阱区,所述半导体衬底内设有阱区,所述阱区露出所述半导体衬底的上表面;
源区,设置在所述阱区内,所述源区露出所述阱区的上表面;
氧化层,设置在半导体衬底的上表面上,所述氧化层的端部延伸到所述阱区和源区的上表面上;
栅电极,设置在所述氧化层的上表面上,所述栅电极的端部上设有斜面台阶;
绝缘氧化层,设置在所述栅电极的上表面上,所述绝缘氧化层的端部延伸到所述源区的上表面上;
金属层,设置在所述绝缘氧化层的上表面上,所述金属层的延伸到所述阱区和源区的上表面上。
2.如权利要求1所述的新型平面栅MOS型半导体功率器件,其特征在于,所述栅电极为多晶硅层。
3.如权利要求2所述的新型平面栅MOS型半导体功率器件,其特征在于,所述金属层为源极电极。
4.如权利要求3所述的新型平面栅MOS型半导体功率器件,其特征在于,所述半导体衬底具有N型掺杂。
5.如权利要求4所述的新型平面栅MOS型半导体功率器件,其特征在于,所述多晶硅层具有N型掺杂。
6.如权利要求5所述的新型平面栅MOS型半导体功率器件,其特征在于,所述栅电极的第一端的底部为垂直台阶,栅电极的端部的上部为斜面台阶。
7.如权利要求6所述的新型平面栅MOS型半导体功率器件,其特征在于,所述源区为N型掺杂,所述阱区为P型掺杂。
8.一种如权利要求1-6任一所述的新型平面栅MOS型半导体功率器件的制造方法,其特征在于,包括如下步骤:
1)提供一种具有N型掺杂的半导体衬底;
2)在N型半导体衬底的上表面热氧化生长一层氧化层;
3)在氧化层表面沉积一层多晶硅层,多晶硅层进行N型掺杂;
4)在氧化层表面涂覆光刻,并曝光显影,将部分多晶硅层暴露出来;
5)将暴露出来的多晶硅层的端部蚀刻掉,形成了斜面台阶;
6)将暴露出的端部剩余的多晶硅层和氧化层蚀刻干净,形成底部的垂直台阶;
7)去除多晶硅层上方剩余的光刻胶层;
8)通过离子注入和扩散方法,在半导体衬底体内、去除了多晶硅层的区域,掺杂阱区和源区;
9)在阱区、源区和多晶硅层上沉积绝缘氧化层,并进行高温退火回流;
10)在绝缘氧化层表面涂覆光刻胶,并曝光显影,选择性蚀刻绝缘氧化层,将部分阱区和源区表面露出;
11)在绝缘氧化层上沉积金属层,形成源极电极。
9.如权利要求8所述的新型平面栅MOS型半导体功率器件的制造方法,其特征在于,上述第6)步中,利用各项异性的干法蚀刻,将暴露出的端部剩余的多晶硅层和氧化层蚀刻干净,形成底部的垂直台阶。
10.如权利要求9所述的新型平面栅MOS型半导体功率器件的制造方法,其特征在于,上述第8)步中,通过离子注入和扩散方法,在半导体衬底体内、去除了多晶硅层的区域,选择性掺杂源区和形成P性的阱区。
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JP2000164862A (ja) * | 1998-11-26 | 2000-06-16 | Fuji Electric Co Ltd | Mos半導体装置およびその製造方法 |
US20160218014A1 (en) * | 2015-01-28 | 2016-07-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
CN106133915A (zh) * | 2014-09-09 | 2016-11-16 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
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JP2000164862A (ja) * | 1998-11-26 | 2000-06-16 | Fuji Electric Co Ltd | Mos半導体装置およびその製造方法 |
CN106133915A (zh) * | 2014-09-09 | 2016-11-16 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
US20160218014A1 (en) * | 2015-01-28 | 2016-07-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
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