CN111883581A - Novel planar gate MOS type semiconductor power device and manufacturing method thereof - Google Patents

Novel planar gate MOS type semiconductor power device and manufacturing method thereof Download PDF

Info

Publication number
CN111883581A
CN111883581A CN202010687412.2A CN202010687412A CN111883581A CN 111883581 A CN111883581 A CN 111883581A CN 202010687412 A CN202010687412 A CN 202010687412A CN 111883581 A CN111883581 A CN 111883581A
Authority
CN
China
Prior art keywords
oxide layer
layer
well region
semiconductor substrate
power device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010687412.2A
Other languages
Chinese (zh)
Inventor
肖秀光
温世达
吕磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui Ruidi Microelectronics Co ltd
Original Assignee
Anhui Ruidi Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anhui Ruidi Microelectronics Co ltd filed Critical Anhui Ruidi Microelectronics Co ltd
Priority to CN202010687412.2A priority Critical patent/CN111883581A/en
Publication of CN111883581A publication Critical patent/CN111883581A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a novel planar gate MOS type semiconductor power device and a manufacturing method thereof, and the device comprises: a semiconductor substrate; the semiconductor device comprises a well region, a first substrate and a second substrate, wherein the well region is arranged in the semiconductor substrate and exposes the upper surface of the semiconductor substrate; the source region is arranged in the well region and exposed out of the upper surface of the well region; the first end of the oxide layer extends to the upper surfaces of the well region and the source region; the gate electrode is arranged on the upper surface of the oxide layer, and the first end of the gate electrode is provided with an inclined plane step; the insulating oxide layer is arranged on the upper surface of the gate electrode, and a first end of the insulating oxide layer extends to the upper surface of the source region; and the metal layer is arranged on the upper surface of the insulating oxide layer, and the first end of the metal layer extends to the upper surfaces of the well region and the source region, so that the stability of voltage and current waveforms of the planar gate device in application is improved.

Description

Novel planar gate MOS type semiconductor power device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a novel planar gate MOS type semiconductor power device and a manufacturing method thereof.
Background
The MOS type semiconductor power devices such as MOSFET, IGBT and the like have the advantages of high switching speed, low switching loss, simple control circuit and the like, and are widely applied to the field of power electronics. The grid structure mainly comprises a planar grid and a trench grid, wherein the planar grid structure has the characteristics of simple manufacturing process, high robustness and the like, and is widely applied to a plurality of products with high reliability requirements.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems: in a common planar gate MOS type semiconductor power device structure, insulation between a gate electrode G and a source electrode metal S is achieved by insulating oxide layer insulating medium isolation, and since the thickness of the gate electrode generally needs to be relatively thick (for example, 1um is generally used) to ensure good conductivity, the step of the formed gate electrode is relatively high, and collapse of the end of a film layer of an insulating medium layer is relatively obvious, so that the thickness of an insulating layer between the gate electrode G and the source electrode metal S is thinned, and the insulating capability is reduced. Particularly, in order to improve the stability of voltage and current waveforms in application of the planar gate device, the thickness of the insulating oxide layer is required to be as thin as possible to increase the GE input capacitance, and at the moment, the thickness of the end part of the insulating dielectric layer film layer is very thin, so that the leakage between GS or the voltage resistance is insufficient.
Disclosure of Invention
The invention aims to provide a novel planar gate MOS type semiconductor power device for improving the stability of voltage and current waveforms of a planar gate device in application and a manufacturing method thereof.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a new planar gate MOS type semiconductor power device having:
a semiconductor substrate;
the semiconductor substrate is provided with a well region, and the well region is exposed out of the upper surface of the semiconductor substrate;
the source region is arranged in the well region and exposes the upper surface of the well region;
the oxide layer is arranged on the upper surface of the semiconductor substrate, and the end parts of the oxide layer extend to the upper surfaces of the well region and the source region;
the gate electrode is arranged on the upper surface of the oxide layer, and an inclined plane step is arranged at the end part of the gate electrode;
the insulating oxide layer is arranged on the upper surface of the gate electrode, and the end part of the insulating oxide layer extends to the upper surface of the source region;
and the metal layer is arranged on the upper surface of the insulating oxide layer, and the end part of the metal layer extends to the upper surfaces of the well region and the source region.
The gate electrode is a polysilicon layer.
The metal layer is a source electrode.
The semiconductor substrate has an N-type doping.
The polysilicon layer has an N-type doping.
The bottom of the first end of the gate electrode is a vertical step, the upper part of the end part of the gate electrode is an inclined-plane step, the source region is doped in an N type mode, and the well region is doped in a P type mode.
The manufacturing method of the novel planar gate MOS type semiconductor power device comprises the following steps:
1) providing a semiconductor substrate with N-type doping;
2) growing an oxide layer on the upper surface of the N-type semiconductor substrate through thermal oxidation;
3) depositing a polysilicon layer on the surface of the oxide layer, and carrying out N-type doping on the polysilicon layer;
4) coating photoetching on the surface of the oxide layer, exposing and developing to expose part of the polycrystalline silicon layer;
5) etching the exposed end of the polycrystalline silicon layer to form an inclined step;
6) etching the exposed residual polysilicon layer and the exposed oxide layer at the end part to form a vertical step at the bottom;
7) removing the residual photoresist layer above the polysilicon layer;
8) through ion implantation and diffusion method, the region of the polycrystalline silicon layer is removed, the well region and the source region are doped in the semiconductor substrate;
9) depositing an insulating oxide layer on the well region, the source region and the polycrystalline silicon layer, and carrying out high-temperature annealing reflux;
10) coating photoresist on the surface of the insulating oxide layer, exposing and developing, selectively etching the insulating oxide layer, and exposing partial surfaces of the well region and the source region;
11) and depositing a metal layer on the insulating oxide layer to form a source electrode.
And 6), etching the residual polycrystalline silicon layer and the residual oxide layer at the exposed end part by utilizing anisotropic dry etching to form a vertical step at the bottom.
And 8) in the step, removing the region of the polysilicon layer, selectively doping the source region and forming the P-shaped well region in the semiconductor substrate body by an ion implantation and diffusion method.
One of the above technical solutions has the following advantages or beneficial effects that the gate electrode layer step is not a very high and steep vertical step, but a combination of a gradual step and a very small vertical step, the upper layer part of the step is a gradual inclined step, and the lower layer part of the step is an approximately vertical step. Because the gradual change step greatly reduces the steep formation of the step, the collapse of the insulation oxide layer during the backflow is slowed down, the thickness of the A part cannot be obviously thinned, the insulation isolation between the gate electrode and the metal layer is ensured, and the GS electric leakage or insufficient voltage resistance is avoided. Meanwhile, the gate electrode is only thinned near the step edge, so that the conductive performance of the gate electrode is not sacrificed.
Drawings
Fig. 1 is a schematic structural diagram of a novel planar gate MOS-type semiconductor power device provided in an embodiment of the present invention;
the labels in the above figures are: 201. the semiconductor device comprises a semiconductor substrate, 202, a well region, 203, a source region, 204, an oxide layer, a polycrystalline silicon layer, a gate electrode, 206, an insulating oxide layer, 207 and a metal layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
Referring to fig. 1, a novel planar gate MOS type semiconductor power device has:
a semiconductor substrate 201;
a well region 202, wherein the well region 202 is arranged in the semiconductor substrate 201, and the well region 202 exposes the upper surface of the semiconductor substrate 201;
a source region 203 arranged in the well region 202, the source region 203 exposing the upper surface of the well region 202;
an oxide layer 204 disposed on the upper surface of the semiconductor substrate 201, end portions of the oxide layer 204 extending onto the upper surfaces of the well region 202 and the source region 203;
a gate electrode 205 disposed on an upper surface of the oxide layer 204, an end of the gate electrode 205 being provided with an inclined step;
an insulating oxide layer 206 disposed on an upper surface of the gate electrode 205, an end portion of the insulating oxide layer 206 extending onto an upper surface of the source region 203;
and a metal layer 207 disposed on an upper surface of the insulating oxide layer 206, wherein end portions of the metal layer 207 extend to upper surfaces of the well region 202 and the source region 203.
The gate electrode 205 is a polysilicon layer. The metal layer 207 is a source electrode.
The semiconductor substrate 201 has an N-type doping. The polysilicon layer has N-type doping. The source region 203 is doped N-type and the well region 202 is doped P-type.
The bottom of the end of the gate electrode 205 is a vertical step, the upper portion of the end of the gate electrode 205 is a sloped step,
the height of the gradually-changed inclined plane step on the upper layer of the gate electrode 205 layer occupies 50-90% of the thickness of the gate electrode 205 layer, the inclined plane angle can be in the range of 30-60 degrees, and the height of the vertical step on the lower layer occupies 10-50% of the thickness of the gate electrode 205 layer.
Example two
The manufacturing method of the novel planar gate MOS type semiconductor power device comprises the following steps:
1. providing a semiconductor substrate 201 with N-type doping;
2. growing an oxide layer 204 on the upper surface of the N-type semiconductor substrate 201 by thermal oxidation;
3. a polysilicon layer is deposited on the surface of the oxide layer 204, and the polysilicon layer is doped N-type.
4. The surface of the oxide layer 204 is exposed by photolithography and exposure to selectively expose the polysilicon layer.
5. Most of the exposed polysilicon layer is etched by isotropic etching to form a gradual slope step
6. Utilizing anisotropic dry etching to etch the exposed residual polysilicon layer to form a vertical step at the bottom;
7. removing the residual photoresist layer above the polysilicon layer
8. By ion implantation and diffusion methods, the polysilicon layer is removed in the semiconductor substrate 201, and a P-type well region 202 and a source region 203 are formed by selective doping.
9. Depositing an insulating oxide layer 206, and performing high-temperature annealing reflux;
10. and coating photoresist on the surface of the insulating oxide layer 206, exposing and developing, and selectively etching the insulating oxide layer 206 to expose parts of the surfaces of the well region 202 and the source region 203.
11. A metal layer 207 is deposited to form a source electrode s.
And step 5, forming a slowly-changed inclined-plane step on the upper layer of the polycrystalline silicon layer by utilizing an isotropic etching method so as to avoid the thinning of the thickness caused by the collapse of the insulating oxide layer 206, and step 6, etching by utilizing an anisotropic method so as to form a vertical step on the lower layer of the polycrystalline silicon layer, so that the edge position of the polycrystalline silicon layer is conveniently and accurately controlled, the height of the edge position is consistent with the height of a designed mask graph, and the consistency of the structure and the performance of a product is ensured.
After the scheme is adopted, the step of the gate electrode 205 layer is not a vertical step with high and steep gradient, but a combination of a gradual step and a small vertical step, the upper part of the step is a gradual inclined-plane step, and the lower part of the step is an approximately vertical step. Because the gradual step greatly reduces the steep formation of the step, the collapse of the insulating oxide layer 206 is slowed down during the backflow, the thickness of the A part is not obviously thinned, the insulating isolation between the gate electrode 205 and the metal layer 207 is ensured, and the GS electric leakage or insufficient voltage resistance is avoided. Meanwhile, since the gate electrode 205 is only thinned near the step edge, the conductive property of the gate electrode 205 is not sacrificed.
The invention has been described above with reference to the accompanying drawings, it is obvious that the invention is not limited to the specific implementation in the above-described manner, and it is within the scope of the invention to apply the inventive concept and solution to other applications without substantial modification.

Claims (10)

1. A novel planar gate MOS type semiconductor power device, characterized by having:
a semiconductor substrate;
the semiconductor substrate is provided with a well region, and the well region is exposed out of the upper surface of the semiconductor substrate;
the source region is arranged in the well region and exposes the upper surface of the well region;
the oxide layer is arranged on the upper surface of the semiconductor substrate, and the end parts of the oxide layer extend to the upper surfaces of the well region and the source region;
the gate electrode is arranged on the upper surface of the oxide layer, and an inclined plane step is arranged at the end part of the gate electrode;
the insulating oxide layer is arranged on the upper surface of the gate electrode, and the end part of the insulating oxide layer extends to the upper surface of the source region;
and the metal layer is arranged on the upper surface of the insulating oxide layer and extends to the upper surfaces of the well region and the source region.
2. The new planar gate MOS-type semiconductor power device according to claim 1, wherein said gate electrode is a polysilicon layer.
3. The new planar gate MOS-type semiconductor power device as claimed in claim 2, wherein said metal layer is a source electrode.
4. The new planar gate MOS-type semiconductor power device according to claim 3, wherein said semiconductor substrate has an N-type doping.
5. The new planar gate MOS-type semiconductor power device according to claim 4, wherein said polysilicon layer has an N-type doping.
6. The new planar gate MOS type semiconductor power device as claimed in claim 5, wherein a bottom of the first end of the gate electrode is a vertical step, and an upper portion of the end portion of the gate electrode is a sloped step.
7. The new planar gate MOS-type semiconductor power device of claim 6, wherein said source region is doped N-type and said well region is doped P-type.
8. A method for manufacturing a new type of semiconductor power device of the planar gate MOS type according to any of the claims 1 to 6, characterized in that it comprises the following steps:
1) providing a semiconductor substrate with N-type doping;
2) growing an oxide layer on the upper surface of the N-type semiconductor substrate through thermal oxidation;
3) depositing a polysilicon layer on the surface of the oxide layer, and carrying out N-type doping on the polysilicon layer;
4) coating photoetching on the surface of the oxide layer, exposing and developing to expose part of the polycrystalline silicon layer;
5) etching the exposed end of the polycrystalline silicon layer to form an inclined step;
6) etching the exposed residual polysilicon layer and the exposed oxide layer at the end part to form a vertical step at the bottom;
7) removing the residual photoresist layer above the polysilicon layer;
8) through ion implantation and diffusion method, the region of the polycrystalline silicon layer is removed, the well region and the source region are doped in the semiconductor substrate;
9) depositing an insulating oxide layer on the well region, the source region and the polycrystalline silicon layer, and carrying out high-temperature annealing reflux;
10) coating photoresist on the surface of the insulating oxide layer, exposing and developing, selectively etching the insulating oxide layer, and exposing partial surfaces of the well region and the source region;
11) and depositing a metal layer on the insulating oxide layer to form a source electrode.
9. The method of claim 8, wherein in step 6), the exposed end portions of the remaining polysilicon layer and the remaining oxide layer are etched clean by anisotropic dry etching to form bottom vertical steps.
10. The method as claimed in claim 9, wherein in step 8), the region of the semiconductor substrate where the polysilicon layer is removed, the source region and the P-type well region are selectively doped by ion implantation and diffusion.
CN202010687412.2A 2020-07-16 2020-07-16 Novel planar gate MOS type semiconductor power device and manufacturing method thereof Pending CN111883581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010687412.2A CN111883581A (en) 2020-07-16 2020-07-16 Novel planar gate MOS type semiconductor power device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010687412.2A CN111883581A (en) 2020-07-16 2020-07-16 Novel planar gate MOS type semiconductor power device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN111883581A true CN111883581A (en) 2020-11-03

Family

ID=73156260

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010687412.2A Pending CN111883581A (en) 2020-07-16 2020-07-16 Novel planar gate MOS type semiconductor power device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111883581A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164862A (en) * 1998-11-26 2000-06-16 Fuji Electric Co Ltd Mos semiconductor device and its manufacture
US20160218014A1 (en) * 2015-01-28 2016-07-28 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN106133915A (en) * 2014-09-09 2016-11-16 富士电机株式会社 Semiconductor device and the manufacture method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164862A (en) * 1998-11-26 2000-06-16 Fuji Electric Co Ltd Mos semiconductor device and its manufacture
CN106133915A (en) * 2014-09-09 2016-11-16 富士电机株式会社 Semiconductor device and the manufacture method of semiconductor device
US20160218014A1 (en) * 2015-01-28 2016-07-28 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

Similar Documents

Publication Publication Date Title
US4864377A (en) Silicon on insulator (SOI) semiconductor device
CN113053738A (en) Split gate type groove MOS device and preparation method thereof
CN115207128B (en) Negative-pressure-resistant silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) with trench side wall gate and preparation method thereof
CN105655402A (en) Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same
CN102569066B (en) Manufacturing method for gate controlled diode semiconductor device
TWI802048B (en) Ldmos transistor and manufacturing method thereof
CN109979821A (en) A kind of semiconductor devices and preparation method thereof
CN114141621A (en) Carrier storage groove gate bipolar transistor with split gate and preparation method thereof
CN103022155B (en) Groove MOS (metal oxide semiconductor) structure Schottky diode and preparation method thereof
TWI414070B (en) Semiconductor power device
WO2021114437A1 (en) Trench field effect transistor structure, and manufacturing method for same
TWI382476B (en) Method for forming semiconductor device
CN116404032A (en) Preparation method of N-channel enhanced MOSFET device for realizing low on-resistance
CN114334661B (en) Groove type double-layer gate power MOSFET and manufacturing method thereof
CN111883581A (en) Novel planar gate MOS type semiconductor power device and manufacturing method thereof
CN115083895A (en) Manufacturing method of field stop IGBT chip with back variable doping structure
CN114156183A (en) Split gate power MOS device and manufacturing method thereof
CN101621072A (en) Semiconductor device and manufacture method thereof
JP2624948B2 (en) MOS-FET manufacturing method
KR100790742B1 (en) Transistor and method for fabricating the same
KR100275484B1 (en) Method for manufacturing a power device having a trench gate electrode
CN218101271U (en) LDMOS device structure design with freely adjustable threshold voltage and breakdown voltage and hot carrier effect resistance
CN111354642B (en) Manufacturing method of low-on-resistance low-voltage groove gate MOS device
CN115207130B (en) Side wall gate double-groove silicon carbide MOSFET and preparation method thereof
CN109768088B (en) Multi-level semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20201103