CN111880597A - Linear voltage stabilizing circuit and electronic equipment - Google Patents

Linear voltage stabilizing circuit and electronic equipment Download PDF

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Publication number
CN111880597A
CN111880597A CN202010678438.0A CN202010678438A CN111880597A CN 111880597 A CN111880597 A CN 111880597A CN 202010678438 A CN202010678438 A CN 202010678438A CN 111880597 A CN111880597 A CN 111880597A
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circuit
output
terminal
stage
resistor
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CN111880597B (en
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刘珍超
李念龙
余东升
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

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  • Continuous-Control Power Sources That Use Transistors (AREA)
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Abstract

The invention discloses a linear voltage stabilizing circuit and an electronic device, which can improve the system stability, wherein the linear voltage stabilizing circuit comprises an error amplifier, a compensating circuit, a power level output circuit and a current detection circuit, wherein the error amplifier comprises a first gain level circuit and a second gain level circuit; the compensation circuit is used for compensating the poles distributed at the output end of the first-stage gain stage circuit so as to reduce the poles distributed at the output end of the first-stage gain stage circuit and generate a zero point; the current detection circuit is connected with the output end of the linear voltage stabilizing circuit and used for detecting the driving current provided by the output end of the linear voltage stabilizing circuit to the load, when the driving current is low, the zero point is reduced, and when the driving current is increased, the zero point is increased.

Description

Linear voltage stabilizing circuit and electronic equipment
Technical Field
The invention relates to the technical field of linear voltage stabilization, in particular to a linear voltage stabilizing circuit and electronic equipment.
Background
Linear voltage regulator circuits, such as LDO (low dropout regulator), are important power supply products and widely used in consumer electronic devices such as mobile phones and computers. At present, the linear voltage stabilizing circuit is required to output a large driving current in more and more scenes.
The inventor researches and discovers that when the driving current output by the linear voltage stabilizing circuit is high, the size of the power tube is increased, parasitic capacitance is generated, and when the parasitic capacitance is large to a certain degree, the pole distributed at the output end of the error amplifier becomes low, namely, is closer to the origin. Usually, the dominant pole is also close to the origin, and the poles distributed at the output end of the error amplifier become low, which is not favorable for realizing the separation from the dominant pole, and the phase margin is also reduced, so that the stability of the linear voltage stabilizing circuit system is reduced.
Disclosure of Invention
Based on this, the invention provides a linear voltage stabilizing circuit, which can increase the phase margin when the driving current output by the linear voltage stabilizing circuit is high.
In a first aspect, a linear voltage stabilizing circuit is provided, wherein the error amplifier comprises a first gain stage circuit and a second gain stage circuit, an output end of the first gain stage circuit is connected with an input end of the second gain stage circuit; the first end of the compensation circuit is connected with the output end of the first-stage gain stage circuit, and the second end of the compensation circuit is connected with the output end of the second-stage gain stage circuit; the output end of the second-stage gain stage circuit is used as the output end of the error amplifier and is connected with the input end of the buffer circuit, and the output end of the buffer circuit is connected with the control end of the power-stage output circuit; the output end of the power level output circuit is used as the output end of the linear voltage stabilizing circuit to provide driving current for supplying power to a load;
the buffer circuit is used for providing the output capacity of a unit gain so as to enhance the current of the control end of the power stage output circuit;
the compensation circuit is used for compensating the poles distributed at the output end of the first-stage gain stage circuit so as to reduce the poles and generate zero points;
the current detection circuit is connected with the output end of the linear voltage stabilizing circuit and used for detecting the driving current provided by the output end of the linear voltage stabilizing circuit to the load and controlling the compensation circuit to increase the zero point when the driving current is detected to be increased to enter a heavy-load mode.
In one embodiment, the output end of the first-stage gain stage circuit is distributed with poles for becoming non-dominant poles when the driving current is small, the output end of the linear voltage stabilizing circuit is distributed with poles for becoming dominant poles when the driving current is small enough to enter a light load mode, and the current detection circuit is used for reducing the zero point when the driving current is detected to become low.
In one embodiment, the compensation circuit includes a first capacitor, a first resistor, a second capacitor, and an adjustable second resistor, a first end of the first resistor is connected to a first end of the second resistor, a connection point serves as the first end of the compensation circuit and is connected to the output end of the first stage gain stage circuit, a second end of the first resistor is connected to the first end of the first capacitor, a second end of the second resistor is connected to the first end of the second capacitor, a second end of the first capacitor is connected to the second end of the second capacitor, and a connection point serves as the second end of the compensation circuit and is connected to the output end of the second stage gain stage circuit;
the current detection circuit is connected with the second resistor and used for increasing the resistance value of the second resistor to reduce the zero point when the driving current is small and reducing the resistance value of the second resistor to increase the zero point when the driving current is increased.
In one embodiment, the power stage output circuit includes a P-type power transistor, a gate terminal of the P-type power transistor serves as a control terminal of the power stage output circuit, a drain terminal of the P-type power transistor serves as an output terminal of the power stage output circuit, and a source terminal of the P-type power transistor serves as a power supply terminal of the power stage output circuit.
In one embodiment, the power stage further comprises a reference voltage output circuit and an adjustable third resistor, wherein a first end of the third resistor is connected with an output end of the reference voltage output circuit, a second end of the third resistor is connected with a second end of the error amplifier, the reference voltage output circuit is used for outputting a reference voltage, the third resistor outputs an adjustable reference voltage to the second end of the error amplifier, a first input end of the error amplifier is connected with an output end of the power tube to access a feedback voltage at an output end of the power stage output circuit, and the feedback voltage and the output voltage of the power stage output circuit are 1: 1.
In one embodiment, the reference voltage filter circuit further includes the adjustable third resistor and a filter capacitor, a second end of the third resistor is connected to a first end of the filter capacitor, and a second end of the filter circuit is grounded.
In one embodiment, the first-stage gain stage circuit of the error amplifier comprises a PMOS transistor MP3, a PMOS transistor MP4, an NMOS transistor MN2, an NMOS transistor MN3 and an NMOS transistor MN 1; the source ends of the PMOS tube MP3 and the PMOS tube MP4 are both accessed with power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP4, the gate end and the drain end of the PMOS tube MP3 are connected together, the drain end of the PMOS tube MP3 is connected with the drain end of the NMOS tube MN2, the drain end of the PMOS tube MP4 is connected with the drain end of the MOS tube MN3, the gate end of the NMOS tube MN2 is used as the second input end of the error amplifier to access reference voltage, the source end of the NMOS tube MN2 is connected with the source end of the NMOS tube MN3, the connection part is connected with the drain end of the NMOS tube MN1, and the gate end of the NMOS tube MN3 is used as the first input end of the error amplifier to access voltage fed back by the output end of the linear voltage stabilizing circuit; the grid end of the NMOS tube MN1 is connected with a driving voltage, and the source end of the NMOS tube MN1 is grounded.
In one embodiment, the second-stage gain stage circuit of the error amplifier comprises an NMOS transistor MN4 and a PMOS transistor MP 5; the drain terminal of the NMOS transistor MN4 is connected to the drain terminal of the PMOS transistor MP5, the gate terminal of the NMOS transistor MN4 is connected to a driving voltage, the source terminal of the NMOS transistor MN4 is grounded, the gate terminal of the PMOS transistor MP5 serves as the input terminal of the second-stage gain stage circuit and is connected to the output terminal of the first-stage gain stage circuit, the source terminal of the PMOS transistor MP5 is connected to a power supply voltage, and the drain terminal of the PMOS transistor MP5 serves as the output terminal of the second-stage gain stage circuit, that is, the output terminal of the error amplifier.
In one embodiment, the buffer circuit includes: an N-type pressure-resistant tube MNA1, an N-type pressure-resistant tube MNA2, an NMOS tube MN5, an NMOS tube MN6 and a current source I1;
the drain ends of the voltage-resistant tube MNA1 and the voltage-resistant tube MNA2 are both connected with a power supply voltage, the gate end of the voltage-resistant tube MNA1 is connected with the gate end of the voltage-resistant tube MNA2, the connection position is used as the input end of the buffer circuit, the source end of the voltage-resistant tube MNA1 is connected with the drain end of the NMOS tube MN5, the source end of the NMOS tube MN5 is grounded, the gate end and the drain end of the NMOS tube MN5 are connected together, the gate end of the NMOS tube MN5 is also connected with the gate end of the NMOS tube MN6, the drain end of the voltage-resistant tube MN6 is connected with the source end of the NMOS tube MNA2, the source end of the NMOS tube MN6 is grounded, the first end of the current source I2 is connected with the power supply voltage, the second end of the current source I2 is connected with the gate end of the NMOS tube MN.
In one embodiment, the linear voltage stabilizing circuit further comprises an output resistor and an external capacitor, wherein a first end of the output resistor is connected with the output end of the linear voltage stabilizing circuit, a second end of the output resistor is connected with a first end of the external capacitor, and a second end of the external capacitor is grounded.
The linear voltage stabilizing circuit is additionally provided with the buffer circuit between the error amplifier and the power stage output circuit, and the control end current of the power stage output circuit is enhanced, so that the linear voltage stabilizing circuit has the capability of outputting large driving current, and the pole at the control end of the power stage output circuit and the pole at the output end of the error amplifier are pushed to high frequency when the driving current is high, so as to enlarge the distance between the poles and the main pole, increase the phase margin and improve the stability of the linear voltage stabilizing circuit. When the driving current is increased, the poles distributed at the output end of the first-stage gain stage circuit become dominant poles, and due to the compensation effect of the compensation circuit, the dominant poles can be further reduced to low frequency, and the zero point is increased, and the non-dominant poles can be compensated, so that the non-dominant poles can be pushed to high frequency, and further separation from the dominant poles is realized, and the system stability can be further improved.
In a second aspect, there is also provided an electronic device comprising a linear voltage regulating circuit as described in any of the above embodiments.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an equivalent small signal model of a linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a structure of a linear voltage regulator circuit according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of a linear voltage regulator circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a linear voltage regulator circuit according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The following embodiments and their technical features may be combined with each other without conflict.
As described in the background, the inventor has found that when the driving current output by the linear voltage regulator circuit is high, the size of the power transistor is increased, and a parasitic capacitance is generated, and when the parasitic capacitance is large to a certain extent, the pole distributed at the output end of the error amplifier becomes low, i.e. closer to the origin. Usually, the dominant pole is also close to the origin, and the poles distributed at the output end of the error amplifier become low, which is not favorable for realizing the separation from the dominant pole, and the phase margin is also reduced, so that the stability of the linear voltage stabilizing circuit system is reduced.
The embodiment of the invention provides a linear voltage stabilizing circuit, which can increase the phase margin when the driving current output by the linear voltage stabilizing circuit is high. Referring to FIG. 1, the linear voltage regulator circuit includes: the circuit comprises an error amplifier 110, a compensation circuit 120, a power stage output circuit 130, a current detection circuit 140 and a buffer circuit 160, wherein the error amplifier comprises a first stage gain stage circuit 112 and a second stage gain stage circuit 114, and an output end of the first stage gain stage circuit 112 is connected with an input end of the second stage gain stage circuit 114; a first terminal of the compensation circuit 120 is connected to the output terminal of the first stage of the gain stage 112, and a second terminal of the compensation circuit 120 is connected to the output terminal of the second stage of the gain stage 114; an output terminal of the second stage gainstage circuit 114 is connected to an input terminal of the buffer circuit 160 as an output terminal of the error amplifier 110, and an output terminal of the buffer circuit 160 is connected to a control terminal of the power stage output circuit 130; the output terminal of the power stage output circuit 130 is used as the output terminal out of the linear voltage regulating circuit to provide a driving current to power a load.
The buffer circuit 160 is used to improve the output capability of the unity gain to enhance the control end current of the power stage output circuit 130, so that the output end of the linear voltage regulator circuit provides a large driving current; the compensation circuit 120 is configured to compensate the poles distributed at the output end of the first-stage gain stage circuit 112, so as to reduce the poles distributed at the output end of the first-stage gain stage circuit 112, and generate zeros; the current detection circuit 140 is respectively connected to the output terminal of the linear voltage stabilizing circuit and the compensation circuit 120, and is configured to detect a driving current provided to the load by the output terminal of the linear voltage stabilizing circuit, and control the compensation circuit 120 to increase the zero point when the driving current increases to enter the heavy load mode.
In another embodiment, the output terminal of the first stage of the gain stage 112 has distributed poles for becoming non-dominant poles when the driving current is decreased to enter the light load mode, the output terminal of the linear regulator circuit has distributed poles for becoming dominant poles when the driving current is decreased to enter the light load mode, and the current detection circuit 140 is configured to control the compensation circuit 120 to reduce the zero point when detecting that the driving current becomes low.
The linear voltage stabilizing circuit increases the buffer circuit between the error amplifier and the power stage output circuit, and enhances the current of the control end of the power stage output circuit 130, so that the linear voltage stabilizing circuit has the capability of outputting large driving current, and can push the poles distributed at the control end of the power stage output circuit 130 and the poles distributed at the output end of the error amplifier to high frequency when the driving current is high, so as to enlarge the distance between the poles and the dominant pole, thereby increasing the phase margin and improving the stability of the linear voltage stabilizing circuit. When the driving current is increased, the poles distributed at the first-stage gain stage circuit 112 are reduced to be dominant poles due to the compensation effect of the compensation circuit, and the non-dominant poles increased at the output end of the linear voltage stabilizing circuit can be compensated by increasing the zero points, so that the stability of the linear voltage stabilizing circuit is improved, the non-dominant poles at the output end of the error amplifier can be pushed to high frequency, the non-dominant poles are further separated from the dominant poles, the phase margin is further increased, and the system stability can be further improved. In addition, when the driving current is low, the output resistance at the output end of the linear voltage stabilizing circuit is increased, the poles distributed at the output end of the linear voltage stabilizing circuit become dominant poles, and the dominant poles are closer to the original point along with the increase of the driving current, the first-stage gain stage circuit 112 generates lower frequency due to the compensation effect of the compensation circuit, the distance between the dominant poles and the non-dominant poles is reduced, the phase margin is smaller, the non-dominant poles can be compensated by reducing the zero point, the phase margin is improved, and the distance between the dominant poles and the non-dominant poles is increased, so that the stability of the system is ensured.
Therefore, by inserting the compensation circuit between the second stage gain stage circuit 114 and the first stage gain stage circuit 112 of the error amplifier 110, not only the poles distributed at the output terminal of the first stage gain stage circuit 112 can be compensated, but also the zero point can be dynamically adjusted according to the change of the driving current, so that the change of the zero point follows the change of the poles, thereby improving the stability of the system.
In one embodiment, referring to fig. 1, the compensation circuit 120 includes a first capacitor Cc1, a first resistor Rc1, a second capacitor Cc2, and an adjustable second resistor Rc2, a first end of the first resistor Rc1 is connected to a first end of the second resistor Rc2, a connection point serves as a first end of the compensation circuit 120 and an output end of the first-stage gain stage circuit 112, a second end of the first resistor Rc1 is connected to a first end of the first capacitor Cc1, a second end of the second resistor Rc2 is connected to a first end of the second capacitor Cc2, a second end of the first capacitor Cc1 is connected to a second end of the second capacitor Cc2, a connection point serves as a second end of the compensation circuit 120 and an output end of the second-stage gain stage circuit 114, and the current detection circuit 140 is connected to the second resistor Rc 2. The current detection circuit 140 may be configured to control the compensation circuit 120 to increase the resistance of the second resistor Rc2 to lower the zero point when the driving current is detected to be small. The current detection circuit 140 may be further configured to decrease the resistance of the second resistor Rc2 to increase the zero point when an increase in the driving current is detected.
Specifically, the compensation circuit 120 is a miller compensation circuit, and each of the first capacitor Cc1 and the second capacitor Cc2 may be a miller compensation capacitor.
Fig. 2 is a schematic diagram of an equivalent small signal model corresponding to fig. 1. When the load is light, namely the driving current provided by the linear voltage stabilizing circuit is small, the output resistor R generated at the output end of the linear voltage stabilizing circuitLThe larger the pole is, the pole distributed at the output end becomes the dominant pole P0, and as the driving current increases, the pole distributed at the output end of the first-stage gain stage circuit 112 of the error amplifier 110 becomes closer to the origin, the non-dominant pole P1 is the pole distributed at the output end of the first-stage gain stage circuit 112, but because the pole is compensated by the compensation circuit 120 and also moves to a low frequency, both the poles are lower, the phase margin is small, and the linear voltage regulating circuit is unstable. Therefore, when the second resistor Rc2 is increased during light load, a low frequency zero point Z0 can be obtained to compensate for the phase margin, and the stability of the linear voltage regulator circuit can be improved. The following are expressions of dominant pole P0 distributed at the output at light load, non-dominant pole P1 distributed at the output of first stage gain stage circuit 112, and zero Z0.
P0＝-1/(RL*CL)
P1＝-1/(gm2*R2*R1*(Cc1+Cc2))
Z0＝-1/(Rc1*Cc1+Rc2*Cc2)
In the above formula, P0 is the dominant pole, P1 is the non-dominant pole, and RLAnd CLThe output resistor and the output capacitor at the output terminal of the linear voltage regulator circuit, R1 is the output resistor of the first stage gain stage circuit 112, R2 is the output resistor of the second stage gain stage circuit 114, and gm2 is the transconductance of the second stage gain stage circuit 114. Rc1For compensating the resistance, R, of a first resistor in the circuitc2Is the resistance of the second resistor.
When the load is heavy, namely the driving current provided by the linear voltage stabilizing circuit is increased, the output resistor RLThe poles distributed at the output end of the linear voltage stabilizing circuit become higher and become a non-dominant pole P1, while the poles distributed at the output end of the first-stage gain stage circuit 112 of the error amplifier 110 become lower and become a dominant pole P0 due to compensation by a compensation circuit, and a zero is needed to compensate the higher non-dominant pole P1, so that the second resistor Rc2 is reduced, a zero Z0 which is shifted to high frequency compared with light load is generated to compensate the non-dominant pole P1, and the compensation circuit 120 is also beneficial to pushing the poles at the output end of the error amplifier 110 to high frequency, so that the separation from the dominant pole is realized, the phase margin is increased, and the stability of the system is improved. The following are expressions of the non-dominant pole P1 distributed at the output, the dominant pole P0 distributed at the output of the first stage gain stage circuit 112, and the zero Z0 under heavy load.
P0＝1/(gm2*R2*R1*(Cc1+Cc2))
P1＝1/(RL*CL)
Z0＝1/(Rc1*Cc1+Rc2*Cc2)
In the above formula, P0 is the dominant pole, P1 is the non-dominant pole, and RLAnd CLThe output resistor and the output capacitor at the output terminal of the linear voltage regulator circuit, R1 is the output resistor of the first stage gain stage circuit 112, R2 is the output resistor of the second stage gain stage circuit 114, and gm2 is the transconductance of the second stage gain stage circuit 114. Rc1For compensating the resistance, R, of a first resistor in the circuitc2Is the resistance of the second resistor.
In another embodiment of the present invention, referring to fig. 3, the linear voltage regulator circuit further includes a reference voltage output circuit 150 and an adjustable third resistor R3, a first end of the third resistor is connected to the output end of the reference voltage output circuit 150, a second end of the third resistor R3 is connected to the second end of the error amplifier 110, the reference voltage output circuit 150 is configured to output a reference voltage, the third resistor R3 outputs an adjustable reference voltage VREF to the second end of the error amplifier 110, a first input end of the error amplifier 110 is connected to the output end of the power stage output circuit 130 to access a feedback voltage at the output end of the power stage output circuit 130, and the feedback voltage and the output voltage of the power stage output circuit 130, that is, the output voltage of the linear voltage regulator circuit, have a magnitude of 1: 1.
In the embodiment, the reference voltage is adjustable, the feedback voltage and the output voltage of the linear voltage stabilizing circuit are 1:1, and the output voltage of the linear voltage stabilizing circuit is variable along with the change of the reference voltage, so that the adjustable output voltage of the linear voltage stabilizing circuit can be realized.
Further, referring to fig. 3, the linear voltage regulator circuit further includes a reference voltage filter circuit, the reference voltage filter circuit includes the adjustable third resistor R3 and a filter capacitor C3, a second terminal of the third resistor R3 is connected to a first terminal of the filter capacitor C3, and a second terminal of the filter circuit C3 is grounded.
The embodiment is beneficial to obtaining the reference voltage with low noise and high PSRR (Power supply rejection ratio) through filtering, thereby providing a front stage guarantee for improving the performance of the linear voltage-stabilizing circuit.
As for the first-stage gain stage circuit 112 of the error amplifier 110, which may be a differential input to single-ended output gain stage circuit, please refer to fig. 4, the first-stage gain stage circuit 112 of the error amplifier 110 may specifically include a PMOS transistor MP3, a PMOS transistor MP4, an NMOS transistor MN2, an NMOS transistor MN3, and an NMOS transistor MN 1; the source ends of the PMOS transistor MP3 and the PMOS transistor MP4 are both connected to a power supply voltage, the gate end of the PMOS transistor MP3 is connected to the gate end of the PMOS transistor MP4, the gate end of the PMOS transistor MP3 is connected to the drain end of the PMOS transistor MP3, the drain end of the PMOS transistor MP3 is connected to the drain end of the NMOS transistor MN2, the drain end of the PMOS transistor MP4 is connected to the drain end of the MOS transistor MN3, the gate end of the NMOS transistor MN2 serves as a second input end of the error amplifier to access a reference voltage, the source end of the NMOS transistor MN2 is connected to the source end of the NMOS transistor MN3, and the connection is connected to the drain end of the NMOS transistor MN1, and the gate end of the NMOS transistor MN3 serves as a first input end of the error amplifier 110 to access a voltage fed back from the output end of the linear voltage regulator circuit; the grid end of the NMOS tube MN1 is connected with a driving voltage, and the source end of the NMOS tube MN1 is grounded.
As for the second-stage gain stage circuit 114 of the error amplifier 110, which may be a common-source output gain stage circuit, referring to fig. 4, the second-stage gain stage circuit 114 of the error amplifier 110 specifically includes an NMOS transistor MN4 and a PMOS transistor MP 5; the drain terminal of the NMOS transistor MN4 is connected to the drain terminal of the PMOS transistor MP5, the gate terminal of the NMOS transistor MN4 is connected to the driving voltage, the source terminal of the NMOS transistor MN4 is grounded, the gate terminal of the PMOS transistor MP5 is used as the input terminal of the second-stage gain stage circuit 114 and is connected to the output terminal of the first-stage gain stage circuit 112, the source terminal of the PMOS transistor MP5 is connected to the power supply voltage, and the drain terminal of the PMOS transistor MP5 is used as the output terminal of the second-stage gain stage circuit 114, that is, the output terminal of the error amplifier.
Specifically, referring to fig. 4, the power stage output circuit 130 includes a P-type power transistor, a gate terminal of the P-type power transistor is used as a control terminal of the power stage output circuit 130, a drain terminal of the P-type power transistor is used as an output terminal of the power stage output circuit 130, and a source terminal of the P-type power transistor is used as a power source terminal of the power stage output circuit 130.
Specifically, the buffer circuit 160 includes: an N-type pressure-resistant tube MNA1, an N-type pressure-resistant tube MNA2, an NMOS tube MN5, an NMOS tube MN6 and a current source I1; the drain ends of the voltage-resistant tube MNA1 and the voltage-resistant tube MNA2 are both connected with a power supply voltage, the gate end of the voltage-resistant tube MNA1 is connected with the gate end of the voltage-resistant tube MNA2, the connection position is used as the input end of the buffer circuit 160, the source end of the voltage-resistant tube MNA1 is connected with the drain end of the NMOS tube MN5, the source end of the NMOS tube MN5 is grounded, the gate end and the drain end of the NMOS tube MN5 are connected together, the gate end of the NMOS tube MN5 is also connected with the gate end of the NMOS tube MN6, the source end of the voltage-resistant tube MNA2 is connected with the drain end of the NMOS tube MN6, the source end of the NMOS tube MN6 is grounded, the first end of the current source I2 is connected with the power supply voltage, the second end of the current source I2 is connected with the gate end of the NMOS tube MN 36.
In this embodiment, the buffer circuit 160 can output the error amplified signal to the control terminal (i.e., the gate terminal) of the power transistor MP6, and can also provide an additional output current to the gate terminal of the power transistor MP6, so as to enhance the on-characteristic of the power transistor MP6, and therefore the buffer circuit 160 can improve the output capability of the unit gain, and realize the output of a large driving current from the power stage output circuit.
In another embodiment of the present invention, as shown in fig. 5, the linear voltage regulating circuit further includes a voltage stabilizing capacitor, one end of the voltage stabilizing capacitor is connected to the output terminal of the linear voltage regulating circuit, and the other end of the voltage stabilizing capacitor is grounded. The voltage stabilizing capacitor is used for stabilizing the output voltage of the linear voltage stabilizing circuit, and the stability of the output voltage of the linear voltage stabilizing circuit can be improved. The voltage stabilizing capacitor can be a ceramic capacitor. Shown in fig. 5 is an equivalent circuit of the voltage stabilizing capacitor, including the capacitor Cr and its equivalent resistance Resr.
An embodiment of the present invention further provides an electronic device, including the linear voltage stabilizing circuit described in any of the above embodiments. The electronic equipment can be consumer electronic equipment such as a mobile phone, a computer and the like.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (11)

1. A linear voltage regulator circuit, comprising: the circuit comprises an error amplifier, a compensation circuit, a buffer circuit, a power level output circuit and a current detection circuit;
the error amplifier comprises a first-stage gain stage circuit and a second-stage gain stage circuit, wherein the output end of the first-stage gain stage circuit is connected with the input end of the second-stage gain stage circuit; the first end of the compensation circuit is connected with the output end of the first-stage gain stage circuit, and the second end of the compensation circuit is connected with the output end of the second-stage gain stage circuit; the output end of the second-stage gain stage circuit is used as the output end of the error amplifier and is connected with the input end of the buffer circuit, and the output end of the buffer circuit is connected with the control end of the power-stage output circuit; the output end of the power level output circuit is used as the output end of the linear voltage stabilizing circuit to provide a driving current for supplying power to a load;
the buffer circuit is used for improving the output capacity of the unit gain so as to enhance the current of the control end of the power stage output circuit;
the compensation circuit is used for compensating the poles distributed at the output end of the first-stage gain stage circuit so as to reduce the poles and generate zero points;
the current detection circuit is connected with the output end of the linear voltage stabilizing circuit and used for detecting the driving current provided by the output end of the linear voltage stabilizing circuit to the load and controlling the compensation circuit to increase the zero point when the driving current is detected to be increased to enter a heavy-load mode.
2. The linear voltage regulator circuit of claim 1, wherein the output of the first stage of the gain stage circuit has distributed poles for becoming non-dominant when the driving current decreases to enter the light load mode, the output of the linear voltage regulator circuit has distributed poles for becoming dominant when the driving current decreases to enter the light load mode, and the current detection circuit is further configured to control the compensation circuit to reduce the zero when detecting that the driving current decreases to enter the light load mode.
3. The linear voltage regulator circuit of claim 2, wherein the compensation circuit comprises a first capacitor, a first resistor, a second capacitor, and an adjustable second resistor, wherein a first terminal of the first resistor is connected to a first terminal of the second resistor, and the connection is connected to the output terminal of the first gain stage circuit as the first terminal of the compensation circuit, a second terminal of the first resistor is connected to the first terminal of the first capacitor, a second terminal of the second resistor is connected to the first terminal of the second capacitor, a second terminal of the first capacitor is connected to the second terminal of the second capacitor, and the connection is connected to the output terminal of the second gain stage circuit as the second terminal of the compensation circuit;
the current detection circuit is connected with the second resistor and used for controlling the compensation circuit to increase the resistance value of the second resistor to reduce the zero point when the driving current is small, and controlling the compensation circuit to decrease the resistance value of the second resistor to increase the zero point when the driving current is increased.
4. The linear voltage regulator circuit of claim 1, wherein the power stage output circuit comprises a P-type power transistor, a gate terminal of the P-type power transistor serves as a control terminal of the power stage output circuit, a drain terminal of the P-type power transistor serves as an output terminal of the power stage output circuit, and a source terminal of the P-type power transistor serves as a power supply terminal of the power stage output circuit.
5. The linear voltage stabilizing circuit of claim 1, further comprising a reference voltage output circuit and an adjustable third resistor, wherein a first terminal of the third resistor is connected to an output terminal of the reference voltage output circuit, a second terminal of the third resistor is connected to a second terminal of the error amplifier, the reference voltage output circuit is configured to output a reference voltage, the third resistor outputs the adjustable reference voltage to the second terminal of the error amplifier, a first input terminal of the error amplifier is connected to an output terminal of the power transistor to receive a feedback voltage at the output terminal of the power stage output circuit, and the feedback voltage and the output voltage of the power stage output circuit are 1: 1.
6. The linear voltage regulator circuit of claim 3, further comprising a reference voltage filter circuit including the adjustable third resistor and a filter capacitor, wherein a second terminal of the third resistor is connected to a first terminal of the filter capacitor, and a second terminal of the filter circuit is connected to ground.
7. The linear voltage regulator circuit of claim 1, wherein the first stage gain stage circuit of the error amplifier comprises a PMOS transistor MP3, a PMOS transistor MP4, an NMOS transistor MN2, an NMOS transistor MN3, and an NMOS transistor MN 1; the source ends of the PMOS tube MP3 and the PMOS tube MP4 are both accessed with power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP4, the gate end and the drain end of the PMOS tube MP3 are connected together, the drain end of the PMOS tube MP3 is connected with the drain end of the NMOS tube MN2, the drain end of the PMOS tube MP4 is connected with the drain end of the MOS tube MN3, the gate end of the NMOS tube MN2 is used as the second input end of the error amplifier to access reference voltage, the source end of the NMOS tube MN2 is connected with the source end of the NMOS tube MN3, the connection part is connected with the drain end of the NMOS tube MN1, and the gate end of the NMOS tube MN3 is used as the first input end of the error amplifier to access voltage fed back by the output end of the linear voltage stabilizing circuit; the grid end of the NMOS tube MN1 is connected with a driving voltage, and the source end of the NMOS tube MN1 is grounded.
8. The linear voltage regulator circuit of claim 6, wherein the second stage gain stage circuit of the error amplifier comprises an NMOS transistor MN4 and a PMOS transistor MP 5; the drain terminal of the NMOS transistor MN4 is connected to the drain terminal of the PMOS transistor MP5, the gate terminal of the NMOS transistor MN4 is connected to a driving voltage, the source terminal of the NMOS transistor MN4 is grounded, the gate terminal of the PMOS transistor MP5 serves as the input terminal of the second-stage gain stage circuit and is connected to the output terminal of the first-stage gain stage circuit, the source terminal of the PMOS transistor MP5 is connected to a power supply voltage, and the drain terminal of the PMOS transistor MP5 serves as the output terminal of the second-stage gain stage circuit, that is, the output terminal of the error amplifier.
9. The linear voltage regulator circuit of claim 6, wherein the snubber circuit comprises: an N-type pressure-resistant tube MNA1, an N-type pressure-resistant tube MNA2, an NMOS tube MN5, an NMOS tube MN6 and a current source I1;
the drain ends of the voltage-resistant tube MNA1 and the voltage-resistant tube MNA2 are both connected with a power supply voltage, the gate end of the voltage-resistant tube MNA1 is connected with the gate end of the voltage-resistant tube MNA2, the connection position is used as the input end of the buffer circuit, the source end of the voltage-resistant tube MNA1 is connected with the drain end of the NMOS tube MN5, the source end of the NMOS tube MN5 is grounded, the gate end and the drain end of the NMOS tube MN5 are connected together, the gate end of the NMOS tube MN5 is also connected with the gate end of the NMOS tube MN6, the drain end of the voltage-resistant tube MN6 is connected with the source end of the NMOS tube MNA2, the source end of the NMOS tube MN6 is grounded, the first end of the current source I2 is connected with the power supply voltage, the second end of the current source I2 is connected with the gate end of the NMOS tube MN.
10. The linear voltage regulator circuit of claim 6, further comprising an output resistor and an external capacitor, wherein a first terminal of the output resistor is connected to the output terminal of the linear voltage regulator circuit, a second terminal of the output resistor is connected to a first terminal of the external capacitor, and a second terminal of the external capacitor is grounded.
11. An electronic device comprising a linear voltage regulator circuit according to any of claims 1-10.
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